High-Performance In0.75Ga0.25AsImplant-Free n-type MOSFETs for Low Power Applications    J. S. Ayubi-Moak, K. Kalna and A....
Outline: • Motivation • Implant-Free (IF) MOSFET • Device Simulator & Results • Conclusions CDE-2009 Santiago de Compostel...
Motivation                     Transistor scaling and future options!                           (High Performance Logic)! ...
Motivation                        The performance is influenced by mobility and saturation velocity!                       ...
Motivation                                GGO is a good                               dielectric for III-Vs               ...
Implant-Free (IF) MOSFET                                                         VT controlled by workfunction           ...
(Real) 1µm gate IF MOSFETCDE-2009 Santiago de Compostela, Spain                                             7             ...
Monte Carlo Device Simulator                              Quantum confinement effects:                              • Effec...
Simulated IF III-V MOSFET                  GateSource                                Drain                                ...
Simulation Results Id-Vg                                           1760 μA/μm                                           16...
Simulation Results Id-Vg                                            5690 µS/µm                                           5...
Simulation Results                                         5.1×107 cm/s                                         4.9×107 cm...
Simulation Results                            2000                                               Lg = 15 nm               ...
Conclusions A fair comparison of different channel materials   requires careful consideration of all relevant effects. I...
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High-Performance In0.75Ga0.25As Implant-Free n-Type MOSFETs for Low Power Applications

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High-Performance In0.75Ga0.25As Implant-Free n-Type MOSFETs for Low Power Applications

  1. 1. High-Performance In0.75Ga0.25AsImplant-Free n-type MOSFETs for Low Power Applications J. S. Ayubi-Moak, K. Kalna and A. Asenov CDE-2009 Santiago de Compostela, Spain
  2. 2. Outline: • Motivation • Implant-Free (IF) MOSFET • Device Simulator & Results • Conclusions CDE-2009 Santiago de Compostela, Spain 2
  3. 3. Motivation Transistor scaling and future options! (High Performance Logic)! III-V device90nm Node 65nm Node 45nm Node prototype P1262 P1264 vision! (Research) 2003 P1266 2005 2007 32nm Generation P1268 22nm Generation 2009? P1270 2012? 50nm Length (Production) 40nm Length (Production) 35nm Length (Production) 27nm Length (Research) 22nm Length Uniaxial (Research) C-nanotube Nanowire Strain High-! /! Prototype Prototype (Research) (Research)SiGe S/D Metal Gate! Unrealistic 2008! Non-planar TriGate 2013-2022 FinFET (Research)CDE-2009 Santiago de Compostela, Spain 3
  4. 4. Motivation The performance is influenced by mobility and saturation velocity! (Low field current=charge*density*mobility*field)! Mobility is ~50 % down due to very short channels ! Higher mobility => Higher drive current! (Saturation current=charge*density*saturation velocity) Saturation velocity will differ in very short channels Higher saturation velocity => Higher drive current! Higher drive current enables lower operating voltages! Material Si Ge GaAs In0.53Ga0.47As InAs InSb Mobility [cm2/Vs] 1500 3900 8500 14000 25000 78000 vS [cm/s] 1!107 6 106 2 107 2.5 107 3.5 107 5 107 Manufacturability Co-IntegrationIII-V MOSFETs ? Low DOS Gate Dielectric The p-channel Doping activation CDE-2009 Santiago de Compostela, Spain 4
  5. 5. Motivation GGO is a good dielectric for III-Vs M. Passlack et al., IEEE EDL 23(9), 2002.CDE-2009 Santiago de Compostela, Spain Z. Yu et al., APL 82(18), 2003. 5
  6. 6. Implant-Free (IF) MOSFET  VT controlled by workfunction  Carriers confined in the channel  Volume inversion  UTB-like electrostatic integrity  Low resistance access regions  High injection velocity  High ballisticity  No thermal budget constraintsM. Passlack, Hartin, Ray, Medendorp, U.S. Patent 6 963 090, Nov. 8, 2005.M. Passlack et al., IEEE TED 53(10), 2006. CDE-2009 Santiago de Compostela, Spain 6
  7. 7. (Real) 1µm gate IF MOSFETCDE-2009 Santiago de Compostela, Spain 7 R. Hill et al., IEEE EDL 28 1080 (2007)
  8. 8. Monte Carlo Device Simulator Quantum confinement effects: • Effective quantum potential D. K. Ferry, Superlatt. Microstruct. 28(5-6) (2000). Included scattering mechanisms: • polar optical phonons • inter/intra-valley optical phonons • acoustic phonons • ionized impurities • alloy scatteringCDE-2009 Santiago de Compostela, Spain 8
  9. 9. Simulated IF III-V MOSFET GateSource Drain Thickness of [nm] Gate Length [nm] 30 20 15 High-κ dielectric 3 2 1.5 In0.52Al0.48As spacer 2 1 1 In0.53Ga0.47As spacer 1 0.5 0.5 In0.75Ga0.25As channel 5 5 5 In0.53Ga0.47As spacer 1 1 1 In0.52Al0.48As spacer 2 2 2 δ-doping 0.5 0.5 0.5 In0.52Al0.48As buffer 10 10 10 Semi-insulating substrate 500 500 500 CDE-2009 Santiago de Compostela, Spain 9
  10. 10. Simulation Results Id-Vg 1760 μA/μm 1600 μA/μm 1360 μA/μmCDE-2009 Santiago de Compostela, Spain 10
  11. 11. Simulation Results Id-Vg 5690 µS/µm 5100 µS/µm 3840 µS/µmCDE-2009 Santiago de Compostela, Spain 11
  12. 12. Simulation Results 5.1×107 cm/s 4.9×107 cm/s 3.9×107 cm/sCDE-2009 Santiago de Compostela, Spain 12
  13. 13. Simulation Results 2000 Lg = 15 nm 1800 y2 y1Cutoff Frequency fT (GHz) 1600 0.25 Lg = 20 nm Delay Time !T (ps) 0.2 1400 0.15 1200 0.1 avg ! y2 $ ! y2 $ Lg = 30 nm 0.05 1 10 2 10 v x = # ( nvx dy & # ( n dy & 1000 Gate Length Lg (nm) #y & #y & " 1 % " 1 % 800 Leff gate 100 150 200 250 300 350 400 1 dx DC Power Dissipation ( !W/!m) tT = = ( 2p fT π 0 v x ( x ) CDE-2009 Santiago de Compostela, Spain 13
  14. 14. Conclusions A fair comparison of different channel materials requires careful consideration of all relevant effects. IF InGaAs channel MOSFETs with high-Indium content offers ~2x performance improvement down to 15 nm channel length. The IF MOSFET attractive for low-power, high- performance CMOS circuits and applications.CDE-2009 Santiago de Compostela, Spain 14

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