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Track e magma redefining mixed so c chipex2011 - magma da

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  • 1. redefining Mixed System-on-Chip Design
    Rajeev Madhavan
    CEO and Chairman, Magma Design Automation
  • 2. Power
    System-on-Chip Complexity Continues to Rise
    Memory
    Computing
    Motorola DroidX
    More functionality
    Much more Analog IP
    Large, complex digital blocks
    Shorter time-to-market
    Multimedia
    NFC
    Connectivity
    Communication
    GPS
    Software
    Gyrometer
  • 3. SoC Example - 28nm 4G/3G Wireless Mobile Chip
    Chip Stats:
    Instances: ~20 Million
    Top Level: 3.5 Million
    Blocks: 25-30
    Block sizes: 100K – 1M cells
    Clocks: >70
    Frequency: 400MHz-1.5GHz
    Utilization: 70-80%
    Timing Scenarios: 70-80 
    10 Modes
    7 Corners
    Components
    Application Processor
    Modem
    Display & Imaging Support
    A/R Interfaces
    GSM
    GPS
    Memory
    Video CODEC
    RF Interfaces
    ADC
    DAC
    Graphics
    Audio CODEC
    Connectivity
    SDIO
    USB
    SIM
    GPIO
    Internal Functions
    Clock Generation
    Power Optimization
    Security
    PLL
    Analog
    Digital
    Mixed
  • 4. Challenges to Build this SoC
    Increasing Analog IP
    Increasing Digital Capacity & Complexity
    Final Signoff Closure
  • 5. Complexity Is Ever Increasing For Analog IP
    Complexity of analog IP has increased multiple fold
    Current design flows are manual and very iterative. Not scalable for increasing complexity of analog IP designed using advance process nodes
    Productivity has to be improved for next generation analog IP
  • 6. Analog IP Design Flows Have Not Evolved
    Traditional Iterative
    Analog Design
    Entire design flow must be manually repeated to accommodate any change in:
    Design Specifications & Constraints
    Process node
    Target Fab
    Each new derivative requires nearly complete redesign
  • 7. New Model-Based Analog Design
    Customized Analog IP
    Optimization Goals
    Circuit Models
    Target Specs
    SerDes
    Charge Pump
    Voltage Reg
    Opamps
    Layout
    Process Models (PDK)
  • 8. Analog Optimization – Multiple Specs in a Week
    PLL’s generated for many specs simultaneously (Frequency ranges, Jitter, Bandwidth, Area, Power etc.)
  • 9. Analog Optimization – Power vs Area
    Analog optimization provides quick tradeoffs of power and area for design exploration
    Example: Regulator circuit
    Analog optimization characterized on 5 corners
    Tradeoff 40% power reduction vs 50% area reduction
  • 10. Challenges to Build this SoC
    Increasing Analog IP
    Increasing Digital Capacity & Complexity
    Final Signoff Closure
  • 11. Digital Designs: Increasing Capacity
    Dramatic throughput needed
    10M
    Capacity-Driven
    Productivity Gap
    Flat Block Capacity
    (000s of Instances)
    3M
    1M
    500K
    Achievable Flat Block Capacity
    250K
    Needed Flat Block Capacity
  • 12. Limitations in Tool Capacity Create Risk
    500K
    500K
    1M
    Limitations force design teams to artificially break up design
    5 blocks, 10 blocks, 20 blocks, 50 blocks or more?
    Partitioning increases complexity – more iterations!!!
    Requires budgeting, clocks and interface timing closure
    Introduces schedule risks, requires more engineering resources
    1M
  • 13. Multi-Threading: Good, but not Good Enough
    Typical “sweet spot” for EDA multi-threading
    Number of cores/threads
  • 14. Current Digital Design Methodology
    80M Cells
  • 15. Multi-million cells/day throughput
    Design capacity per engineer up to 10M cells, flat!
    Place & Route
    Distributed Implementation
    (Master Process)
    4-5M
    Place & Route
    Place & Route
    1 – Implementation
    Engineer
    Place & Route
    Place & Route
    New Distributed Digital Design
  • 16. Benefit of Distributed Design
    Greatly increases designer productivity
    Leverages existing hardware and P&R licenses
    Implements bigger designs faster using existing engineering resources
  • 17. Design Example
    ~4M cells hierarchical design
    Redefined as flat and distributed across 8 servers
  • 18. Challenges to Build this SoC
    Increasing Analog IP
    Increasing Digital Capacity & Complexity
    Final Signoff Closure
  • 19. Final Signoff Closure Too Long
    ~50 days
    ~50 days
    8-20
    Iterations
    Final Netlist Closure: 100 days!
    3-5 days per iteration!
  • 20. New ZERO ECO Approach
    Best-in-class runtime for each tool  Improves TAT of each iteration
    Integrated flow  Fewer iterations
    Result: Faster Total Throughput
    20 days
    5 days
    5 days
    10 days
    Place & Route
    Multi-Processing
    Signoff
    Verification
    Final Netlist Closure: 40 days!
    1-2 days per iteration
  • 21. Summary
    Every SoC is Mixed Signal
    Every EDA tool must focus on Silicon first
    Mixed Signal SoC redefined  EDA must comprehend & solve new mixed signal challenges