Track e magma redefining mixed so c chipex2011 - magma da

580 views

Published on

Published in: Education, Technology, Business
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
580
On SlideShare
0
From Embeds
0
Number of Embeds
45
Actions
Shares
0
Downloads
5
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Track e magma redefining mixed so c chipex2011 - magma da

  1. 1. redefining Mixed System-on-Chip Design<br />Rajeev Madhavan<br />CEO and Chairman, Magma Design Automation<br />
  2. 2. Power<br />System-on-Chip Complexity Continues to Rise<br />Memory<br />Computing<br />Motorola DroidX<br />More functionality<br />Much more Analog IP<br />Large, complex digital blocks<br />Shorter time-to-market<br />Multimedia<br />NFC<br />Connectivity<br />Communication<br />GPS<br />Software<br />Gyrometer<br />
  3. 3. SoC Example - 28nm 4G/3G Wireless Mobile Chip<br />Chip Stats:<br />Instances: ~20 Million<br />Top Level: 3.5 Million<br />Blocks: 25-30<br />Block sizes: 100K – 1M cells<br />Clocks: >70<br />Frequency: 400MHz-1.5GHz <br />Utilization: 70-80%<br />Timing Scenarios: 70-80  <br />10 Modes<br />7 Corners<br />Components<br />Application Processor<br />Modem<br />Display & Imaging Support<br />A/R Interfaces<br />GSM<br />GPS<br />Memory<br />Video CODEC<br />RF Interfaces<br />ADC<br />DAC<br />Graphics<br />Audio CODEC<br />Connectivity<br />SDIO<br />USB<br />SIM<br />GPIO<br />Internal Functions<br />Clock Generation<br />Power Optimization<br />Security<br />PLL<br />Analog<br />Digital<br />Mixed<br />
  4. 4. Challenges to Build this SoC<br />Increasing Analog IP<br />Increasing Digital Capacity & Complexity<br />Final Signoff Closure<br />
  5. 5. Complexity Is Ever Increasing For Analog IP<br />Complexity of analog IP has increased multiple fold<br />Current design flows are manual and very iterative. Not scalable for increasing complexity of analog IP designed using advance process nodes<br />Productivity has to be improved for next generation analog IP<br />
  6. 6. Analog IP Design Flows Have Not Evolved <br />Traditional Iterative <br />Analog Design<br />Entire design flow must be manually repeated to accommodate any change in: <br />Design Specifications & Constraints <br />Process node<br />Target Fab<br />Each new derivative requires nearly complete redesign<br />
  7. 7. New Model-Based Analog Design<br />Customized Analog IP<br />Optimization Goals<br />Circuit Models<br />Target Specs<br />SerDes<br />Charge Pump<br />Voltage Reg<br />Opamps<br />Layout<br />Process Models (PDK)<br />
  8. 8. Analog Optimization – Multiple Specs in a Week <br />PLL’s generated for many specs simultaneously (Frequency ranges, Jitter, Bandwidth, Area, Power etc.)<br />
  9. 9. Analog Optimization – Power vs Area<br />Analog optimization provides quick tradeoffs of power and area for design exploration<br />Example: Regulator circuit<br />Analog optimization characterized on 5 corners<br />Tradeoff 40% power reduction vs 50% area reduction<br />
  10. 10. Challenges to Build this SoC<br />Increasing Analog IP<br />Increasing Digital Capacity & Complexity<br />Final Signoff Closure<br />
  11. 11. Digital Designs: Increasing Capacity<br />Dramatic throughput needed<br />10M<br />Capacity-Driven<br />Productivity Gap<br />Flat Block Capacity<br />(000s of Instances)<br />3M<br />1M<br />500K<br />Achievable Flat Block Capacity<br />250K<br />Needed Flat Block Capacity<br />
  12. 12. Limitations in Tool Capacity Create Risk<br />500K<br />500K<br />1M <br />Limitations force design teams to artificially break up design<br />5 blocks, 10 blocks, 20 blocks, 50 blocks or more? <br />Partitioning increases complexity – more iterations!!!<br />Requires budgeting, clocks and interface timing closure<br />Introduces schedule risks, requires more engineering resources<br />1M <br />
  13. 13. Multi-Threading: Good, but not Good Enough<br />Typical “sweet spot” for EDA multi-threading<br />Number of cores/threads<br />
  14. 14. Current Digital Design Methodology<br />80M Cells<br />
  15. 15. Multi-million cells/day throughput<br />Design capacity per engineer up to 10M cells, flat!<br />Place & Route<br />Distributed Implementation<br />(Master Process)<br />4-5M<br />Place & Route<br />Place & Route<br />1 – Implementation<br />Engineer<br />Place & Route<br />Place & Route<br />New Distributed Digital Design<br />
  16. 16. Benefit of Distributed Design<br />Greatly increases designer productivity<br />Leverages existing hardware and P&R licenses<br />Implements bigger designs faster using existing engineering resources<br />
  17. 17. Design Example<br />~4M cells hierarchical design<br />Redefined as flat and distributed across 8 servers<br />
  18. 18. Challenges to Build this SoC<br />Increasing Analog IP<br />Increasing Digital Capacity & Complexity<br />Final Signoff Closure<br />
  19. 19. Final Signoff Closure Too Long<br />~50 days<br />~50 days<br />8-20<br />Iterations<br />Final Netlist Closure: 100 days!<br />3-5 days per iteration!<br />
  20. 20. New ZERO ECO Approach<br />Best-in-class runtime for each tool  Improves TAT of each iteration<br />Integrated flow  Fewer iterations<br />Result: Faster Total Throughput<br />20 days<br />5 days<br />5 days<br />10 days<br />Place & Route<br />Multi-Processing<br />Signoff<br />Verification<br />Final Netlist Closure: 40 days!<br />1-2 days per iteration<br />
  21. 21. Summary<br />Every SoC is Mixed Signal<br />Every EDA tool must focus on Silicon first<br />Mixed Signal SoC redefined  EDA must comprehend & solve new mixed signal challenges<br />

×