A semiconductor memory system can experience hard failures from permanent physical defects or soft errors from random, non-destructive events that change memory cell contents without permanent damage. Error correcting codes add redundant bits when data is stored to detect and possibly correct errors by regenerating codes when data is read out and comparing them. ECC memory can detect common internal data corruption to prevent data loss in applications where reliability is critical.

1. ERROR CORRECTION
 A semiconductor memory system is subject to errors. These
can be categorized as Hard Failures and Soft Errors.
 Hard Failure
-permanent physical defect.
 Soft Error
-Random, non destructive events that alters the contents of one or more memory cells.
-No permanent damage to memory.
-Can caused by power supply problem.

2. Error Correcting Code Function
 When data are to be read into memory,
a calculation depicted as a function f is
performed on the date to produce a code.
 Both the code and the data are stores, thus if
an M-bit word of data is to be stored, and the
code is of length K bits, then the actual size of
the stored word in M+K bits.
 When the previously stored word is read out,
the code is used to detect and possibly correct
errors.
 A new set of K code bits is generated from
The M data bits and compared with the fetched
bits

3. Error Correcting Code Function
 The comparison yields one of the 3 results:
-No errors are detected. The fetched data bits
Are sent out.
-An error is detected, and it is possible to
correct the error. The data bits plus error
correction bits are fed into a corrector, which
produces a corrected set of M bits to be sent out.
-An error is detected, but it is not possible
To correct it. This condition is reported.
 A code is characterized by the number of
bits errors in a word that it can correct and
detect.

4. Hamming Error Correcting Code

5. ECC Memory
Error-correcting code memory (ECC memory)
is a type of computer data storage that can detect the most
common kinds of internal data corruption.
ECC memory used in most computers where data
corruption cannot be tolerated under any circumstances,
such as scientific or financial computing. *

6. What is Internal data corruption?
Data corruption refers to errors in computer data that occur during writing
reading, storage, transmission, or processing, which introduce
unintended changes to the original data.
Photo data corruption:

7. My Memory is ECC or Non-ECC?
For Windows 7 you can run the following command in command prompt:
wmic MEMORYCHIP get DataWidth,TotalWidth
If the Total Width value is larger than the Data Width value you have ECC memory.
Example output:
//ECC Memory
DataWidth TotalWidth
64 72
//Non-ECC Memory
DataWidth TotalWidth
64 64

8. My Memory is ECC or Non-ECC?
If you look at the physical memory module, ECC will usually have 9 (sometimes more) chips.
Non-ECC will have only 8 (or rarely, 8x2=16).

9. Advantages and Disadvantages of using ECC Memory
ADVANTAGES
 Data Integrity
 Easier Troubleshooting
 Advance Warning of Hardware Failure
DISADVANTAGES
 Greater Expense
 Harder to Find
 Occasional False Positives
 Performance Penalty For ECC

10. ECC RAM vs. Non-ECC RAM

11. ECC Failure Rate Analysis
ECC RAM is theoretically more stable and reliable than standard RAM, but many times theory does not match up with fact. To
see if ECC RAM really is more reliable, we looked up our failure rates for ECC and non-ECC RAM over the past 3 years.

12. Advanced DRAM Organization
 One of the most critical system bottlenecks when using high performance
processor is the interface to main internal memory
 The traditional DRAM chip is constrained both by its internal architecture and by
interface to the processor’s memory bus
 A number of enhancements to the basic DRAM architecture have been explored:

13. Synchronous DRAM (SDRAM)
 One of the most widely used forms of DRAM
 Exchanges data with the processor synchronized to an external clock signal and running at
the full speed of the processor/memory bus without imposing wait states
With synchronous access the DRAM moves data in and out under control of the system clock
 The processor or other master issues the instruction and address information which is
latched by the DRAM
 The DRAM then responds after a set number of clock cycles
 Meanwhile the master can safely do other task while the SDRAM is processing

14. Synchronous DRAM (SDRAM)

15. SDRAM Pin Assignments

18. Double Data Rate SDRAM (DDR SDRAM)
 SDRAM can only send data once per bus clock cycle
 Double-data rate SDRAM can send data twice per clock cycle, once on the
rising of the clock pulse and once on the falling edge
 Developed by the JEDEC Solid State Technology Association ( Electronic
Industries Alliance’s semiconductor engineering standardization body)

19. DDR SDRAM Road Timing
 RAS = row address select
 CAS = column address select
 DQ = data (in or out)
 DQS = DQ select
Double data rate SDRAM can send
data twice per clock cycle
 Rising edge
 Falling edge

20. DDR SDRAM for PCs

21. Cache DRAM (CDRAM)
 Developed by Mitsubishi
 Integrates a small SRAM cache onto a generic DRAM chip
 SRAM on the CDRAM can used in two ways:
 Cache mode of the CDRAM is effective for ordinary random access to memory
 Can also used as a buffer to support the serial access of a block of data

22. Types of DRAM
SDRAM
RDRAM
DDR SDRAM
CACHE DRAM