The 80386 introduced 32-bit processing to the 8086 family, improving performance. It had multiple internal units that operated in parallel. The 80386 came in several versions, including the full 80386DX and reduced bus 80386SX. In protected mode, the 80386 supported virtual memory, multitasking, and memory protection through descriptor tables, paging, and privilege levels. New features like control registers and the task register enabled these protected mode capabilities.
Evolution of microprocessors and 80486 Microprocessor.Ritwik MG
The document discusses the evolution of Intel x86 microprocessors from 80186 to 80486. It describes the key features and improvements introduced in each generation, including additional instructions, memory management capabilities, and on-chip cache in 80486. The 80486 is a 32-bit processor compatible with 80386 with enhanced performance due to its highly integrated design and 8KB internal cache. It has the same 4GB memory address space and register set as 80386 but provides faster execution through fewer clock cycles and additional instructions.
The document summarizes the Intel 80386 microprocessor, which was introduced in 1985. It discusses the key features and architecture of both the 80386DX and 80386SX versions. The 80386 was Intel's first 32-bit microprocessor and supported addressing up to 4GB of physical memory and 64TB of virtual memory using segmentation and paging. It had several operating modes and instruction sets to support multitasking and memory protection in protected mode.
The document discusses the Intel 80286 microprocessor. It was introduced in 1982 as the 5th generation of Intel's x86 family. It had several improvements over the 8086 including a faster clock speed of 12.5MHz, more transistors at 125K, and an advanced memory management system. The 80286 could address up to 16MB of memory and had two operating modes: real address mode for compatibility and protected virtual address mode for multitasking. It also introduced the ability to use virtual memory in protected mode.
The document summarizes the 80486 and Pentium microprocessors. It describes the key features and architecture of the 80486, including its on-chip cache, integrated floating point unit, and support for memory segmentation and paging. It then discusses the Pentium, noting it has a superscalar architecture, dynamic branch prediction, separate code and data caches, and a 64-bit data bus. The document provides pin diagrams and overviews of the architectures and workings of both processors.
The document discusses the Intel 80286 microprocessor. It introduces the 80286 as a 16-bit microprocessor introduced in 1982 with separate address and data buses. It had approximately 134,000 transistors and clock speeds up to 12.5 MHz. The 80286 supported both real and protected virtual addressing modes, advanced memory management, and was compatible with the 8086 instruction set. It had features like 4-level memory protection and could address up to 16MB of physical memory or 1GB of virtual memory.
The 80386 microprocessor has two versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications not requiring the full 32-bit bus of the 80386DX. It supports up to 4GB of virtual memory address space using segmentation and paging. The 80386 architecture includes a central processing unit, memory management unit, and bus interface unit. It has numerous features that enhance performance such as cache, pipeline processing, and floating point unit.
The Intel 80386 was a 32-bit microprocessor introduced in 1985 that represented a significant advancement over the 16-bit 8086. It had 32-bit registers and instructions, supported up to 4GB of physical memory and 64TB of virtual memory, and included memory management features like paging and segmentation for protection and virtual memory. The 80386's functional units included a bus interface for data transfer, an execution unit, and units for segmenting, paging, instruction decoding, and prefetching. It had various operating modes and registers to support both 32-bit and backward compatible 16-bit operations.
Evolution of microprocessors and 80486 Microprocessor.Ritwik MG
The document discusses the evolution of Intel x86 microprocessors from 80186 to 80486. It describes the key features and improvements introduced in each generation, including additional instructions, memory management capabilities, and on-chip cache in 80486. The 80486 is a 32-bit processor compatible with 80386 with enhanced performance due to its highly integrated design and 8KB internal cache. It has the same 4GB memory address space and register set as 80386 but provides faster execution through fewer clock cycles and additional instructions.
The document summarizes the Intel 80386 microprocessor, which was introduced in 1985. It discusses the key features and architecture of both the 80386DX and 80386SX versions. The 80386 was Intel's first 32-bit microprocessor and supported addressing up to 4GB of physical memory and 64TB of virtual memory using segmentation and paging. It had several operating modes and instruction sets to support multitasking and memory protection in protected mode.
The document discusses the Intel 80286 microprocessor. It was introduced in 1982 as the 5th generation of Intel's x86 family. It had several improvements over the 8086 including a faster clock speed of 12.5MHz, more transistors at 125K, and an advanced memory management system. The 80286 could address up to 16MB of memory and had two operating modes: real address mode for compatibility and protected virtual address mode for multitasking. It also introduced the ability to use virtual memory in protected mode.
The document summarizes the 80486 and Pentium microprocessors. It describes the key features and architecture of the 80486, including its on-chip cache, integrated floating point unit, and support for memory segmentation and paging. It then discusses the Pentium, noting it has a superscalar architecture, dynamic branch prediction, separate code and data caches, and a 64-bit data bus. The document provides pin diagrams and overviews of the architectures and workings of both processors.
The document discusses the Intel 80286 microprocessor. It introduces the 80286 as a 16-bit microprocessor introduced in 1982 with separate address and data buses. It had approximately 134,000 transistors and clock speeds up to 12.5 MHz. The 80286 supported both real and protected virtual addressing modes, advanced memory management, and was compatible with the 8086 instruction set. It had features like 4-level memory protection and could address up to 16MB of physical memory or 1GB of virtual memory.
The 80386 microprocessor has two versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications not requiring the full 32-bit bus of the 80386DX. It supports up to 4GB of virtual memory address space using segmentation and paging. The 80386 architecture includes a central processing unit, memory management unit, and bus interface unit. It has numerous features that enhance performance such as cache, pipeline processing, and floating point unit.
The Intel 80386 was a 32-bit microprocessor introduced in 1985 that represented a significant advancement over the 16-bit 8086. It had 32-bit registers and instructions, supported up to 4GB of physical memory and 64TB of virtual memory, and included memory management features like paging and segmentation for protection and virtual memory. The 80386's functional units included a bus interface for data transfer, an execution unit, and units for segmenting, paging, instruction decoding, and prefetching. It had various operating modes and registers to support both 32-bit and backward compatible 16-bit operations.
The document discusses the architecture and features of the Intel 80386 16-bit microprocessor. It describes the key components of the 80386 including the central processing unit with execution and instruction units, memory management unit, and bus interface unit. It also summarizes the 80386's addressing modes, registers, memory management, and real address mode of operation.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
The 80386 microprocessor was introduced by Intel in 1985. It had a 32-bit data bus and 32-bit address bus, allowing it to access up to 4GB of memory. It improved on the 80286 by including a memory management unit and paging capabilities. The 80386 operated in real, protected, and virtual modes and could address memory using various addressing modes including scaled indexed addressing. It had enhanced 32-bit registers and introduced debugging features like breakpoints using debug registers. Paging divided memory into fixed-size pages allowing more efficient memory management for multitasking systems.
The document discusses the Intel 80486 microprocessor chip. It was a 32-bit chip containing over 1.2 million transistors that operated between 20-100 MHz and was capable of 70 million instructions per second. The 80486 had 32-bit registers and data bus. It provided significantly improved performance over the 80386 through its 32-bit architecture and internal design.
The document discusses the features and architecture of the Intel 8086 microprocessor, including its 16-bit architecture, 20-bit address bus, instruction queue, segmentation of memory into four 64KB segments, registers, flag register, arithmetic logic unit, and various addressing modes. It also provides a comparison of the 8086 to the 8085 microprocessor and describes some applications of the 8086.
The document describes the architecture and functional units of the Intel 80486 microprocessor. It discusses the following key points in 3 sentences:
The 80486 contains various functional units like the BIU, code prefetch unit, instruction decoding unit, execution unit, FPU, segmentation unit, paging unit, and cache unit. It has register organizations like general purpose registers, segment registers, instruction pointer, and flag registers. The 80486 also includes special purpose registers like segment descriptor cache registers, system level registers, FPU registers, debug registers, and test registers that control various functions.
The document discusses the architecture of the Intel 80386 microprocessor, including its salient features such as supporting 32-bit data and addressing as well as virtual memory capabilities. It describes the functional blocks of the 80386 including the central processing unit, memory management unit, and bus control unit. Details are provided on the pin layout and specifications of the 80386 as compared to the earlier 8086 processor.
The document describes the architecture of the Pentium family processor. It discusses the Pentium processor's architecture including its 64-bit data bus, separate code and data caches, pipeline sequence, and superscalar execution using two pipelines. It also describes the Pentium's registers including the general purpose, segment, debug, and EFlags registers. Finally, it discusses the Pentium's bus description including the address bus, data bus, control bus, byte enables, and bus cycles.
The 80386 processor architecture is divided into three sections - the central processing unit (CPU), memory management unit (MMU), and bus interface unit (BIU). The CPU contains an execution unit with registers for handling data and calculating offsets, and an instruction unit that decodes instructions. The MMU manages memory using segmentation and paging, dividing physical memory into pages and virtual memory into segments and pages. It provides protection of system code and data. The BUI controls access to the system bus. The 80386 also features eight 32-bit general purpose registers that can be used as 16-bit registers, along with extended 32-bit versions of the BP, SP, SI, and DI registers.
The document discusses the architecture and components of microprocessors, specifically the Intel 80386 microprocessor. It describes the basic components of a microprocessor including the ALU, registers, buses, and control unit. It then provides details on the architecture of the 80386 including its registers, operating modes, and signal types.
The document discusses the architecture and features of the 16-bit Intel 80386 microprocessor. It describes the internal architecture including the central processing unit, memory management unit, and bus interface unit. The memory management unit uses segmentation and paging to translate virtual to physical addresses. The document provides details on the registers, addressing modes, operation in real and protected modes, and paging mechanism of the 80386 microprocessor.
The document discusses the Intel 80486 microprocessor. Some key points:
1) The 80486 is an evolutionary step up from the 80386, integrating the math coprocessor on the chip for faster performance.
2) It has an 8KB internal code and data cache, a floating point unit, and 168 pins in a pin grid array package.
3) The architecture includes address and data buses, cache control signals, and status flags in registers like the 80386. It supports protected mode with virtual memory and multitasking capabilities.
The Intel 80286 is the first microprocessor with memory management and protection abilities. It has a 16-bit data bus, 24-bit address bus, and can address up to 16MB of physical memory. Key features include virtual memory management, protection abilities through its integrated memory management unit, and two operating modes - real address mode and protected virtual address mode. The 80286 also introduced additional instructions for memory management and protection compared to earlier Intel processors.
The 80386 microprocessor was Intel's 32-bit processor introduced in 1985. It had several improvements over the 80286 including a 32-bit external data bus, increased virtual memory support up to 4GB using segmentation and paging, and faster instruction execution via parallel pipelining. The 80386 came in two versions - the 80386DX with a full 32-bit external data bus, and the lower-cost 80386SX which had a 16-bit data bus. It found use in personal computers and some embedded applications like early mobile phones and spacecraft due to its power and multitasking capabilities.
An 8086-based microcomputer system consists of the following components: 8086 CPU, ROM, RAM, peripherals, control bus, address bus, and data bus. The buses include the control bus which outputs signals like M/IO, RD, WR. The address and data buses are multiplexed and use latches to separate the address and data. The system also includes transceivers, a clock generator, and interrupt and DMA controllers. The 8086 can operate in minimum or maximum mode, with different control signal outputs in each mode. Read and write cycles take 4 clock cycles each and involve latching the address, then transferring/accepting the data.
This document describes the architecture of the 8086 microprocessor. It includes descriptions of the main components: the central processing unit containing the execution unit, instruction unit, memory management unit, and bus interface unit. It then provides details on the execution unit, instruction unit, memory management unit, addressing modes, pin diagram, and references used.
The document describes the pins of the 8086 microprocessor. It operates in either minimum or maximum mode depending on the state of the MN/MX pin. The AD0-AD15 pins are used for the lower 16-bits of addressing or data. The upper 4 address lines are multiplexed with status signals. The BHE/S7 pin is used for bus high enable during instruction execution.
The document summarizes key features of the Intel 80386 microprocessor. It discusses the two main versions - 80386DX and 80386SX, their address buses, data buses, and packaging. It then covers the internal architecture including the central processing unit, memory management unit, and bus interface unit. Finally, it discusses addressing modes and memory management in real and protected modes.
The document discusses the architecture and features of the Intel 80386 16-bit microprocessor. It describes the key components of the 80386 including the central processing unit with execution and instruction units, memory management unit, and bus interface unit. It also summarizes the 80386's addressing modes, registers, memory management, and real address mode of operation.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
The 80386 microprocessor was introduced by Intel in 1985. It had a 32-bit data bus and 32-bit address bus, allowing it to access up to 4GB of memory. It improved on the 80286 by including a memory management unit and paging capabilities. The 80386 operated in real, protected, and virtual modes and could address memory using various addressing modes including scaled indexed addressing. It had enhanced 32-bit registers and introduced debugging features like breakpoints using debug registers. Paging divided memory into fixed-size pages allowing more efficient memory management for multitasking systems.
The document discusses the Intel 80486 microprocessor chip. It was a 32-bit chip containing over 1.2 million transistors that operated between 20-100 MHz and was capable of 70 million instructions per second. The 80486 had 32-bit registers and data bus. It provided significantly improved performance over the 80386 through its 32-bit architecture and internal design.
The document discusses the features and architecture of the Intel 8086 microprocessor, including its 16-bit architecture, 20-bit address bus, instruction queue, segmentation of memory into four 64KB segments, registers, flag register, arithmetic logic unit, and various addressing modes. It also provides a comparison of the 8086 to the 8085 microprocessor and describes some applications of the 8086.
The document describes the architecture and functional units of the Intel 80486 microprocessor. It discusses the following key points in 3 sentences:
The 80486 contains various functional units like the BIU, code prefetch unit, instruction decoding unit, execution unit, FPU, segmentation unit, paging unit, and cache unit. It has register organizations like general purpose registers, segment registers, instruction pointer, and flag registers. The 80486 also includes special purpose registers like segment descriptor cache registers, system level registers, FPU registers, debug registers, and test registers that control various functions.
The document discusses the architecture of the Intel 80386 microprocessor, including its salient features such as supporting 32-bit data and addressing as well as virtual memory capabilities. It describes the functional blocks of the 80386 including the central processing unit, memory management unit, and bus control unit. Details are provided on the pin layout and specifications of the 80386 as compared to the earlier 8086 processor.
The document describes the architecture of the Pentium family processor. It discusses the Pentium processor's architecture including its 64-bit data bus, separate code and data caches, pipeline sequence, and superscalar execution using two pipelines. It also describes the Pentium's registers including the general purpose, segment, debug, and EFlags registers. Finally, it discusses the Pentium's bus description including the address bus, data bus, control bus, byte enables, and bus cycles.
The 80386 processor architecture is divided into three sections - the central processing unit (CPU), memory management unit (MMU), and bus interface unit (BIU). The CPU contains an execution unit with registers for handling data and calculating offsets, and an instruction unit that decodes instructions. The MMU manages memory using segmentation and paging, dividing physical memory into pages and virtual memory into segments and pages. It provides protection of system code and data. The BUI controls access to the system bus. The 80386 also features eight 32-bit general purpose registers that can be used as 16-bit registers, along with extended 32-bit versions of the BP, SP, SI, and DI registers.
The document discusses the architecture and components of microprocessors, specifically the Intel 80386 microprocessor. It describes the basic components of a microprocessor including the ALU, registers, buses, and control unit. It then provides details on the architecture of the 80386 including its registers, operating modes, and signal types.
The document discusses the architecture and features of the 16-bit Intel 80386 microprocessor. It describes the internal architecture including the central processing unit, memory management unit, and bus interface unit. The memory management unit uses segmentation and paging to translate virtual to physical addresses. The document provides details on the registers, addressing modes, operation in real and protected modes, and paging mechanism of the 80386 microprocessor.
The document discusses the Intel 80486 microprocessor. Some key points:
1) The 80486 is an evolutionary step up from the 80386, integrating the math coprocessor on the chip for faster performance.
2) It has an 8KB internal code and data cache, a floating point unit, and 168 pins in a pin grid array package.
3) The architecture includes address and data buses, cache control signals, and status flags in registers like the 80386. It supports protected mode with virtual memory and multitasking capabilities.
The Intel 80286 is the first microprocessor with memory management and protection abilities. It has a 16-bit data bus, 24-bit address bus, and can address up to 16MB of physical memory. Key features include virtual memory management, protection abilities through its integrated memory management unit, and two operating modes - real address mode and protected virtual address mode. The 80286 also introduced additional instructions for memory management and protection compared to earlier Intel processors.
The 80386 microprocessor was Intel's 32-bit processor introduced in 1985. It had several improvements over the 80286 including a 32-bit external data bus, increased virtual memory support up to 4GB using segmentation and paging, and faster instruction execution via parallel pipelining. The 80386 came in two versions - the 80386DX with a full 32-bit external data bus, and the lower-cost 80386SX which had a 16-bit data bus. It found use in personal computers and some embedded applications like early mobile phones and spacecraft due to its power and multitasking capabilities.
An 8086-based microcomputer system consists of the following components: 8086 CPU, ROM, RAM, peripherals, control bus, address bus, and data bus. The buses include the control bus which outputs signals like M/IO, RD, WR. The address and data buses are multiplexed and use latches to separate the address and data. The system also includes transceivers, a clock generator, and interrupt and DMA controllers. The 8086 can operate in minimum or maximum mode, with different control signal outputs in each mode. Read and write cycles take 4 clock cycles each and involve latching the address, then transferring/accepting the data.
This document describes the architecture of the 8086 microprocessor. It includes descriptions of the main components: the central processing unit containing the execution unit, instruction unit, memory management unit, and bus interface unit. It then provides details on the execution unit, instruction unit, memory management unit, addressing modes, pin diagram, and references used.
The document describes the pins of the 8086 microprocessor. It operates in either minimum or maximum mode depending on the state of the MN/MX pin. The AD0-AD15 pins are used for the lower 16-bits of addressing or data. The upper 4 address lines are multiplexed with status signals. The BHE/S7 pin is used for bus high enable during instruction execution.
The document summarizes key features of the Intel 80386 microprocessor. It discusses the two main versions - 80386DX and 80386SX, their address buses, data buses, and packaging. It then covers the internal architecture including the central processing unit, memory management unit, and bus interface unit. Finally, it discusses addressing modes and memory management in real and protected modes.
The 80386 microprocessor had two main versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications that did not require the full 32-bit capabilities of the 80386DX. The 80386 supported protected mode which enabled virtual memory, paging, and memory protection in addition to the capabilities of the 80286. It had enhanced registers, addressing modes, and memory management compared to earlier Intel processors.
The document describes the features and architecture of the Intel 80386 microprocessor. It discusses the two main versions - the 80386DX and 80386SX. The 80386DX has a 32-bit address and data bus while the 80386SX has a 24-bit address bus and 16-bit data bus. The document also describes the internal architecture of the 80386 which is divided into the central processing unit, memory management unit, and bus interface unit. It provides details on addressing modes, registers, protection rings, segmentation, paging, and virtual memory support in the protected mode of the 80386.
32- bit Microprocessor-Indtel 80386.pptxYuvraj994432
The document describes the architecture and features of the Intel 80386 microprocessor. It discusses the following key points in 3 sentences:
The 80386 has a 32-bit architecture divided into a central processing unit, memory management unit, and bus interface unit. It supports 32-bit registers, segmentation to access up to 64 terabytes of virtual memory, and pipelining to improve performance. The 80386 operates in real, protected, and virtual 8086 modes and uses segmentation and paging for memory management with protection levels to isolate programs and the operating system.
The document provides details about the 80386 processor architecture in real mode. It discusses the 80386 features, architecture, register set, memory addressing, and segmentation in real mode. The architecture of 80386 consists of the central processing unit, memory management unit, and bus interface unit. The central processing unit contains the instruction decoder and execution unit. The execution unit performs operations using the data unit, control unit, and test protection unit.
This document provides an overview of the 80386DX processor. It discusses the course objectives which are to learn the architecture, instruction set, and assembly programming of the 80386DX. The outcomes include being able to develop small real-life embedded applications using assembly language and understanding the architecture thoroughly. It then covers what a microprocessor is and provides details on the architecture, features, and memory organization of the 80386DX, including its segmentation unit, paging unit, and support for protected and virtual modes.
This presentation is about the design and function of a microprocessor, how to program and how to interface it with other electronics machines and devices
The document discusses the 8086 microprocessor architecture. It is a 16-bit microprocessor developed by Intel. Key points include:
- It has a 16-bit data bus and 20-bit address bus, allowing it to access up to 1 MB of memory.
- It uses memory segmentation to access more than 64KB of memory through segment registers and offsets.
- It has general purpose 16-bit registers including AX, BX, CX, and DX as well as other registers like the stack pointer and instruction pointer.
- It supports arithmetic, logical, and data transfer instructions on 16-bit operands as well as 8-bit operands.
- It can be configured in minimum or maximum mode depending
The document summarizes the Intel 80386 microprocessor. It describes the two main versions, the 80386DX and 80386SX, and explains that the SX was developed for applications that did not require the full 32-bit bus of the DX. It provides an overview of the key features of the 80386 like its 32-bit registers and address bus, support for segmentation and paging, protection levels, and use of coprocessors. The document also describes the internal architecture of the 80386 including its central processing unit, memory management unit, and bus interface unit. It explains how the 80386 supports virtual addressing through segmentation and paging to access up to 64 terabytes of virtual memory.
The document provides an overview of the syllabus for an Assembly Programming Language course. The syllabus covers 6 units: (1) 8086 microprocessor architecture, memory addressing, data types, and segment registers; (2) 8086 instruction set and addressing modes; (3) 8086 instructions for logic, shifts, flags, and flow control; (4) stack, subroutines, macros, and recursion; (5) 8086 I/O and the 8255 PPI; and (6) 8086 interrupt mechanism and the 8259 PIC. The course aims to teach students about 8086 organization, instruction formats, control flow, subroutines, I/O, and interrupts through 8086 programming exercises
This document provides information about microprocessors and microcontrollers, specifically the 8085 and 8086 microprocessors. It discusses the architecture, features, registers, addressing modes, instruction sets and interrupts of the 8085 and 8086 microprocessors. The 8085 is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. The 8086 is a 16-bit microprocessor designed by Intel that can access 1 megabyte of memory and has 14 registers. Both microprocessors have various addressing modes including immediate, register, direct, indirect and relative modes.
- Memory addressing refers to how operands are provided to instructions in memory. There are two types: non-memory addressing which uses predefined data or registers, and memory addressing which accesses data in memory.
- x86 processors use memory segmentation to divide memory into segments identified by segment registers and an offset. Real mode uses 16-bit segments while protected mode supports virtual memory and memory protection.
- x86 has various addressing modes like register, immediate, direct, register indirect, based, indexed, and based indexed addressing to access memory in different ways. These influence performance depending on whether memory is accessed.
The 8086 microprocessor is a 16-bit processor introduced by Intel in 1978. It has a 16-bit data bus and 20-bit address bus, allowing it to access up to 1MB of memory. The 8086 has an internal architecture divided into a Bus Interface Unit and an Execution Unit that can work simultaneously. The BIU handles external bus operations like fetching instructions and data from memory, while the EU decodes instructions and performs arithmetic/logical operations. The 8086 supports memory segmentation through the use of segment registers and pointers to generate 20-bit physical addresses.
The x86 instruction set architecture began with Intel's 16-bit processors in the 1980s and has since evolved through numerous extensions. It supports multiple execution modes including 16-bit real mode, 32-bit protected mode, and 64-bit long mode. The instruction format includes optional prefixes, opcode bytes, addressing fields, and immediate data. General purpose registers are used for operands along with memory addressing modes. Subsequent x86 architectures, such as AMD64, expanded register sizes and added new instructions while maintaining backwards compatibility.
This document provides an overview of the microprocessor, including its components, architecture, and features. It discusses the main components of a microprocessor like the ALU, register array, and control unit. It then describes the architecture and features of the 8085 microprocessor, including its registers, arithmetic logic unit, program counter, stack pointer, and pin diagram. It provides details on the address bus, data bus, control signals, and interrupts of the 8085 microprocessor.
The document provides information about the 8086 microprocessor including its registers, programming model, stack, pin details, and multiprocessor configurations. It discusses the following key points in 3 sentences:
The 8086 has general purpose registers (AX, BX, CX, DX) that can be used for temporary storage and operations. It uses a segmented memory model with code, stack, extra, and data segments. The 8086 can be used in minimum and maximum mode systems with different memory and I/O interfacing depending on the configuration.
2. Introduction:
• The 80386 family of microprocessors of Intel Corporation is the
first 32 bit version of the 8086 family-a switch from 16 bit to 32
bit
• 80386 has upward compatibility with 8086,8088,80286 etc
• The 80386 was launched in October 1985, but full-function chips
were first delivered in the third quarter of 1986
• Although it had long been obsolete as a personal
computer CPU, Intel and others had continued making the chip
for embedded systems.
• Used in aerospace technology
3. Versions of 80386
80386DX – the full version
• The first member in 80386 family
• this CPU could work with 16-bit and 32-bit external buses.
• Comprises of both 32-bit internal registers and 32-bit external bus.
80386SX –the reduced bus version
• low cost version of the 80386.
• This processor had 16 bit external data bus,32-bit internal registers and 24-bit external
address bus.
80386SL –
• low-power microprocessor with power management features, with 16-bit external data
bus and 24-bit external address bus.
• The processor included ISA bus controller, memory controller and cache controller.
Embedded 80376 and 80386EX processors.- Still in use today.
4. Internal Architecture
• To enhance performance 80386 has 6
functional units, processing in parallel:
– The bus unit
– The prefetch unit
– The decode unit
– The execution unit
– The page unit
– The segment unit
5.
6.
7. The Bus Unit
• The bus unit is the interface to the external devices.
• The bus interface unit provides a 32-bit data bus, a 3-bit
address bus and the signals needed to control transfers
over the bus.
• In fact, 8-bit, 16-bit and 32-bit data transfers are
supported.
• 80386 has separate pins for its address and data bus lines.
• This processing unit contains the latches and drivers for
the address bus, transceivers for the data bus, and control
logic for signaling whether a memory input/output, or
interrupt-acknowledgement bus cycle is to be performed.
8. The Prefetch Unit
• The prefetch unit performs a mechanism known as an
instruction stream queue.
• This queue permits a prefetch upto 16 bytes of instruction
code.
• Whenever the queue is not full, and the execution unit is
not asking the bus unit to read or write data from the
memory, the prefetch queue supplies addresses to the bus
interface unit and signals it to look ahead in the program
by fetching the next sequential instructions.
• Prefetched instructions are held in the FIFO queue for use
by the instruction decoder.
• Whenever bytes are loaded into the input end of the
queue, they are automatically shifted up through the
FIFO to the empty location near the output
9. The Decode Unit
• The decode unit accesses the output end of the
prefetch unit’s instruction queue.
• It reads the machine-code instructions from the
output side of the prefetch queue and decodes
them into microcode instruction format used by
the execution unit, thus it off-loads the
responsibility for the instruction decoding from
the execution unit.
• The instruction queue, a part of the decode unit
permits three fully decoded instructions to be
held waiting for use by the execution unit.
• Thus it improves the performance of the CPU.
10. The Execution Unit
• The execution unit involves the arithmetic/logic unit-
ALU, registers, special multiply, divide, and shift
hardware, and a control ROM.
• The control ROM contains the microcode sequences that
define the operation performed by each of the machine
code instructions.
• The execution unit reads the decoded instructions from
the instruction queue and performs the operations that
are specified.
• During the execution of an instruction, it requests the
segment and page units to generate operand addresses
and the bus interface unit to perform read or write bus
cycles to access data in memory or I/O devices
11. The Page and Segment Unit
• The segment and the Page units provide the
memory management and protection services for
the 80386.
• They offload the responsibility for address
generation, address translation and segment
checking from the bus interface unit and thereby
further boosting the performance of the CPU.
• The segment unit implements the segmentation
model of the 386 memory management.
• i.e. It contains dedicated hardware for performing
high speed address calculations, logical to linear
address translation and protection checks.
12. • The page unit implements the protected mode paging
model of the 80386’s memory management.
• It contains the translation look aside buffer that stores
recently used page directory and page table entries.
• When paging is enabled, the linear address produced by
the segment unit is used as the input to the paging unit.
• Here the linear address is translated into the physical
address of the memory or I/O location to be accessed.
Thus physical memory is the output to the bus interface
unit.
13. Real Address Mode Software
Model of the 80386DX
• Just like 80286, 80386DX comes up in the real address mode after it is
reset
• The CPU will remain in this mode unless it is switched to protected
mode by the software
• When in the real mode, the 80386DX can be used to execute the base
instruction set of the 8086/8088 architecture.
• Similar to 80286, object code for the base instructions of the 80386 is
identical to that of the 8086/8088. Thus code compatibility is
maintained between them.
• The real mode of the 386 generates the physical addresses in the
same way as in the 8086 or 80286.That is 16 bit segment register
contents and the 16 bit offset are used to generate the absolute 20 bit
physical address.
• Note: IP has 32 bits but in real mode only lower 16 bits are active.
14. REAL MODE SOFTWARE MODEL
OF 80386DX
• The register model of 80386dx is quite different from those of the
8088, 8086 and 80286.
• There are 17 internal registers that are used in the real mode
application programming.
• Nine of them –the data registers-(EAX, EBX, ECX and EDX), the
pointer registers (EBP and ESP), the index registers-(ESI and EDI)
and the flag register (EFLAG) - are identical to the corresponding
registers in the 8086’s software model except that they are now 32
bits in length.
• On the other hand the segment registers (CS, DS, ES and SS) and the
instruction pointers (IP) are both identical and still 16 bits in length.
• Several new registers are found in the real-mode 80386DX’s software
model.For instance, it has two more data segment registers, FS and
GS.
15. • Another new register is called the Control
Register Zero (CR0).
• The five least significant bits of this register are
called the machine status word-MSW and are
identical to the MSW of the 80286.
• The only bit in CR0 that is active in the real mode
is bit 0, which is the protection enable (PE) bit.
• PE is the bit used to switch the 80386dx from the
real mode to the protected mode.
• At reset, PE is set to Zero and thus Real mode is
selected at reset.
16. 80386 Specific Instruction Set:
• The base instruction set was enhanced in the 80286
microprocessor with a group of instructions known as the
extended instruction set.
• All these instructions are also available in the 80386 real
mode.
• The enhancement to the 80386dx’s real mode instruction
set is the 80386 specific instruction set.
• It includes instructions to directly load a pointer into the
FS, GS and SS registers.
• A number of special purpose instructions have been
added in the instruction set of 386.
17. Protected Address mode Software
Architecture of 80386dx
• When configured for the protected mode operation, the
80386dx microprocessor provides an advanced software
architecture that supports memory management, virtual
addressing, paging and multitasking. There are four new
registers in the protected mode model:
• The Global Descriptor Table Register(GDTR)
• Interrupt Descriptor Table Register(IDTR),
• Local Descriptor Table Register(LDTR)
• Task Register (TR)
18. 1.The Global Descriptor Table
Register-GDTR
• The contents of the GDTR define a table in the 80386dx’s physical
memory address space called the Global Descriptor Table, which is
one important element in the CPU’s memory management system.
• GDTR is a 48-bit register located inside the 80386DX to address GDT.
• The lower 2 bytes of the register, identified as the LIMIT, specify the
size in bytes of the GDT.
• The upper 4 bytes of the GDTR labeled as the BASE, locate the
beginning of the GDT in physical memory.
• This 32 bit address allows the table to be positioned anywhere in the
4 Gbyte linear address space.
• The GDT provides a mechanism for defining the characteristics of the
80386’s global memory address space. .
• i.e. Storage locations in the global memory is accessible by any task
that runs on the microprocessor.
• Only 1 GDT exists for all programs.
19. • This table contains what are called System segment Descriptors.
• These descriptors identify the characteristics of the segments of the
global memory.
• For instance, a segment descriptor provides information about the
size, starting point, and access rights of a global memory segment.
• Each descriptor is 8 bytes long. GDT can hold maximum up to 8192
descriptors.
• The value of BASE and LIMIT must be loaded into the GDTR before
the processor is switched from the real mode of operation to the
protected mode.
• Once in protected mode, the location of the table is not changed.
20.
21. 2.Interrupt Descriptor Table
Register
• Just like GDTR, the IDTR defines a table in the physical memory.
• The contents of the table are Interrupt Descriptors, not segment
descriptors.
• This register and table provide the mechanism by which the
microprocessor passes the program control to the interrupt and the
exception service routines.
• IDTR also is of 48 bits in length.
• Again, the lower two bytes define the size, and it also can be up to
65,536 bytes long.
• But 386 supports up to 256 interrupts and exceptions.
• The upper 4 bytes identify the starting address of the IDT in physical
memory.
• IDTR needs to be loaded prior to switching to the protected mode.
22. 3.Local Descriptor Table Register
• LDTR is also a part of the memory management support
mechanism.
• Each task can have access to its own private descriptor
table in addition to the GDT.
• The private descriptor table is called LDT and defines a
local memory address space for use by the task.
• The LDT holds segment descriptors that provide access to
the codes and the data in segments of memory that are
reserved for the current task.
• Since each task can have its own segment of local
memory, the protected mode can contain many LDT.
• LDTR is of 16 bit.
23. • The contents of the 16 bit LDTR do not directly
define the local descriptor table.
• Instead it holds a selector that points to an LDT
descriptor in the GDT.
• Whenever a selector is loaded into the LDTR, the
corresponding descriptor is apparently read from
the global memory and loaded into the LDT
cache within the processor.
• Every time the selector is loaded into the LDTR,
a local descriptor is cached and a new LDT is
activated.
24.
25. • In selector format, the two least significant bits
are RPL- Requested privilege level, which assigns
a privilege level to the selector.
• The next bit is identified as task indicator-TI,
which selects the table to be used when accessing
a segment descriptor.
• If TI is 0, the selector corresponds to a descriptor
in the GDT else LDT.
• The 13 most significant bits contain an index that
is used as a pointer to a specific descriptor entry
in the table selected by the TI bit.
26. 4. Control Registers
• The protected mode includes the 4 system control
registers, identified as CR0 to CR3.
• These are 32 bit registers.
• The lower 5 bits of the CR0 are system control flags.
• These bits make up what is known as the machine status
word-MSW.
• The most significant bit of the CR0 and registers CR2 and
CR3 are used by the 80386’s paging mechanism
• MSW bits of the CR0 contain PE, MP, EM, and R control
bits which define the protected mode system
configuration and status.
• The fifth bit TS, is a status bit.
27.
28.
29. Paging
• The Protected mode also supports the paged memory operation.
• Switching the PG bit in the CR0 to 1 turns on the paging.
• Now addressing of physical memory is implemented with an address
translation mechanism that consists of a page directory and page
table, which are both held in the physical memory.
• Control Register CR3 contains the page directory base register –
PDBR.
• This register holds a 20 bit page directory base address which points
to the beginning of the page directory.
• A page fault error occurs in the page translation process if page is not
present in the memory.
• In this case, the 80386dx saves the address at which the page fault
occurred in register CR2.
• This address is denoted as page fault linear address.
30.
31. The Task Register
• It is the key element in the protected mode task switching mechanism of the
80386dx microprocessor.
• This register holds a 16 bit index value called a selector.
• The initial selector must be loaded into TR under software control. This starts
the initial task.
• After this is done, the selector is changed automatically whenever the
processor executes an instruction that performs a task switch.
• The selector in TR is used to locate a descriptor in the GDT.
• When a selector is loaded into the TR, the corresponding Task State Segment
(TSS) descriptor automatically gets read from the memory and loaded into
the on-chip Task Descriptor Cache.
• This descriptor defines a block of memory called the Task state segment.
• It does this by providing the starting address (BASE) and the size-LIMIT of
the segment.
• Every task has its own TSS.
• The TSS holds the information needed to initiate a task, such as initial values
for the user accessible registers.
32. Registers with changed
functionality
• Register whose function changes when the 80386DX is switched to
protected mode is the flag register.
• The flag register is now identified as the EFLAGS and expands to 32
bits in length.
• 5 additional bits have been included here.
• 2 I/O privilege level-IOPL, the nested task flag-NF, The resume flag-
RF, the virtual 8086 mode flag-VM
33. VM - Virtual Mode Flag:
• If this flag is set, the 80386 enters the virtual 8086 mode within the
protection mode.
• This is to be set only when the 80386 is in protected mode.
• In this mode, if any privileged instruction is executed an exception 13
is generated.
• This bit can be set using IRET instruction or any task switch
operation only in the protected mode.
RF- Resume Flag:
• This flag is used with the debug register breakpoints.
• It is checked at the starting of every instruction cycle and if it is set,
any debug fault is ignored during the instruction cycle.
• The RF is automatically reset after successful execution of every
instruction, except for IRET and POPF instructions.
• Also, it is not automatically cleared after the successful execution of
JMP, CALL and INT instruction causing a task switch.
• These instructions are used to set the RF to the value specified by the
memory data available at the stack.
34. Test and Debug Registers
• Intel has provided a set of 8 debug registers for
hardware debugging.
• Out of these eight registers DR0 to DR7, two
registers DR4 and DR5 are Intel reserved.
• The initial four registers DR0 to DR3 store four
program controllable breakpoint addresses, while
DR6 and DR7 respectively hold breakpoint status
and breakpoint control information.
• Two more test register are provided by 80386 for
page caching namely test control and test status
register.
35. Multitasking and Protection
• It contains on-chip hardware that permits multiple tasks
to exist in a software system and allows them to be
scheduled for execution in a time-shared manner.
• Safeguards can be built into the protected mode software
system to deny the unauthorized access of a task’s
memory resource. This concept is called protection.
• The processor includes an on-chip hardware that
implements a protection mechanism.
• The mechanism is designed to put restrictions on the
access of local and system resources by a task and to
isolate tasks from each other in a multitasking
environment.
36. Physical Address Space and
Virtual to physical Address
Translation:
• As a part of the translation process, the memory management unit
determines whether or not the corresponding segment or page
already resides in the memory, the operation is performed on the
information.
• However if the segment or page is not present, it signals this
condition as an error.
• Once this condition is identified, the memory manager software
initiates loading of the segment or page from the external storage
device to the physical memory. This operation is called SWAP.
• That is an old segment or page gets swapped out of the memory and
then a new segment is swapped in the freed space in the physical
memory.
37.
38. Summary
• The Instruction unit decodes the opcode bytes received from the 16-byte instruction code queue and arranges
them in a 3- instruction decoded instruction queue.
•After decoding them pass it to the control section for deriving the necessary control signals. The barrel shifter
increases the speed of all shift and rotate operations.
• The multiply / divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time.
•Even 32- bit multiplications can be executed within one microsecond by the multiply / divide logic.
•The Memory management unit consists of a Segmentation unit and a Paging unit.
•Segmentation unit allows the use of two address components, viz. segment and offset for relocability and sharing of
code and data.
•Segmentation unit allows segments of size 4Gbytes at max.
•The Paging unit organizes the physical memory in terms of pages of 4kbytes size each.
•Paging unit works under the control of the segmentation unit, i.e. each segment is further divided into pages. The
virtual memory is also organizes in terms of segments and pages by the memory management unit.
•The Segmentation unit provides a 4 level protection mechanism for protecting and isolating the system code and data
from those of the application program.
•Paging unit converts linear addresses into physical addresses.
•The control and attribute PLA checks the privileges at the page level. Each of the pages maintains the paging
information of the task. The limit and attribute PLA checks segment limits and attributes at segment level to avoid
invalid accesses to code and data in the
memory segments.
•The Bus control unit has a prioritizer to resolve the priority of the various bus requests. This controls the access of the
bus. The address driver drives the bus enable and address signal A0 – A31. The pipeline and dynamic bus sizing
unit handle the related control signals.
•The data buffers interface the internal data bus with the system bus.