ESD protection

Power IC용 ESD Protection Technology
구 용서 ( Yong-Seo Koo )
Electronic Engineering
Dankook University, Korea
yskoo@dankook.ac.kr
031-8005-3625

2
Outline
• Introduction
• Summary
• ESD Protection Design for Power IC
• High Voltage ESD Device Solution for Power IC
• ESD Circuit Solution for Power IC
• Whole Chip ESD Protection Circuit Design
• Low Voltage ESD Device Solution for Power IC
• Basic Design of ESD Protection Circuit
• ESD Technology Issue

4
What is ESD ?
Material A Material B
Material
Contact
Material A Material B
Material
Separation
ESD is a process in which charge is transferred
from one object to the other
• Discharge event due to tribo-electrically generated charges.
• ESD is a high-current (~Amps) and short-duration (~ns) stress event
10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 1
CDM MM
HBM
Typical
EOS
DC
overstress
ESD
EOS
TIME IN SECONDS (Log Scale)

5
Distribution of Failure Model in ICs
• Of all the failed microchip, about 35% as called by the ESD, resulting in a loss of
several 100 million$ to the industry every year.
• ESD protection is a very high priority for IC reliability.

6
Transistor gate oxide
damage typical for CDM
with low leakage
Metal damage
Junction breakdown Oxide breakdown
Via damage
Transistor Via damage
under PS-mode MM 300V
ESD Damage in ICs
Transistor drain to source
melt filament under HBM

7
ESD Control Methods
• Fab Level :
– Use of air ionizers, electrostatic handling procedures for the wafers during fabrication
• Process Level :
– Modifications to the process technology to build-in ESD robustness to the transistors
• Component/Chip Level :
– On-chip protection design at the signal pins connected to the package
• Package Level :
– Proper grounding methods during packaging
• Test Level :
– Proper handling methods during testing and shipping the parts
• System Level :
– Proper shielding methods once the packaged chip is placed on the board

8
Model of ESD Events (Component-Level)
HBM (Human Body Model)
Standard :
1. EOS/ESD association standard STM.5.1
2. JEDEC STD JESD22-A114D
3. MIL-STD 883E
CHBM
RHBM Ls
RL
DUT
V
HBM
Cs
CHBM=100pF, RHBM=1.5kΩ
CS=1.5pF, LS=8uH
1.5
1
0.5
0
0 50 100 150 200
I
HBM
[A]
Time [ns]
HBM 2kV 기준
Ipeak = 1.33A
Rise Time = 2~10ns

9
MM (Machine Model)
Standard :
1. EOS/ESD association standard STM.5.2
2. JEDEC STD JESD22-A114-A
R
Ls
RL
DUT
V
ESD
CMM=200pF, LS=750nH
CMM
I
MM
[A]
Time [ns]
2
0
4
-4
-2
0 50 100 150 200
MM 200V 기준
Ipeak = 2.8~3.5A
Rise Time = 15~30ns

10
CDM (Charge Device Model)
Standard :
1. EOS/ESD association standard STM.5.3.1
2. JEDEC STD JESD22-C101-A
RL
Ls
RCDM
DUT
CCDM
CCDM=10pF, RL=10Ω, LS=10nH
Time [ns]
0 50 100 150 200
10
8
6
4
2
0
-2
-4
CDM 500V 기준
Ipeak = 8A
Rise Time = < 1ns

11
Model of ESD Events (System-Level)
IEC 61000-4-2
VIEC = 8kV 기준
Ipeak = 30A
Rise Time = 0.7 to 1ns
• Under IEC 61000-4-2, it specifies that
Direct Contact Discharge is used
Whenever the discharge is to metal
For repeatability
• Direct Air Discharge is only used
when metal is not exposed.
• IEC 61000-4-2 Level 4 Direct Contact
Discharge is ± 8kV
Level Test Voltage
First Peak
Current of
Discharge
(±10%)
Rise Time
Current (±30%)
at 30ns
Current (±30%)
at 60ns
1 2KV 7.5A 0.7ns to 1ns 4A 2A
2 4KV 15A 0.7ns to 1ns 8A 4A
3 6KV 22.5A 0.7ns to 1ns 12A 6A
4 8KV 30A 0.7ns to 1ns 16A 8A Market Trend

12
Transmission Line Pulse
• An Effective Analysis Tool for ESD Mechanism
- Analysis of On-Chip ESD Protection Devices
• Used by IC Designers since 1985 (T.J. Maloney@INTEL) to evaluate ESD Protection Schemes.
• Simulates HBM/MM/CDM with very Short Pulses.
• High Current Time Domain Reflectometry Techniques.
• Merits of TLP
- Produce an I-V Curve for ESD Conditions
- Effective ESD Analysis Tool
• Demerits of TLP
- Correlation Issue between Package-Level ESD and TLP ESD
- Not recommended as en Evaluation Tool for ESD Level
Component-Level ESD Normal TLP Vf-TLP
Model HBM MM CDM ≈ HBM ≈ MM ≈ CDM
Pulse Width [ns] > 150 60 ~ 80 ~ 1 100 30 1.25
Rise Time [ns] 2 ~ 10 2 ~ 20 < 0.4 10 10 0.2

13
TLP test method
High Voltage
Power Supply
Sampling
Head
uA Leakage
Current
Mesurement
Current
Measurement
50 Ohm load
Differential
Measurement
0 - 5V
5V supply
DUT ( Probe Station )
Digital Storage OSC
Interface
Data
Acquisition
Board
USB
50 Ohm TL
USB
USB
• TLP test has become one of the standard tools
for ESD characterization in the HBM region
with pulse duration of about 100ns

14
Transient-Induced Latch-up
• System-level ESD events, electromagnetic coupling, or hot plug of ICs, can induced fast
transient noises on I/O pins and Power supply lines, which can of HV ICs.
Fail
Pass
< Transient Latch-up Test Block Diagram>

2. Basic Design of ESD Protection
Circuit

ESD Design Key Parameter
• Process Parameters
– Wafer Type : SOI vs. Bulk (EPI or Non-EPI)
– Doping Profile (Vertical & Lateral) : Junction Breakdown Voltage
– Silicide Process
– Oxide Thickness : Oxide Breakdown Voltage
– Contact Size and Metal Thickness & Resistance
• Layout Parameters
– DCGS & SCGS : ESD Device Area Scaling Effect
– Silicide Blocking
– ESD Scheme : IO ESD & Power Clamp Scheme, CDM Device
– Vdd-to-Vss Decoupling Capacitor
– Package Type : Wire-Bonding Package or Flip-Chip Package
• Wire-Bonding Package : PAD Limit or Core Limit
• Flip-Chip Package : Peripheral Type or Area Type

17
• The ESD clamp must not trigger
- under normal circuit operation condition
• The ESD clamp must trigger
- below the oxide breakdown voltage Vox
• Another Condition
- The Lower Ron (on-state R), The Better @within ESD Windows
• The condition of ESD design window
Vdd + 10% < Vclamp =< Vt1 < Vt2 < Vox
• The design window gets narrower with down-scaling Tech.
- The margin between junction and oxide breakdown voltage is
decreasing dramatically and eventually crossed the junction
breakdown voltage.
- New trigger mechanism will have to be found which no longer
rely in the junction breakdown.
- Dynamic trigger schemes suggest reduced trigger voltage voltage.
Current
Voltage
Supply
voltage
range
margin
Oxide
Break-
down
ESD design
window
Vsp Vt1
Vt2
It2
Ron
ESD Device Design Window

18
• Resistor (diffusion, well, poly resistors)
• Diode (p-n junction)
• Thick-oxide (Gate-oxide) NMOS/PMOS
• Parasitic vertical / lateral bipolar junction transistor
• Parasitic SCR device (p-n-p-n structure)
• SCR Based Device (LVTSCR, DTSCR..)
• Capacitor / Inductor
Design of ESD Protection Devices

ESD Design Flow
Finish Layout & Tape out
Schematic Entry
Latch up Check
Yield Analysis
Nominal Design
ESD Check
Layout Entry
Leakage Check
LVS
DRC
DFM Check
Latch up Check
ESD Check
Parasitic Extraction
Latch up Check
Yield Analysis
Nominal Design
Top Level Block
Level

20
Basic Design of ESD Clamp
VSS
I/O
Pins
:ESD Clamp :Parasitic Diode :ESD (Surge)
Internal
Circuit
IC Chip
• To protect the IC from such high voltage pulses, ESD clamps are placed
between every I/O pin and power supply pin.
• ESD clamps turn on only when an ESD pulse is detected
And turn off during normal operations.
VDD
VSS
I/O Clamp
Power Clamp

21
ESD Protection Circuit
PAD Based ESD Protection
• ESD current is directly shunted from the I/O pin to GND.
• ESD device exists on every I/O pad between the pad and the ground.
• ESD protection devices are usually snapback devices.

22
ESD Protection Circuit
Rail Based ESD Protection
• ESD current is redirected to the VDD power rail and then shunted to GND by a power clamp.
• Bus resistance from I/O pins to the power clamps should be accurately estimated.

23
• Large remote clamps are placed in power pad cells only
Total VDD line Resistance =RVDD X N (I/O pad Num)
Large
Clamp
Rvdd
VDD
VDD PAD
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
Large
Clamp
Rvdd
VDD
VSS PAD
VSS
VSS
Primary Path
Remote rails clamp network
ESD Protection Circuit Design Strategy

24
• I/O pads contain the diode and small clamps.
• Large clamps in power pad cells to terminate the bus segment
Large
Clamp
Rvdd
VDD
VDD PAD
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
I/O PAD
Rvdd
Large
Clamp
Rvdd
VDD
VSS PAD
VSS
VSS
Primary Path
Small
Clamp
Small
Clamp
Small
Clamp
Small
Clamp
Small
Clamp
Small
Clamp
Small
Clamp
Distributed rails clamp network
ESD Protection Circuit Design Strategy

26
ESD Protection Trend
High ESD Level
• Direct stress to the chip : Memory controller Card ( HBM 4kV ), Touch Screen Controller ICs( HBM 8kV )
• Absorption of system level ESD : Timing Controller ( IEC 6kV ) , Display Driver ICs( IEC 20kV )
- Cost Reduction and Reliability Improvement
- Realization of ESD Specification for Chip Size Shrink
High Voltage ICs
• With the rapidly increasing demands on High Voltage ICs in field application
- Automotive Electronics, PMICs, LED & LCD Driver ICs
• Latch up Issue in HV ICs
ESD Network Analysis
• Mixed Signal , Multiple power supply
New System-Level ESD
• CDE (Cable Discharge Event), HMM(Human or Hand Metal Model), System-Level ESD Induced Flicker Noise
High Speed
• Display Port ( 2.7Gpbs ), HDMI (2.5Gbps ), RF IC, LVDS ( 2Gpbs )

27
Process Technology
• ESD Design Window
 ESD design window shrinks with new CMOS tech.
• Gate Oxide Downscaling
 Transient oxide breakdown voltage is decreasing faster with technology advancement.
Low Voltage ESD Protection Issue

28
※ LDD and Silicide seriously degrade ESD robustness of NMOS
< Effect of LDD on ESD robustness of NMOS > < Effect of Silicide thickness on ESD robustness of NMOS >
Process Technology

29
• As technology scale down, the value of trigger voltage (VT1) should be less than the oxide
breakdown voltage.  Gate Triggering Technique, Substrate Triggering Technique
• Non-Uniform turn-on behavior among the multi-finger of the ggNMOS
The Issue of the GGNMOS
A B
C
D

30
High Voltage ESD Protection Issue
High Voltage ESD Protection Device
• Various HV Applications (Motor control, Power Management and Conversion ..)
 High Voltage devices have been widely used in IC products.
• Though these applications represent fast growth markets, the underlying silicon process
technologies lack standardized high performance ESD solutions.
a. Basic SCR
b. HV-GGNMOS
c. GCNMOS
d. HV-GGPMOS
e. GCPMOS
f. Reverse Diode
a
b
c
d
e
f
• Basic SCR
- Superb ESD characteristics (low leakage & cap.)
- require careful high holding voltage
• HV-NMOS/NPN
- Basic ESD protection Device
- Degradation issues due to non-uniform triggering
- latch-up weakness due to low holding voltage
• RC-N/P-MOS (BigFET)
- Very large area consumption, Low HBM level
• HV-PMOS/PNP
- Characteristic similar to the Reverse diode
- ESD performance is very process dependent.
• Reverse Diode
- Latch-up immune ESD device
- Very higher capacitance and leakage than others.

• ESD Performance Comparison
High Voltage ESD Protection Device

Holding Voltage Engineering
Operation
Range
VDD
VH
VH Engineering
VT
• In HV ICs, the Power Supply(VDD) can be over ten volts, a few ten of volts, or even higher.
 Requirements for automotive IC, e.g. 5V, 20V, 45V, 60V
• Low doping implants to obtain the high breakdown voltage
 Low doping concentrations strongly impact the snapback behavior.
•Due to the high operating voltage in applications of HV devices,
all clamps have a high enough holding voltage above VDD.
After transient trigger
40V
< Transient Latch-up Test >

Area Efficiency
• In HV ICs, HV-ESD protection Device typically leading to very large area consumption
 Large Leakage Current, Large Capacitance
• HV-ESD solutions for the Power IC focus on smallest area HV-ESD protection design
 Small pad pitch, Small ESD device size
• Circuit Under Pad (CUP) is useful to reduce the ESD protection circuit area
Clamp Layout
It2
(mA/um2)
HBM
(V/um2)
LV-MOS
Stack
Non-Silicide 0.24 > 0.56
LV-MOS
Stack
Silicide 0.63 > 0.56
RC-
MOSFET
Min Cap. 0.11 0.66
< Comparison of the current capability per unit area>
Diode
RC-
MOS
PMOS/
PNP
NMOS/
NPN
SCR
Area ★ ★ ★★ ★★★ ★★★★★
< Comparison of general High Voltage ESD Device>
PAD
PAD
LV-ESD
LV-ESD
LV-ESD
LV-ESD
< LV I/O Clamp & HV Power Clamp in Power IC>
HV-ESD

4. ESD Protection Design
for Power IC

*Gate Grounded NMOS
LV ESD Device Solution for Power IC (MOS Tech)
• Conventional NMOS Device
• Area for local protection : 5950um²
• 0.35um BCDMOS process
Trigger Voltage : 8.1V
Holding Voltage : 5.96V
It2 : 3.1A
HBM Level : 3.7kV
MM Level : 400V
<Layout View> <TLP I-V Curve>

*Substrate Trigger NMOS
Gate Length : 0.8um
Width : 60um
Finger : 12
Total Area :3000 um2
• Proposed NMOS Device
• Low trigger voltage and Uniformity using Substrate Trigger Technique
• Very Low Trigger Voltage
It2 : 3.14A
HBM Level : 5kV
MM Level : 450V
<Schematics>

*Fast-Substrate Triggering BiCMOS
• Proposed BiCMOS Device
• Very Low Trigger Voltage, Fast Turn-on Speed
• 0.13um CMOS process
<Layout View>
<Schematics>
<TLP I-V Curve>
<Turn-On>
It2 : 2.3A
HBM Level : 3kV
MM Level : 210V

*Dynamic-Body Floating NMOS
Sub-Triggering PMOS
Gate-Triggering NMOS
Main NMOS
Resistor
Resistor
• Proposed MOS Device
• Dynamic Trigger Voltage using MOS’s Floating Technique
• The body of Main NMOS floats and base potential of the parasitic bipolar transistor in the
GGNMOS increases
• 65nm CMOS process
• Small area for local protection : 3500um²
• HBM: 8kV, MM: 800V
It2 : 4.05A

*HHVSCR (High Holding Voltage SCR)
LV ESD Device Solution for Power IC (SCR Tech)
• High holding voltage, Latch-up immunity
• Effective ESD performance by SCR based Device
• Extended p+ cathode diffusion and the additional n-well region
• Power Clamp for 10V
• Small area for local protection : 2565um²
<Layout View>
<TLP I-V Curve>
It2 : 6.6A
HBM Level : 8kV
MM Level : 720V

40
*PTSCR (P-Substrate Triggered SCR)
• Proposed SCR based Device
• MOS Trigger technique and SCR operation
• Low triggering voltage, High holding voltage, High Holding Current Latch-up immunity
Trigger Voltage : 8~10V
Holding Voltage : 5~7V
It2 : 6~7A
HBM Level : 8kV
MM Level : 940V

41
VDD
GND
I/O I/O
ND PD
PS NS
One-direction
VDD
GND
I/O I/O
ND PD
PS NS
Dual-direction
I
V
I
V
BVOX
BVOX
BVOX
BVOX
Design
window
Design
window
VDD
GND
I/O I/O
ND PD
PS NS
One-direction VDD
GND
I/O I/O
ND PD
PS NS
One-direction
VDD
GND
I/O I/O
ND PD
PS NS
Dual-direction VDD
GND
I/O I/O
ND PD
PS NS
Dual-direction
I
V
I
V
BVOX
BVOX
BVOX
BVOX
Design
window
Design
window
ESD path
<<Dual Direction SCR – Simulation I-V Curves >>
*Dual Directional SCR

42
Modified NPN Bipolar
• N-type Buried Layer( N-BL) Engineering
 The lower effective n-bl doping reduces the intrinsic electric avalanche field in the collector-base junction
under high current conditions
 More external voltage needs to be applied to maintain the self-biased NPN snapback operation
 The effect of holding voltage increase due to a larger n-bl dilution
• A snapback below the operation voltage would result in a large static current through the ESD
device and a consequent EOS damage.
HV ESD Device Solution for Power IC (NPN Tech)

Robust High Voltage Clamp for LDMOS
HV ESD Device Solution for Power IC (MOS Tech)
• Imbedded SCR in the LDMOSFET
• Holding Voltage Control  Imbedded SCR Length, Nwell Length
• Overcome ESD weakness of LDMOSFET
Imbedded SCR

44
Modified LDMOSFET (1)
• Layout arrangement for LDMOS with poly-bending
• Grounded P+ slots between the N+ drain (collector)
and P+ source (base) of LDMOS, the P+ slots can
shunt the avalanche-generated hole to ground 
Hole current to forward bias the P-Body underneath
the N+ source  turn-on behavior of BJT inherent
in the LDMOS can be effectively suppressed ESD
stresses.
• HBM(MM) ESD protection level was improved from
0.75kV (50V) to 2.75kV (225V)
<cross-sectional view> <TLP measurement I-V curve of LDMOS with poly-bending>
<layout top view>

45
< Device cross-sectional view of LDMOS>
PBI
• The PBI (P-type boron implant) layer under the source-
side N+ region
• Electron density ejected source side  Increased the
holding voltage of LDMOS
(a) (b) (c)
< TLP measured I-V curves>
< Layout top view of nLDMOS with (a) type-A, (b) type-B, and (c) type-C>
• 0.5um BCD Process
PBI

46
46
< Cross-sectional view >
• ESD protection structure with novel trigger
technique for LDMOS
• The same structure as drain region in LDMOS,
the vertical NPN transistor and the lateral
transistor
• The avalanche current acts as the base current
of NPN transistor.
• The IT2 value is nearly four times as large as
that of the simple LDMOS < TLP I-V characteristics>
< TLP I-V characteristics with small and large R1 resistance>
• 0.6um BCD Process

47
47
• Inserting some dot P+ diffusions into the source  enough Rbulk &
decrease the device dimension
• Instead of a long strip N+, the dot N+ diffusions  the positive
temperature coefficient resistor RN+ to compensate the resistance
decrease caused by the Rrsurf
• Eliminate the current crowding effect
• 0.35um HV BCD Process
< TLPI-V characteristics of HV-LDMOS>
< Cross-sectional & layout of the HV-LDMOS>
(a)
< (a)Two scheme to increase the R-bulk, (b) layout >
(b)
TW HBM MM Vt1 It2
Conventional
HV-LDMOS
360um 0.5kV 50V 34V 0.28A
New structure
HV-LDMOS
360um 5kV 550V 28V 2.74A

48
48
• Effective methods to increase ESD robustness of ESD protection device
is the substrate-triggered technique
• In order to effectively inject the trigger current into the p-body of LDMOS
(base of n-p-n BJT)  waffle-layout style
• Increase It2 from 0.41A to 0.95A
• 0.5um 16V BCD Process
(a) (b)
< Layout top view (a) stripe, (b) waffle-layout style>
(a)
(b)
< TLP measured (a) I-V curves (b) multiple-zapping reliability >

49
Segmented SCR
N-Ext P-Ext
N+ P+ N+ P+
N-Ext P-Ext
N+
P+
N+
P+
P+
P+
P+
P+
P+
N+
N+
N+
N+
N+
• SCR structure with high holding voltage ( ~ 40V )
 Reduced the emitter injection efficiency of the parasitic BJTs in the SCR.
• Latch-up immunity and high failure current for ESD robustness
< Conventional > < Segmented SCR >
HV ESD Device Solution for Power IC (SCR Tech)

50
HV ESD Device Solution for Power IC (Stacking Tech)
*Stack NMOSFET
• GGNMOSFET Stacking Technique
• Power Clamp for >12V
• 0.35um CMOS process
Anode
Cathode
VT1 VH IT2 HBM Cell size
Default 10V 7V 3.2A 4.1KV 53umX80um=4240um2
2 stack 21.5V 15V 2.95A 4KV 107umX80um=8560um2
3 stack 31.5V 26.5V 2.9A 4KV 162umX80um=12960um2
4 stack 42V 36.5V 2.8A 4KV 216umX80um=17280um2
Anode
Cathode

*Stack ST-NMOS
• n-Stack ST-NMOS using Stacking Technique
• Low trigger voltage as the forward bias base-emitter junction of the parasitic bipolar transistor
• Power Clamp for 10~40V Power IC applications
using Stacking Technique
<Layout View>
Default 4.6V 4.43V 2.4A 5kV 88umX84um=7392um2
2 stack 15.1V 15.1V 4.24A 6.5kV 167umX84um=13776um2

<TLP measurement as D3 variation >
<Single Device> <SCR vs Proposed SCR>
<n-Stack Device>
<n-Stack TLP Measurement>
<Conventional SCR>
<Proposed SCR>
• SCR’S Stacking Technique
• Power Clamp for 20V~40V
• 0.6um Bi-CMOS Process
Stack SCR

*Stack HHVSCR
• Power Clamp for High Voltage Power IC
• SCR Device using Stacking Technique
<Layout View>
Default 14.06V 11.28V 7.62A 8kV 24um X 60um=1448um2
2 stack 26.31V 22.55V 7.05A 7kV 50um X 60um=3000um2
3 stack 40.79V 34.94V 6.01A 7kV 80um X 60um=4800um2
4 stack 57.02V 55.14V 4A 7kV 104um X 60um=6240um2
60um
24um
60um
24um

Stack BJT
• BJT’S Stacking Technique
Trigger Voltage : 79V
Holding Voltage : 69V
It2 : 8.3A
Area : 110um * 240um
HBM Level : 12kV
Single Bipolar
Triple Stack Bipolar
<BJT Stack Schematic>

55
*LIGBT (Lateral Insulated Gate Bipolar Transistor)
HV ESD Device Solution for Power IC (IGBT Tech)
• High holding voltage, Latch-up immunity
• Effective ESD performance by using IGBT technique
Trigger Voltage: 85V
Holding Voltage: 68V
Trigger Voltage: 93V
Holding Voltage: 81V
Trigger Voltage : 85~93V
Holding Voltage : 68~81V
It2 : 9.2~9.9A
HBM Level : >8kV
MM Level : >800V
<LIGBT Layout>

56
• Power IC’s use two or more voltage domain
 Use on-chip charge pump circuitry to generate additional voltage levels
 Logic, Control Block, High voltage for power conversions
 Consider of all pin to pin combination for discharging current for effective ESD protection
Control
Block
High Voltage
for power conversions Logic
VDD1
GNDA
VDD2 VDD3
GNDD
ESD Protection Strategy
ESD Circuit solution for Power IC

57
ESD Protection Scheme for Mixed Supply Voltage
In In
Circuit I Circuit II
VSS-LV
Power
Clamp
Power
Clamp
Out Out
VDD-LV
VSS-HV
VDD-HV
ESD Cell
ESD Clamp Coupling Diode
:HV ESD Clamp :Parasitic Diode
:LV ESD Clamp
:Coupling Diode

58
 An ESD Voltage occurs on a low voltage input pin with an high voltage
input pin grounded, but all the low and high voltage power pins are floating.
• Internal ESD damage Due to Pin to Pin ESD Stress in a CMOS IC with the
Separated Power Pins
I/O I/O
VDD-L
VSS-L
VDD-H
VSS-H

59
I/O I/O
VDD-L
VSS-L
VDD-H
VSS-H
Power
Clamp
Power
Clamp
2nd Clamp
• Power protection network requires a set of power clamps between VDD and VSS
busses and back-to-back diode.
• To reduce the large voltage build-up between different power domain, second
clamp is used

60
ESD Protection Scheme with ESD Buses
Circuit I Circuit II Circuit III
ESD
Conduction
Circuit
ESD
Conduction
Circuit
ESD
Conduction
Circuit
ESD
Conduction
Circuit
ESD
Conduction
Circuit
ESD
Conduction
Circuit
Power-Rail
ESD
Clamp
Circuit
Power-Rail
ESD
Clamp
Circuit
Power-Rail
ESD
Clamp
Circuit
Power-Rail
ESD
Clamp
Circuit
VDD1
VSS1
VDD2
VSS2
VDD3
VSS3
VDD ESD Bus
VSS ESD Bus

61
Whole Chip ESD Protection Circuit Design
R
T
PAD
PAD
VREF
Block
(1.2V)
I REF
Block
M1 M2 M3 M4
M5 M6
M7 M8
Q1 Q2
M9
Cc
Rc
RFB2
RFB1
LVDS
Driver
External
ESD
Ring
ESD
Ring
• I/O Frequency 1.1Ghz ( < 0.5pF )
• HBM 4kV, MM 400V
• PAD to PAD Space: 30um
• VCC ring: 30um, VSS ring: 15um
• I/O, Power Clamp: SCR type Device (50umX 60um)
*ESD Protection Circuit for the LVDS Driver
ESD Protection
LVDS Driver
PAD
ESD Protection
LVDS Driver
Power
Clamp
Power
Clamp
I/O I/O
I/O
I/O
VSS
VSS
VCC
LVDS Driver
SCR SCR SCR SCR
SCR
SCR

*ESD Protection Scheme for PMIC
Requirement:
• HBM 4kV, MM 400V
• Area (<1000um2)
• VDD ring: 30um, VSS ring: 30um
• The use of ggNMOS based ESD device

63
*ESD Protection Circuit for Touch Screen Driver IC
• I/O Frequency 1.1Ghz ( < 0.5pF )
• ESD Protection Device: PTSCR
• HBM >7kV, MM >600V , IEC61000-4-2 4kV
• Area (BPAD: 70umX70um, Device: 50umX 70um
<HBM 7kV PASS> <HBM 8kV FAIL>
< Layout Top-view >
< ESD Device DC-IV curve after HBM zap tester>
PTSCR
DIODE
BPAD

64
*ESD Protection circuit for LED Driver IC
• HBM 8kV, MM 800V Pass
• Area (< 2600um2)
• Output current per channel : 100mA
• The use of SCR based ESD device
IO & Power
ESD Device
Design Factor
HHVSCR Width = 57um, Length = 45um

ESD Protection Circuit for UXGA/HDTV LCoS
• LCoS Panel Spec
- Resolution: 1920(+24) X 1200(+24)
- Frame rate: 120Hz
- Display area: 1 inch
• ESD Spec
- HBM: above 3.5kV, MM: 200V
• I/O Device: GGNMOS, GDPMOS
• Power Clamp: R-C Field Oxide Device
<Layout Top View of HV and LV I/O>

• The ESD device solution for Power ICs :
66
Summary
• Power IC’s ESD Strategy : Area efficiency, Latch-up immunity, ESD
robustness, Consider of all pin to pin combination
• ESD Technology Trend : High ESD Level, High Speed,
High Voltage Device, ESD Network Analysis, Process Technology
• ESD protection is a very high priority for Power ICs reliability
- Low Voltage : MOS, SCR based ESD Protection Device etc.
- High Voltage : LDMOS, SCR, IGBT, Stack based ESD Protection Device etc.

ESD protection

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to ESD protection

Similar to ESD protection (20)

Recently uploaded

Recently uploaded (20)

ESD protection