The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new, G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity, and latency, which is found to be 0.52
m2, 387 and 1 respectively. In addition, the complete energy dissipation analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage outputs than its counterparts circuits, which ensure more scalable.

1. ARTICLE
Copyright © 2016 by American Scientific Publishers
All rights reserved.
Printed in the United States of America
Journal of Nanoengineering and Nanomanufacturing
Vol. 6, pp. 1–16, 2016
(www.aspbs.com/jnan)
Designing Conservative Reversible N-Bit Binary
Comparator for Emerging Quantum-Dot Cellular
Automata Nano Circuits
Neeraj Kumar Misra1,∗
, Bibhash Sen2
, and Subodh Wairya3
1
Department of Electronics Engineering, Institute of Engineering and Technology, Lucknow, India
2
Department of Computer Science and Engineering, National Institute of Technology, Durgapur, India
3
Department of Electronics Engineering, Institute of Engineering and Technology, Lucknow, India
ABSTRACT
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conser-
vative reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2
, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
KEYWORDS: Reversible Logic, Conservative Reversible Gate, Reversible Comparator, Quantum Cost,
Latency, Quantum-Dot Cellular Automata.
1. INTRODUCTION
In the area of low power digital integrated circuit, there
are numerous applications of reversible logic. A reversible
gate is m number of inputs and m number of outputs,
the bijective maps of each binary logic input pattern to
a unique binary logic output pattern. Reversible logic has
attracted a great deal of intention due to no energy wastage.
A logic computation is reversible in nature, if the out-
put logic includes adequate data to reconstruct the input
logic, no data bits are erased. The quantum logic circuit
design is inherently reversible. The major difficulty is the
optimizing of the reversible metrics caused by the synthe-
sization of the circuits.1
To acquire the reversible metric
optimization is commonly employed gate count, constant
inputs, garbage outputs and quantum cost. Constant input
is the ones that choose to a fixed amount (either 1 or 0).
A garbage corresponds to the output whose functionality
∗
Author to whom correspondence should be addressed.
Email: neeraj.mishra@ietlucknow.ac.in
Received: 29 July 2016
Accepted: 13 October 2016
is not a contribution to the circuit. A quantum cost can
be synthesized by primitive quantum gates (CNOT gate,
controlled-V and controlled-V+
gate). The counting of
primitive quantum gates gives the quantum cost.
The CMOS circuit design in the nanometer scale range
has primary limitations such as MOS transistor width (W),
length (L) and short channel effect that cause degrada-
tion of the device performance. To overcome the problems
the research moved towards nanoelectronics.2
Due to the
advancement of quantum computing in nano-electronics,
it becomes essential to consider their trustworthiness of
quantum-dot cellular automata (QCA). Recently QCA
general theorems have promised the principle of low
power, high device density, high switching speed and high
operating frequency (THz).
The comparator circuit is widely used and play a sig-
nificant role in various applications such as digital sig-
nal processing and ALU design. Therefore, to reduce the
quantum cost of comparator circuit efficiently is significant
to lower the cost of ALU or processor.3 4
This work of the
conservative reversible comparator (CRC) which optimizes
the reversible metrics like gate count, garbage outputs and
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2. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits Misra et al.
ARTICLE
quantum cost compared to the state of the art circuits.
To the best of our state of the art reviews, there is no such
conservative reversible comparator in QCA computing.
In this paper, we introduce a more scalable version of
the modular approach based conservative reversible com-
parator (CRC). Here, we have separated the CRC into
three modules. The first module, utilize PPC gate, the sec-
ond module utilizes PPPNG-2 and BVPPG and the third
module utilizes PPNG-2. Further, we demonstrate a more
scalable circuit of n-bit CRC. This circuit is motivated by
the same size of the n-bit CRC.5
The major constraints for
this circuit are more gate count, quantum cost and realized
in conventional CMOS technology. The presented CRC in
this article achieves the optimal values of reversible met-
rics such as gate count, garbage outputs, and quantum cost.
In the optimization, there is an achievement of all the met-
rics improves. The primary interest in this work is both
in logic reversible synthesis prospect as well as a physi-
cally reversible prospect. The physical reversibility check-
ing in emerging nanoscale, Quantum cellular automata
(QCA) because reversible logic has prospective application
in logic design in QCA.6
The PPC gate layout in QCA is
forming a 1-bit comparator results with the strong value
of polarization in simulation waveform and only 1 latency
reported here.
In this paper, we attempt to construct a CRC in
QCA framework. The major outlines of this workaround
reversible-QCA circuit can be concise as follows:
• We have proposed scalable conservative reversible gates
(PPC, PPNG-1, and PPNG-2), for reversible computing
application.
• We present the architecture level representation of 1-bit,
2-bit and n-bit CRC around proposed conservative gates.
• We have compared proposed circuit with other n-bit
CRC that used the previous circuit.
• We estimate and analyze the scalability of 2-bit com-
parator than its existing, 33.33% improvement regarding
gate count.
• We implement the smaller robust structure of PPC in
QCA framework. During simulation, the result is ensured
by comparison with the truth table of PPC.
• We dissect the QCA layout of PPC, the similar QCA
layout of the 1-bit comparator is utilized.
• We estimate the gate used with a 1-bit comparator and
present latency of 66.66% over counterparts circuits.
• We dissect the thermal-layout map of PPC using
QCAPro version 1.3. The physical reversibility is trying to
maintain by according to the thermal layout. The design of
the PPC is concluded by physically irreversible, but logi-
cally reversible.
• We extracted the energy dissipation related parameters
from exhaustive studies. To indicate the low power feature
in this work.
• We estimate the average output node cell polarization
value over a different temperature range. By simulation,
setup results proved that average output polarization value
decrease slowly with the increase in the temperature.
The article is organized as follows: Section 2 gives an
overview of the state of the art and the basics of reversible
logic and QCA. Section 3, three new reversible gates are
introduced with minimum quantum cost. Section 4, we
elaborate the circuit of the binary n-bit comparator. Also
details, the algorithm presented. Section 5 presents the
QCA design of PPC gate and details of simulation setup
results. Section 6, elaborate the energy dissipation analy-
sis. Section 7, estimation of temperature versus polariza-
tion is reported. The conclusion and reference are shown
in Sections 8 and 9.
2. BASICS AND STATE-OF-THE-ART
This section includes the basics of reversible logic, con-
servative reversible logic, QCA, and kink energy.
2.1. Reversible Logic Gate
The reversible logic gate has numbers of input signals
equals to the number of output signals and there is
a bijective-mapping between its input and output lines.
In reversible computing technology, minimizing the gate
count, garbage outputs, constant inputs and quantum cost
are main demand of syntheses. The circuit constructed
from reversible gates will be using feedback, acyclic, fan-
outs and loops are not allowed.7
The reversible logic is
adopted with two elucidates as follows:
(a) Logical reversibility: In this amends the mapping of
input to output logic is bijective, means for every dis-
tinct input yields a distinct output logic and inputs can be
retrieved by output logic.
(b) Physical reversibility: The physical reversibility
should run backward without the dissipation of power. The
both links of logical reversibility and physical reversibility
will be established, no heat dissipates.
2.2. Conservative Reversible Logic Gate
The concept of conservative reversible logic is to design,
gates that prevent fault propagation. A reversible gate is
known as conservative (parity preserving) gate, if it pre-
serves two elucidates as follow:
(a) Input vector Iv is mapped with output vector Ov such
that bijective mapping between them.
(b) Input and output hamming weight is the same.
Several conservative reversible gates have been pre-
sented up to now, which can be employed for constructing
the reversible logic circuit.8
The restriction of this type of
gates does not construct the CRC circuits with an optimal
value of reversible metrics. The reversible gates used in
the construction of CRC are existing 5 × 5 BVPPG gate
and some our proposed gates. In this work, one conser-
vative reversible BVPPG gate has been employed and we
will examine them. The BVPPG has five inputs and five
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3. Misra et al. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits
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Fig. 1. Existing CR, BVPPG, (a) Schematic presentation, (b) Quantum equivalent realization, its QC = 10.
outputs.9
The input and output are indicated as IV (A, B,
C, D) and Ov (P, Q, R, S). Schematic of BVPPG is
depicted in Figure 1(a), whereas quantum equivalent real-
ization in Figure 1(b).
2.3. QCA
QCA cells consist of four quantum dots positioned at the
corners of the square-shaped cell and two free electrons
bounded within the cell. In QCA design there is no con-
cept of wire; instead of this, QCA cells are joined to form
a grid-like structure which resembles like a wire. QCA
principle promises lower power because four clock control
the information flow.10
All clock zones (Clock 0, Clock 1,
Clock 2 and Clock 3) must be synchronized, the clock
zone has four phases namely: Release, Relax, Switch and
Hold (Fig. 1(a)). The QCA inverter and buffer signal of
input are synthesized by the alternate placement of cells
by tapping off a normal wire, depicted in Figure 1(b). The
basic QCA structures are the inverter and majority voter
gate (Figs. 1(c, e)). The electron can settle with two stable
polarization (P = −1, Binary logic ‘0’ and P = +1, Binary
logic ‘1’), depicted in Figure 1(d).
2.4. Kink Energy
In the situation, when two adjacent cells have opposite
polarization, energy increases, and that increased energy
is known as kink energy (Always greater than ground
energy). More appropriately, minimum energy is termed
for same polarization state and maximum for different
polarization state.11 12
It is estimated by electrostatic inter-
action between the quantum dots in the adjacent cells.
Mathematically, it is the difference between maximum and
minimum electrostatic energy, drawn in Eq. (1).
Ek = Ea b
Pa=Pb − Ea b
Pa=Pb (1)
QCA cell has four dots that depict four sites, the kink
energy of two adjacent cells ‘a’ and ‘b’ can be drawn in
Eq. (2).
Ekink
a b =
qaqb
4 0 r ri −rj
(2)
The denoted symbol as r = relative permittivity, 0 = free
space permittivity, qa and qb are electronic charges of cells
‘an’ and ‘b’ respectively and ra −rb = Distance between
two cells.
To perform correct functionality, the excitation energy
must be greater than KbT. The number of cells with the
same clocking does not show correct functionality. The
restriction of a number of cells to avoid unexpected kink,
following mathematical Eq. (3) is drawn.
N ≤ eE
kink/KbT (3)
The denoted symbol as N = Number of QCA cells,
Kb = Boltzmann constant, Ekink = Kink energy, and
T = Temperature.
2.5. State-of-the-Art-Work
Reversible logic circuit syntheses have attracted consid-
erable attention in recent years due to its low power.13
Many researchers have covered the optimization of the cir-
cuit from the appearance of gate counts, constant inputs,
garbage outputs and quantum cost. Recently, in Ref. [5];
attractive contributions are caused towards syntheses and
optimization of CRC circuit. Most of the researcher in
Refs. [14–21] used the CMOS technology for simulation
and few;22
used the QCA for such simulation. A proper
circuit construction and the optimal value of reversible
metrics are essential to estimate the performance of a
CRC. In Ref. [5]; researchers have constructed the 2-bit
CRC circuit having 6 gate count, 11 garbage outputs and
Clock3Clock2Clock1Clock0
Switch Hold Release Relax
T/4 T/2 3T/4 T
(a)
(b)
(d)
(e)
I1
I2
I3
OUT
P=‘–1’,
Binary ‘0’
P=‘+1’,
Binary‘1’
450
A
A
A
A’
A’
A’
A’
Input A
Out A’
Out A
(c)
900
900
Fig. 2. Basics of QCA, (a) clocking, (b) wire crossing, (c) inverter,
(d) polarization of cell, (e) majority voter.
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Table I. Preliminaries work on reversible comparator.
Comparator circuit Gates utilized Rlogic+PP Logical+Physical reversible Technology adopted Capacity
[5] AG, FTSEG Both Only logical reversible Conventional CMOS 1-bit, 2-bit, n-bit
[14] PG, CNOT, Only reversible Only logical reversible Missing 1-bit, 2-bit, 3-bit, 4-bit,
8-bit, 16-bit, 64-bit
[16] BJSS, HLNS, FG Only reversible Only logical reversible Conventional CMOS 1-bit, 2-bit, n-bit
[18] RC-I, RC-II, PG,TS-3 Only reversible Only logical reversible Conventional CMOS 1-bit, 2-bit, 8-bit,64-bit
and n-bit
[20] CPG, TVG, F2G Both Only logical reversible Verilog HDL 1-bit, 4-bit
[21] ZRQG, Only reversible Only logical reversible Missing 1-bit, 4-bit, n-bit
[22] TR, FG, Only reversible Both QCA 1-bit
31 quantum cost, which is more optimized. We examined
the circuits in Ref. [5]; and compared with our CRC cir-
cuit, as the attempt was to the optimal value of reversible
metrics such as gate count, garbage outputs, and quan-
tum cost. Thus to the best of our state of the art reviews,
researchers have not yet applied the CRC circuit to QCA
technology. In this section, we are highlighting the state
of the art work with their pros and cons.
2.5.1. Fault-Tolerant Reversible Comparator
In 2015, Bose et al. design a parity-preserving based cir-
cuit of 1-bit, 2-bit, and an n-bit reversible comparator.19
The 2-bit comparator circuit utilizes 6 gate count, 11
garbage output, and 31 quantum cost. Conventional CMOS
technology tests the workability of the circuit with missing
technology nodes.
2.5.2. Reversible Comparator
Initially, a novel reversible comparator was designed
by Thapliyal et al. 2010.4
Its design was resembled
to tree based. The circuit constructed 8-bit and 64-bit,
but it is not a modular approach to constructing n-bit
comparator.
2.5.3. Reversible Comparator
In 2014, Babu et al. designed a compact, low power com-
parator that is composed of 6 numbers of gates, 5 garbage
outputs and 21 quantum cost of the 2-bit comparator and
also designed n-bit comparator, but its design was not
conservative.5
This circuit was mainly depicted with con-
ventional CMOS technology by using Micro wind DSCH-
3.5 tool. The simulation results of 2-bit based comparator
circuit brought forward 0.27 ns delay, 70.5 m2
circuit
area, and 202.58 w power respectively.
2.5.4. Reversible Comparator
In 2014 Qi et al. proposed parity preserving the design
of 4-bit comparator, that utilize 15 gate count, 32 garbage
outputs, and 95 quantum cost.10
The 4-bit comparator cir-
cuit results are validated by Verilog HDL-based on the
coding on Altera Quartus II. The validations and verifica-
tion are normal gate-level.
2.5.5. Reversible Comparator Design Using QCA
Das et al. proposed 1-bit comparator in the QCA
framework;29
in 2015. A 1-bit comparator circuit was
designed in the first attempt by using FG and TR gate
and it’s energy efficient with the high number of reversible
primitives (gate count, garbage outputs, quantum cost) as
well as QCA primitives (clock cycle delay, cell area and
clock utilized). However, the designing approach target
only non-conservative reversible.
Due to the influence of all these works, inspire me
to design CR, comparator circuit and to optimize the
reversible metrics as well as QCA primitives. Further,
the verification of circuits in nano-scale based QCA. To
the best of the state of the art reviews, no such design
of conservative reversible comparator in QCA computing.
The preliminary designs of existing works are presented
in Table I.
3. THE PROPOSED CONSERVATIVE
REVERSIBLE GATES
Reliability, power consumption, high performance and
optimization are essential factors in reversible computing.
In recent conservative, reversible is adopted for the dig-
ital logic circuit. It preserves parity on both sides of the
input and output signals, and drawn significant attention in
response to the data integrity and continue operation.23 24
In this work, a three novel conservative reversible gate
(CRG) is proposed with minimum quantum cost, and set-
ting proper input lines to produce required output lines for
CRC circuit.
3.1. The Proposed PPC Gate
A 5×5 CRG named PPC gate is proposed in this work and
is depicted in Figure 3(a). The corresponding truth table
of PPC is drawn in Table II. It can be confirmed from the
truth table that the bijective mapping established, hence
this gate is reversible. Figure 3(b) presents the quantum
equivalent circuit of PPC. The quantum cost of PPC gate
is 9, since it consists of 6 XOR gates, 2 controlled-V, and
1 controlled-V+
gate. The hardware complexity is as arise
8 +2 .
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Fig. 3. Proposed CR, PPC: (a) Schematic diagram, (b) Quantum equivalent realization.
When programmed the third, fourth and fifth inputs
of the PPC gate as high, low and low respectively. The
required outputs of the PPC will occur.
P = A⊕B⊕1 = A⊕B
Table II. The truth table of the PPC gate.
A B C D E P Q R S T
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 1 1 1
0 0 0 1 1 0 0 1 1 0
0 0 1 0 0 1 0 0 0 0
0 0 1 0 1 1 0 0 0 1
0 0 1 1 0 1 0 1 1 1
0 0 1 1 1 1 0 1 1 0
0 1 0 0 0 1 1 1 0 0
0 1 0 0 1 1 1 1 0 1
0 1 0 1 0 1 1 0 1 1
0 1 0 1 1 1 1 0 1 0
0 1 1 0 0 0 1 1 0 0
0 1 1 0 1 0 1 1 0 1
0 1 1 1 0 0 1 0 1 1
0 1 1 1 1 0 1 0 1 0
1 0 0 0 0 1 0 0 1 1
1 0 0 0 1 1 0 0 1 0
1 0 0 1 0 1 0 1 0 0
1 0 0 1 1 1 0 1 0 1
1 0 1 0 0 0 0 0 1 1
1 0 1 0 1 0 0 0 1 0
1 0 1 1 0 0 0 1 0 0
1 0 1 1 1 0 0 1 0 1
1 1 0 0 0 0 1 0 0 1
1 1 0 0 1 0 1 0 0 0
1 1 0 1 0 0 1 1 1 0
1 1 0 1 1 0 1 1 1 1
1 1 1 0 0 1 1 0 0 1
1 1 1 0 1 1 1 0 0 0
1 1 1 1 0 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1
R = A·B⊕B⊕0 = B· A⊕1 = AB
S = A·B⊕A⊕0 = A· B⊕1 = AB
For this intention, we have minimized the gate counts
in the module-1 design of n-bit comparator. In this work,
we utilize one PPC to construct the module-1 of the n-
bit comparator as well as the 1-bit comparator (presented
in Section 4.2). The schematic presentation and quantum
equivalent realization of 1-bit comparator are depicted in
Figures 4(a and b).
3.2. The Proposed PPNG-1 Gate
A 4 × 4 PPNG-1 is presented in Figure 5(a) and its truth
table are drawn in Table III. It can be confirmed from
the truth table that the PPNG-1 is reversible because of
bijective mapping between input and output signals. The
quantum equivalent presentation in Figure 5(b), and dotted
rectangle box is equal to a 2×2 CNOT gate, the quantum
cost of PPNG-2 is 7 and its hardware complexity is as
arise 6 +4 +3 .
When programmed the third and fourth inputs of the
PPNG-1 gate as high and low respectively. The required
outputs of the PPNG-1 will occur.
Q = A⊕B
S = A· B⊕0 ⊕A· 1 ⊕0 = A·B⊕A·0 = AB
For this intention, we have minimized the garbage outputs
in the module-2 design of n-bit comparator (presented in
Section 4.2).
3.3. The Proposed PPNG-2 Gate
A 3 × 3 CRG named, PPNG-2 is proposed in this work
and depicted in Figure 6(a). The reversibility truth table is
drawn in the Table IV. The QC of the PPNG-2 is equal
to 3, and its hardware complexity is as arise 4 . There are
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Fig. 4. Two-input comparator with PPC gate: (a) Schematic diagram, (b) Quantum equivalent realization.
Fig. 5. The proposed PPNG-1 gate: (a) Schematic presentation, (b) Quantum equivalent realization.
very few CRG has such low value of quantum cost with
its unique feature.
When programmed the first and third inputs of the
PPNG-2 gate as low and high respectively. The required
outputs of the PPNG-2 will occur.
P = 0 ⊕B = B
R = B ⊕1 ⊕D = B ⊕D
Table III. The truth table of the PPNG-1 gate.
A B C D P Q R S
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 1 0 0
0 0 1 1 0 1 0 1
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 0 1 0
1 0 0 0 1 1 0 1
1 0 0 1 1 1 0 0
1 0 1 0 1 0 1 0
1 0 1 1 1 0 1 1
1 1 0 0 1 0 0 1
1 1 0 1 1 0 0 0
1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 1
For this intention, we have minimized the garbage outputs
and required the output of the comparator in module 3
design of n-bit comparator. In this work, we utilize one
proposed PPNG-2 to construct the module-3 of the n-bit
comparator (presented in Section 4.2).
Lemma 1. Novel PPC gate is a conservative gate.
Proof A PPC gate is 5 × 5 type reversible gate. Let the
input vector is Iv(A, B, C, D) and the output vector is OV =
P = A⊕B⊕C , Q = B, R = AB⊕B⊕D , S = AB⊕
A ⊕ D , T = A ⊕ D ⊕ E . We know that parity of input
and parity of output was conserved in any conservative
gate.
The parity of input is A ⊕ B ⊕ C ⊕ D ⊕ E and parity
of output is
A⊕B⊕C ⊕B⊕ AB⊕B⊕D ⊕ AB⊕A⊕D
⊕ A⊕D⊕E
= A⊕B⊕C ⊕B⊕ AB⊕D ⊕ AB⊕D
⊕ A⊕D⊕E
= B⊕C ⊕ AB⊕A⊕D ⊕ AB⊕B⊕D
⊕ A⊕D⊕E
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Fig. 6. The proposed PPNG-2 gate: (a) Schematic presentation, (b) Quantum equivalent realization.
Table IV. The truth table of the PPNG-2.
A B C D P Q R S
0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 1
0 0 1 0 0 0 1 0
0 0 1 1 0 1 0 1
0 1 0 0 1 1 1 0
0 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 0
1 0 0 1 1 1 1 1
1 0 1 0 1 0 1 0
1 0 1 1 1 1 0 1
1 1 0 0 0 1 1 0
1 1 0 1 0 0 0 1
1 1 1 0 0 1 0 0
1 1 1 1 0 0 1 1
= B ⊕C ⊕ A+B ⊕D⊕ A+B ⊕D⊕A⊕D⊕E
= B⊕C⊕A⊕D⊕E = A⊕B⊕C⊕D⊕E
Since we know AB ⊕ A = A + B, AB ⊕ B = A + B,
A⊕A = 0
Thus, the parity of the output is matched to the
parity of input. Hence, PPC gate is a conservative
gate.
4. THE PROPOSED DESIGNING APPROACH
FOR CR, n-BIT COMPARATOR
The proposed conservative reversible n-bit comparator,
based on three modules, named as module-1, module-2
and module-3. There are various circuits of the reversible
comparator in the state of art among which the latest cir-
cuits in Ref. [5]; are examined to be the optimal reversible
metrics. We influence on this circuit;5
and compared it
with our circuit, our achievement was to optimize all the
reversible metrics such as gate count, garbage outputs, and
quantum cost. In the next section, we cover this concept to
the schematic diagram, algorithms, detail description, and
lemmas.
4.1. Module-1 Design of Conservative Reversible
n-Bit Comparator
This section, we have explored the proposed gate to syn-
thesize a module-1. A 5 × 5 PPC gate has been uti-
lized to synthesize a module-1. The working princi-
ples of the proposed PPC are utilized MSB bit of two
n-bit numbers with Figure 7(a). The required output for
comparator design as, a first output for equal to, the
third output for less than and fourth outputs for greater
THAN.
4.2. Module-2 Design of Conservative
Reversible n-Bit Comparator
In this section, the construction of the module-2 using the
PPNG-1 and BVPPG gates. The motive of selection of
gates is optimizing the reversible metrics. Based on this
combination gates, a PPC-I around the module-2 is fin-
ished. Figure 7(b) depicts the circuit of PCC-1 (named as
P = parity, C = comparator, and C = cell). In considera-
tion with the rules of reversible logic syntheses that fan-in,
feedback and fan-out are not permitted, kept in mind to the
circuit construction. The working principles of the second
module are utilized (n–1) the bit of two numbers, as well
as previous module inputs Rn = Equal to and Pn = Greater
than. In fact, module-2 generate the equal and a greater
logic bit.
The QC of PPNG-1 gate is 7 and BVPPG gates is 10;
therefore, the QC of PCC-1 is equal to:
QC PCC−1 = QC 1 ×PPNG-1 +QC 1 ×BVPPG
= 7 +10 = 17
4.3. Module-3 Design of Conservative Reversible
n-Bit Comparator
For minimizing the quantum cost and unit delay in order
to cost effective design, we use the one PPNG-2 as a pro-
grammable way of inputs (A = 0, C = 1) as a module-3.
The working principle of the third module is to utilize two
outputs of previous module-2 (Pn and Rn , the process of
acquiring output from the previous module can take place
in a repeated way if the least significant bit (LSB) is not
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Fig. 7. (a) The proposed architecture of module-1. (b) The proposed architecture of module-2. (c) The proposed architecture of
module-3.
Table V. The truth table of 2-bit comparator.
Input Output
A2B2 A1B1 P (Greater than) Q (Less than) R (Equal to)
A2 > B2 x 1 0 0
A2 < B2 x 0 1 0
A2 = B2 A1 = B1 0 0 1
A2 = B2 A1 < B1 0 1 0
A2 = B2 A1 > B1 1 0 0
obtained. The less than logic obtain, if greater and equal
enter into the third module (utilize PPNG-2). It first checks
the greater than, equal to and if not any of these, it’s final
step is to synthesize the less than logic by this expres-
sion, {(Greater than) ⊕ (Equal to)}.’ In fact, module-3
Fig. 8. Proposed CR, 2-bit comparator (a) The presented architecture (b) Quantum equivalent realization.
generates the all logic bits of the comparator, as shown in
Figure 7(c).
4.4. Modules Based 2-Bit Conservative
Reversible Comparator
The 2-bit comparator computing the three required outputs
such as P (Greater than), Q (Less than) and R (Equal to),
from truth Table V, some logical calculation expressions
can be obtained as followed.
FG = A2 > B2 ⊕ A2 = B2 A1 > B1
FL = A2 < B2 ⊕ A2 = B2 A1 < B1
FE = A2 = B2 A1 = B1
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Fig. 9. The proposed architecture of CR, n-bit comparator.
According to the logical calculation expressions, a cir-
cuit employing three modules is depicted in Figure 8(a).
The circuit of 2-bit comparator has groups of inputs
(A1, B1 and (A2, B2 these inputs are applied to PPC
and PCC-1. The outputs (P2, R2 of PPC gate, are
associated with PCC-1. Similarly, the outputs (P1, R1
of PCC-1, are associated with PPNG-2 gate. The
required comparator logic is obtained from the PPNG-
2 gate, marked as P (Greater than), Q (Less than)
and R (Equal to). The quantum presentation of the
2-bit comparator is depicted in Figure 8(b). The
steps to design a 2-bit comparator are presented in
Algorithm 1.
Algorithm 1 (2-Bit Comparator Design).
(a) Take a 1 PPC gate will take inputs A2 B2 1 0 0
and synthesize outputs P1 = A2
¯B2 Q1 = AB R1 =
A1 ⊕B1 A2 B2
(b) Take a 1 PPC-1 cell will take inputs A1 B1 P1 R1
and synthesize outputs P0 = P1 ⊕ R1 A2B2 R0 =
R1 A2 ⊕B2
(c) For final selection of comparator output take one
PPNG-2 gate will accept inputs in the sequence
0 P0 1 R0 and synthesize outputs P = P0 Q =
P0 ⊕R0 R = R0 P0 ⊕R0
(d) Select appropriate comparator outputs, P (Greater
than) Q (Less than) and R (Equal to) and consider remain-
ing as garbage outputs.
4.5. Modules Based n-Bit Conservative
Reversible Comparator
The n-bit comparator required, one time module-1 (used
one PPC), (n − 1) time module-2 (used one BVPPG and
PPNG-2) and one module-3 (used one PPNG-2), depicted
in Figure 9. The n-bit comparator is designed by 1 PPC
gate which acquires two binary numbers An and Bn. It
produces three outputs Rn, Pn and Qn. These outputs are
associated with PCC-1, where previous of (n−1 the bits
of A and B are also feed. Now generated outputs are Pn−1
and Qn−1 associated with PPNG-2 gate. That presented
outputs of the PPNG-2 gate is the comparator outputs.
Algorithm 2 shows a formal presentation of the n-bit com-
parator design.
Algorithm 2 (Comparator-Design-Algorithm
(n-Bit)).
1. Input, Output: Input (A0, A1,……An) and B=(B0,B1,…Bn),
Output O=(P, Q, R) for comparator operation.
Begin
2. Level-1: Circuit takes on one PPC gate
a. Take two MSB of (n-1)th bit data from n-bit data
I(A,B) and synthesize three output
O(Pn-1, Qn-1, Rn-1)
3. Begin procedure
4. Step-1. If I1>I2 then
5. O4=Pn-1
6. if I1<I2 then
7. O3=Qn-1
8. Else O3=Rn-1
9. End if
End if
10. End procedure
11. Level-2: Circuit takes (n-1) PCC-1 cell
a. Take (n-2)
th
data from n-bit data bit I(A,B) and two
also take level-1 particular output I(Pn-1, Rn-1) and
synthesize two output (Pn-2, Rn-2)
12. Begin procedure
For i=n to 0
If i=n then
13. )2nB2nA(1nR1nP2nP1O −−−⊕−=−= ,
14. )2nB2nA(1nR2O −⊕−−=
15. End if
End loop
16. End procedure
17. Level-3: Circuit takes one PPNG-2 gate
a. Take LSB data bit from previously result output O
(P0,R0) and synthesize three output O(P,Q,R), where
R (Equal to), P (Greater than) and Q(Less than) for
appropriate Comparator logic operation.
18. Begin procedure
19. If i=0 then
20. O1=P, // Greater than
21. 0R0PQ3O ⊕== , // Less than
22. O4=R, // Equal to
23. End if
24. End procedure
25. End
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5. REVERSIBLE METRICS CALCULATION
OF THE PROPOSED CRC
In this section, we have present the comprehensive calcu-
lation of all the proposed CRC in terms of popular met-
rics. In the circuit construction of 2-bit and n-bit CRC, the
main concern is to keep reversible metrics as minimum
as possible. Several minimum reversible metrics for CRC
in regards quantum cost, garbage outputs, constant inputs,
and hardware complexity are presented by Lemmas 2, 3
and 4.
Lemma 2. A CRC circuit for 2-bit binary number com-
parator can be syntheses of at least 29 quantum cost,
9 garbage outputs, 8 constant input and (19 +8 +4
hardware complexity.
Proof. A 2-bit comparator has used three modules
(module-1, module-2 and module-3) in Figure 8. The QC
of module-1, module-2 and module-3 are 9, 17 and 3
respectively. Thus, the QC of 2-bit CRC is 29, because
QC 2-bit comparator
= 1QC module-1 +1QC module-2
+1QC module-3 = 9 +17 +3 = 29
The input to output mapping is bijective and conserve
the parity bit in the 2-bit comparator circuit. In this,
at least, 9 garbage outputs are required, which needed
8 constant inputs. The circuit structure of 2-bit compara-
tor utilizes module-1 that generates 3 garbage output,
module-2 that generates 5 garbage output and module-3
that generate 1 garbage output, depicted in Figure 7(b).
Thus, the GO is 9, because
GO 2-bit comparator
= 1GO module-1 +1GO module-2
+1GO module-3 = 3 +5 +1 = 9
The circuit of 2-bit comparator consists of modules
(module-1, module-2 and module-3), that required con-
stant input (CI) is 3, 3 and 2 respectively. Thus, the CI
is 8, because
CI 2-bit comparator
= 1CI module-1 +1CI module-2
+1CI module-3 = 3 +3 +2 = 8
Table VI. Reversible metrics comparison of n-bit CRC.
Size GC in %IR
order bit GC in [5] proposed w.r. to GC QC in [5] QC in proposed %IR w.r. to QC GO in [5] GO in proposed %IR w.r. to GO
2 6 4 33 33 31 29 6 45 11 8 27 27
4 12 8 69 63 8 69 25 18 28
8 24 16 145 131 9 65 53 38 28 30
16 48 32 297 267 10 10 109 77 29 35
32 96 64 601 539 10 31 221 158 28 50
64 192 128 1209 1083 10 42 445 318 28 53
128 384 256 2425 2171 10 47 893 638 28 53
256 768 512 4857 4347 10 50 1789 1278 28 85
Table VII. Comparison results of different n-bit comparator.
Design [5] [14] [16] [17] Proposed
n-bit
#GC (4n−2) (7n−4) (3n) (4n−2) 2n
# QC (19n−7) (16n−10) (13n−5) (14n) (17n−5)
# GO (7n−3) (5n−4) (4n−3) (5n−4) (5n−2)
In a 2-bit comparator, we use 1 module-1, 1 module-2,
and 1 module-3. The module-2 is acknowledged as a
combination of two gates (1 PPNG-1 + 1BVPPG) in
Figure 7(a). Thus, we can specify that the hardware com-
plexity (HC) as:
HCmodule−1 = 8 +2
HCmodule−2 = HCPPNG−1 +HCBVPPF
= 5 +6 +4 + 2 = 7 +6 +4
HCmodule−3 = 4
Thus, then requires hardware complexity for 2-bit CRC is
HC = HCPPC +HCPCC−1 +HCPPNG−2
= 8 +2 + 7 +6 +4 + 4
= 19 +8 +4
Lemma 3. The n-bit binary number of CRC circuit can be
syntheses by at least
GOn−bit ≥ 5n−2
GCn−bit ≥ 2n
QCn−bit ≥ 17n−5
Where GO, GC, QC be the necessary numbers of garbage
outputs, gate count, and quantum cost. Then
Proof. In 2-bit comparator, there are three outputs
(P, Q, R). Thus, it has at least 8 garbage output. Because
PPC at least 2 GO, PPC-1 cell at least 5 GO and PPNG-
2 at least 1 GO. The least number of GO in 2-bit
comparator is
GO2−bit = 8 = 5 ×2 −2
Hence, the result persists for 2- bit comparator.
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Fig. 10. (a) Comparison results of existing and proposed based on gate count, (b) Comparison results of existing and proposed based on Quantum
cost, (c) Comparison results of existing and proposed based on garbage output.
Suppose that, the result persists for the n-bit compara-
tor. Hence, a necessary number of garbage outputs is
GOn−bit = 5n−2 .
The 2-bit comparator logic synthesis by utilizing the
designs such as module-1, module-2, and module-3. The
total gate count is 1 + 2 + 1 = 4 = 2 × 2. Thus, the result
persists for 2-bit. Suppose that, the result persists for
the n-bit.
As a result, the least gate count for a n-bit comparator
is 2n.
According to the circuit of the 2-bit comparator. The
circuit consists of 3 modules (module-1, module-2 and
module-3), that requires 9, 17 and 3 quantum cost respec-
tively. So the least quantum cost of 2-bit comparator is
QC2−bit = 29 = 17 ×2 −5 .
Hence, the result persists for the 2-bit comparator.
Assume that, the result persists for the n-bit com-
pactor. The least quantum cost for n-bit comparator is
QCn−bit = 17n−5 .
Lemma 4. A n-bit comparator can be synthesized with
5 +7n + 6n−4 +4 n−1 , hardware complexity.
Proof. Theorem 3 is the evidence for 2-bit comparator
with (19 + 8 + 4 hardware complexity. In this state,
we have synthesized hardware complexity of n-bit com-
parator. Combining 1 module-1, (n − 1) module-2 and
1 module-3 for the n-bit comparator. Hence, the hardware
complexity for a n-bit comparator is
1× 8 +2 + n−1 7 +6 +4 +4
= 8 +7 n−7 +4 + 2 +6 n−6
+ 4 n−4 = 5+7n + 6n−4 +4 n−1
Therefore, a reversible n-bit comparator can be synthe-
sized with 5 + 7n + 6n − 4 + 4 n − 1 , hardware
complexity.
5.1. Comparison Between Various Circuits of
Reversible Comparator
Circuits for reversible comparator were presented in
Refs. [14–21]. It is demanding to perform better regard-
ing reversible metrics and size order extend for n-bit.
The proposed n-bit CRC is compared to counterparts.5
Note that the proposed CRC circuit has an optimal value
of reversible metrics than the existing CRC. It is verified in
Table VI the quantity, size increase, the improvement ratio
(IR) also increases. Hence, it can analyze that reversible
comparator is giving optimal reversible metrics as com-
pared to the best existing CRC.5
Table VII shows that
the existing CRC circuit requires (4n−2) gate count and
(19n−7) quantum cost. This work presented CRC circuit
require less reversible metrics such as (2n) gate counts
and (17n − 5) quantum cost. So our claim for the opti-
mal value of reversible metrics has been correct. In the
same way, garbage outputs of proposed CRC circuit that
our better reversible metrics. Figures 10(a–c) present the
comparison of the proposed CRC with the existing non-
conservative reversible comparator (NCRC) circuits. Gen-
erally, a conservative circuit is not cost effective than the
non-conservative circuits. Note that the proposed CRC per-
form better than the NCRC circuit, which is shown in
Figures 10(a–c). In the case of proposed 2-bit comparator
circuit synthesize by 4 gate count, 29 quantum cost and
8 garbage outputs, whereas the best-known conservative,
reversible comparator;5
requires 6 gate count, 31 quantum
cost, and 10 garbage outputs.
6. DESIGN OF REVERSIBLE PPC IN QCA
In this section, we present QCA layouts and simulation
results of PPC gate. It is suitable to give layout rules
as required for designing layouts in QCA in the next
part.
6.1. QCA Computing Design Rules Adopted in the
PPC Layout Design
(i) Taking coplanar (rotated) cells to reduce the clock
cycle delay.25
(ii) Using four clock zones to synthesizing the
results.
(iii) Using a proper sequence of the clock (clock0, clock1,
clock2, clock3 ).
(iv) Avoiding long wire and crossovers. Its advantage is
that it decreases the layout area and delay.26
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Fig. 11. PPC gate: (a) Logic diagram by Maj3, (b) Cell layout.
(v) The maximum 15 cells in layout design to operate
with one clock zone. It minimizes the thermodynamic phe-
nomenon.
(vi) For duplication of logic signal take the fan-out con-
cept but with different clock zone. It reduces the layout
area.
(vii) For computation, fixed polarization, normal cell and
rotated cell utilized.
6.2. QCA Layout of Reversible PPC and
Simulation Results
In an attempt to quantum information processing by using
reversible logic, we select QCA, more powerful than its
CMOS technology.25
The theorems of QCA are confi-
dent that they can provide high computing speed and high
device density. Researchers in demonstrated the robust
design (coplanar crossing) and it were focused that rotated
cells are more stable as compared to normal cells. That’s
why the rotating cell is utilized for cell layout design.
Proposed designs are simulated with QCA Designer, using
the simulation engine (Bistable approximation), with a
default parameter. We present the block diagram and cell
layout of PPC (In Fig. 11). The QCA simulation results of
PPC are presented in Figure 12(a). Here we show the QCA
primitives results for quantum information, 14 Majority
voter, 7 Inverter, 0.432 m2
(cell area) and 387 (cell
count).
The appropriate QCA majority gate expression can be
written for P node is:
P = M M A, B, C M A, B C C
= M AB+BC+AC AB+BC+AC C
= C AB+BC+AC + AB+BC+AC AB+BC+AC
+C AB+BC+AC
= C AB BC AC + AB BC
× AC AB+BC+AC +ABC
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(a)
(b)
Fig. 12. (a) Simulation result of PPC gate, (b) Simulation diagram of
the proposed 1-bit comparator.
= C AB+BC+AC + AB+BC+AC
× AB+BC+AC +ABC
= ABC+ABC+ABC+ABC= 1 2 4 7 =A⊕B⊕C
The majority logic format of the node R according to lay-
out of PPC can be written as:
R = M M M A B 0 D 0 M M A B 0 D 0 1
= M M AB D 0 M AB D 0 1
= M D A+B ABD 1
= D A+B ABD+ABD+ A+B D
= ABD+AD+BD = ABD+ A+B D
= AB D+ AB D = 1 2 5 7 = AB⊕D
As the equation of node S = AB ⊕ A ⊕ D = AB ⊕ D
requires EX-OR, AND, NOT gates for the realization of
the layout. These EX-OR, AND, NOT gates are synthe-
sized by majority gate. The synthesize majority equation
is drawn as:
Q = M M M A B 0 D 0 M M A B 0 D 0 1
= M M AB D 0 M AB D 0 1
= M D A+B ABD 1
= D A+B ABD+ABD+ A+B D
= ABD+AD+BD = ABD+ A+B D
= AB D+ AB D = 1 3 4 7 = AB⊕D
The input-output connection can be represented as a node
T = A ⊕ D ⊕ E. The majority logic arrangement accord-
ing to PPC cell layout can be represented by appropriate
synthesise majority expression as:
T = M M A, D, E M A, D, E E
= M AD+DE+AE AD+DE+AE E
= E AD+DE+AE + AD+DE+AE
× AD+DE+AE +E AD+DE+AE
= E AD DE AE + AD DE AE
× AD+DE+AE +ADE
= E AD+DE+AE + AD+DE+AE
× AD+DE+AE +ADE
= ADE+ADE+ADE+ADE
= 1 2 4 7 = A⊕D⊕E
Lemma 5. A 1-bit comparator utilizes 24.205% of area
usages.
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Proof. One PPC gate forms a 1-bit comparator
(In Fig. 7(a)). For total area calculation, QCA Designer
tool automatic gives the total area of PPC layout, which is
518,008 nm2
. However, in the case of the cell area, manual
manipulation is done. These manipulations are:
Cell area = Total number of cells used in the layout
× One individual cell area
= Total number of cells used in the layout
× One cell width×One cell height
= 387 × 18×18 =387×324=125 388 nm2
For area usages, the calculation is done by dividing the
cell area to total area by following way.
Area usage for proposed gate
= Cell area / Total area
= 125 388 / 518 008 = 24 205%
Therefore, 1-bit comparator utilizes 24.205% of area
usages.
Lemma 6. The 1-bit comparator requires the same layout
of PPC with 1 latency.
Proof. PPC can implement the 1-bit comparator results
as shown in Figure 7(a). In the layout (Fig. 11(a)) inputs
are set as C = 1 and D = E = 0 the output P, R and S
synthesize the comparator logic (In Fig. 12(b)). In the cell
layout design of the PPC the following clock is utilized
in the specific order (Clock 0, Clock 1, Clock 2, Clock 3,
Clock 0, ). The simulation result ensures that if A = B
means outputs, P = 1, and Q = R = 0, after 1 clock cycle
delay i.e., Equal logic synthesizer. When the comparator
input A = 0 and B = 1, then the output as P = Q = 0 and
R = 1, after 1 clock cycle delay i.e., Less logic synthesizer.
When A = 1 and B = 0, then the output as S = 1 and
P = R = 0, after 1 clock cycle delay i.e., Greater logic
synthesizer. Hence, the 1-bit comparator requires the same
layout of PPC with 1 latency.
In Table VIII specify the detail of reversible as well as
QCA primitives for the adopted coplanar crossover (used
rotated as well as a normal cell) in the proposed compara-
tor design and compared to recent preliminary design.22
According to parameter obtained, our circuits are more
suitable for conservative reversible-QCA approach.
Table VIII. Comparisons of 1-bit reversible comparator.
QCA primitives
Reversible metrics
Area
Design MV Latency ( m2
GC QC CI GO Conservative
[22] 1-bit 17 7 0.343 3 9 3 2 NO
Proposed 1-bit 14 3 0.432 1 9 3 2 YES
%IR 17.64 57.14 NI 66.66 NI NI NI
7. THE ENERGY DISSIPATION ANALYSIS OF
PROPOSED PPC GATE
To analyze the robustness and performance of the proposed
PPC gate at different kink energy (0.5 mev, 1 mev and
1.5 mev).27
The exhaustive technique is used for energy
estimation during an input switching vector in PPC gate.
The results are depicted in Table IX. This result shows that
the maximum energy dissipation, minimum energy dissi-
pation, average energy dissipation, average leakage and
average switching energy dissipation are 1.433, 0.2245,
0.78531, 0.22764, 0.55767 respectively at Ek = 0 5 mev,
likewise are 1.6172, 0.61914, 1.07908, 0.62527, 0.45381
respectively at Ek = 1 mev and 1.87115, 1.0498, 1.42932,
1.05777, 0.37154 respectively at Ek = 1 5 mev. By this
result, the average energy dissipation of the PPC gate
increases with the kink energy in a constant manner. For
this analyzing energy is conducted using QCAPro tool.
Energy dissipation versus kink energy plots for average
leakage, average switching and average energy dissipation
of PPC are drawn in Table VIII of the second row. For
instance, at a kink energy (0.5 mev, 1 mev and 1.5 mev),
maximum and minimum energy dissipation are drawn in
Table VIII of the third row. The estimation of power in
each cell at 0.5Ek is depicted in Table IX of the first
row. The worst power dissipated cells, encircled with black
must be made physically reversible, so to make it zero
power dissipation. All other remaining cells, which are
indicated with a light color, used in designing wire, the
majority and inverter are better regarding power dissipa-
tion. In the energy estimation, we have used the cell size
of 18 nm.
8. AVERAGE POLARIZATION ESTIMATION
VERSUS TEMPERATURE
The usual working of reversible 1-bit comparator is men-
tioned in the previous section. Temperature dependency
analysis of proposed PPC gate is also presented. How-
ever, temperature dependency analysis is done with a
coherent vector engine with default parameters. To test
the temperature dependencies of the QCA design of the
PPC are simulated in a different range of temperature
(1 to 10 0
K) and measure polarization at the differ-
ent output node (P, Q, R, S, T). For output node R
the Avg. Output node polarization at 1 0
K is calculated
as: (9.50e–001)–(−9.56e–001)/2 = 3.812. The obtained
polarization value ensure that the design has an accu-
rate functioning in a different range of temperature (1
to 10 K). Figure 13 depicts the average output node
polarization versus temperature for the proposed design
of the PPC gate. Therefore, the average polarization esti-
mation is efficient in the range of temperature (1 to
10 K). The maximum reaches temperature is a challenge
in QCA.27
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Table IX. Energy dissipation analysis.
Design PPC
QCA cell count 348
Thermal layout Ek At 0.5, Where Ek is the
maximum kink energy
Average energy dissipation for various
value (0.5, 1 and 1.5) of kink energy Ek
Max and min energy dissipation for various
value (0.5, 1 and 1.5) of kink energy Ek
9. DISCUSSION
We achieve the physical reversibility and estimation of
energy dissipation aspects of the QCA cell layout by using
QCAPro tool. The two main concerns of this analysis are:
Physical reversibility may be anticipated by the cover of
prerequisites that
(a) In thermal layout map good and worst condition iden-
tified by color map, few of the cells and gates are dissi-
pate large power, this is made by the QCAPro tool. The
major step in minimizing the energy dissipation of dark
hotspot to designers to achieve the fully physical reversible
system.
(b) By synchronizing all the four clock zones, the higher
the stability (Polarization value) in QCA design can be
achieved.
Therefore, our emphasis on the analysis of QCA cell lay-
out in QCAPro tool with a different value of kink energy.
However, analysis of energy dissipation applied to PPC.
Therefore, we analyzed the energy dissipation, to indicate
the low power feature in this work.
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Fig. 13. Temperature analysis of average output node polarization of
proposed PPC gate.
10. CONCLUSIONS
An effort has been made in optimizing the conservative
comparator circuit around QCA. The proposed comparator
circuit is successfully designed with three new conserva-
tive, reversible gates. These new reversible gates (PPC,
PPNG-1, and PPNG-2 gate) have low values of quan-
tum cost and novel comparator circuit is analyzed with
the existing circuits regarding gate count, garbage output,
and quantum cost, all the parameters is optimized. Also,
reversible 1-bit comparator simulation is performed suc-
cessfully by QCA Designer tool. The QCA design of 1-bit
comparator has been tested successfully and requires only
387 number of cells, 0.432 m2
area, and 24.205% area
usages. Also, we also tested average polarization versus
temperature of all the different nodes of the PPC in QCA
using coherence engine. This analysis shows that output
S node cell slumped after 7 K0
to 8 K0
then become
constant. The optimized reversible parameters and QCA
primitive results demonstrate and confirmed that our cir-
cuits dominate over the state of the art circuits. This com-
parator circuit will be useful for implementing the digital
devices, encryption devices, microprocessor and microcon-
troller systems and digital communication.
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