Low Power LC-Quadrature VCO with Superior Phase Noise Performance in 0.13 μmRF-CMOS Process for Modern WLAN Application

Circuits, Systems, and Signal Processing
https://doi.org/10.1007/s00034-021-01921-4
Low Power LC-Quadrature VCO with Superior Phase Noise
Performance in 0.13 µm RF-CMOS Process for Modern
WLAN Application
Imran Ullah Khan1 · Deepak Balodi2 · Neeraj Kumar Misra3
Received: 12 November 2020 / Revised: 21 November 2021 / Accepted: 24 November 2021
© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021
Abstract
The presented work intends to encounter the challenge of optimizing frequency track-
ing in the C-band WLAN spectrum, with a tuning range and phase noise (PN)
performance. A Quadrature Voltage Controlled Oscillator (QVCO) design in 130 nm
CMOS technology has been presented to cover the most sought WLAN/WiFi spec-
trum of modern wireless systems, employing the current reuse technique and an
on-chip inductor implementation. To provide better compensation of LC losses at
reduced power dissipation, a cross-coupled structure combining NMOS and PMOS
has been used. We have run an extensive simulation using the industry-standard ADS
(Keysight technology) platform. The simulation study attributed to the superior phase
noise performance of − 160 dBc/Hz at 1 MHz (near f max) at a power dissipation
of 6.52 mW from 1.2 V supply. With the moderate voltage tuning range, the entire
desired frequency span of 5.400–5.495 GHz was obtained with a fairly high resolu-
tion of 2.375 MHz/1 mV, which allows serving a larger crowd for this spectrum. A
fairly moderate VCO gain along with the obtained phase noise and power dissipation
provides a well-established Figure of Merit (FOM) of − 187 dB. Finally, a compar-
ison study in terms of power dissipation, phase noise, tuning range, voltage tuning,
and Kvco is performed to demonstrate that the provided work is considerably more
significant than traditional efforts.
B Neeraj Kumar Misra
neeraj.mishra3@gmail.com
Imran Ullah Khan
iukhan@iul.ac.in
Deepak Balodi
deepakbalodi@gmail.com
1 Department of Electronics and Communication Engineering, Integral University, Lucknow, India
2 Department of Electronics and Communication Engineering, Babu Banarasi Das Engineering
College, Lucknow, India
3 Department of Electronics and Communication Engineering, Bharat Institute of Engineering and
Technology, Hyderabad 501510, India

Keywords VCO · PLL · Phase noise · Wi-Fi · RF-CMOS
1 Introduction
Due to their importance in a broad range of contemporary wireless applications,
high-frequency Voltage Controlled Oscillators (VCO) and Phase-Locked Loop (PLL)
frequency synthesizers have received a lot of attention in recent years [10]. Certain
stringent requirements like phase noise specifications and power dissipations imposed
by these wireless applications have demanded lots of research and analysis work in
this field, especially the backbone of PLL, that is a VCO. Therefore, designing low
power tuned oscillators that too with optimal phase noise performance has been one of
the most challenging aspects of PLL design. Out of the various topologies and archi-
tectures of VCO in the present technologies, LC-VCO proved to be the best choice
due to the narrowband requirements of the wireless applications.
Although several VCO designs with low phase noise and broad tuning range have
been described, designing a VCO with an optimal performance of high sensitivity, low
phase noise, and low power consumption remains a difficult task. In [10], the bimodal
oscillations have been studied and prevented from occurring in an attempt to obtain
the sharp tuning characteristic. This was essential to obtain for the proposed QVCO
with a sufficient stability margin in gain management. The study highlighted the use
of quadrature clocks, which are widely utilized in RF front-ends of wireless systems
to speed up the conversion process. An earlier attempt [20], envisages this fact where a
cellular transceiver employed the on-chip inductor topology for the tuned oscillator in
support of the mixer. The quadrature VCO was designed to meet the cellular specifica-
tions, where the poly-phase network controls its phase noise performance. In contrast
to the initial efforts, recent work was reported with the efforts in the ultra-wideband
operation of quadrature VCO for S and C band applications [13]. This also made use
of the tuned oscillator’s best quality and phase noise performance through on-chip
stacked inductor implementation. Ultra-wideband tuning was obtained using a dis-
crete 8-bit capacitor bank array in addition to the NMOS varactor pair for fine-tuning.
The whole combination showed satisfactory tuning between 2.4 to 6 GHz with 12 mW
dissipation from a 1.2 V supply. In [25], a novelty in wider tuning with low phase noise
was claimed for LC-VCO implemented using a modified Class-C structure. The addi-
tional effort in achieving the best phase noise performance was kept using the damping
resistors at the source end, whereas the LC filter was also placed in the current source.
One more article was reported for the similar effort of widening the tuning range [13]
where the running condition of the VCO was tuned from class AB to C operation. The
work used the Colpitts structure for transistor-based LC oscillations in 41.14 GHz to
48.11 GHz. An improved varactor circuit to support a 25 GHz oscillator was employed
in [21], where the VCO design was aimed to achieve a wide tuning operation. Parallel
varactors were biased in a distributed sense with a series inductor connected at both
ends of the varactor bank. This topology of the proposed LC-VCO has extended the
tuning range of the oscillator, but unfortunately, has certain limitations in the phase
noise aspects. Figure 1 depicts the LC-VCO in a phase locked loop.

Fig. 1 Demonstration of an LC
VCO employed in a
phase-locked loop
A sub-pico-Farad magnitude capacitance to the output terminal was also connected
to lower the phase noise and to ensure the quick starting of VCO, a startup circuit was
also implemented in that work. In another effort [25], the lowered frequency-tuning
range (FTR) of the VCO could be easily covered up by the use of a single LC-VCO. A
high Q factor and active low phase noise were achieved, due to the reduced FTR. The
50% duty cycle in addition to quadrature operation was also achieved using the fully
differential divide by 6 dividers. The optimum settlement between the tuning range and
phase noises (PN) performance have to be sought additionally. A comparative analysis
has been performed and harmonic-mode VCOs (H-VCOs) has been compared with
fundamental-mode VCO (F-VCOs) in another work [19]. The objective to improve
mixing efficiency was achieved using the class-C push–pull topology in the VCO core
which enhanced the second-harmonic content to solve the purpose. The most effective
way of achieving the quadrature signal generation with the current reuse technique has
been demonstrated in other published work [22]. A well-recognized and optimized
scheme for quadrature signal generation without much additional power dissipation
is to go for the back-gate topology for the switching transistors of the differential
structure. A circuit mismatch also sometimes introduced purposely to manage the
startup behaviour of the oscillator. A similar effort was placed in the reported work
[2], where the intention was to reduce the start-up time of the oscillations and was
attempted by turning-on on the tail current. An extremely low power LC-VCO with
superior phase noise performance was reported recently [2, 4], which targeted the
narrowband Bluetooth application in the most sought S-band spectrum of the modern
wireless systems. In this work, the CMOS cross-coupled pair along with an on-chip
inductor facilitated the low power and low phase noise attributes. This study develops
a robust model for LC-VCO with improved primitives such as low power, superior
noise performance. The power dissipation of 8.56 mW with a high gain sensitivity of
194 MHz/Volt was reported using 1.2 V supply in the 130 nm RF-CMOS process.
In this proposed work, an LC-VCO with tuned MOS varactors and an on-chip induc-
tor implemented in UMC’s 130 nm RF-CMOS process is presented. In the literature,
several works [17, 2, 5, 14, 7, 21, 23–25] of LC-VCO were directly proposed through
algorithm derivation and architectural exploration. They contained no quantitative
architectural comparison with others. It is because existing architectures of LC-VCO
have not achieved the optimal parameters. The proposed innovative approach of LC-
VCO design has low power, superior noise performance, which proved to serve the
most sought WLAN applications (as Wi-Fi in IEEE 802.11) in modern wireless stan-
dards. The LC-VCO is finally targeted to embed onto the synthesizer chip, to address
the most sought WiFi applications in the narrowband WLAN range (S-Band). The

active differential architecture, which is a cross-coupled NMOS structure, has been
envisaged for the gain which counters the losses of the LC resonator. First of all, the
driving specifications of the LC resonator are obtained from the required tuned fre-
quency which in the present case is 5400–5495 MHz. The stacked on-chip Inductor
has been designed for low losses and for C-Band applications which comes up with
adequate size to be feasible enough to be implemented with the said process. The
losses in the LC resonator which has been achieved by the cross-coupled NMOS pair
(NMOS-CCP). CCP brings in the negative resistance, thereby compensating for the
losses that occurred in the LC resonator and initializing the oscillations with its positive
feedback topology. The complete LC-VCO circuit has been simulated and checked
for the major concerns mentioned above. In light of this, we designed a Quadrature
Voltage Controlled Oscillator (QVCO) in 130 nm CMOS technology to encompass
the most sought-after WLAN/WiFi spectrum of contemporary wireless systems, using
the current reuse method and an on-chip inductor implementation. It is shown here
that the proposed Quadrature Voltage Controlled Oscillator provides a robust structure
and optimum power with better phase noise performance when compared to the best
existing design in the literature [17, 2, 5, 6, 8, 14, 21, 23–25]
The following are the main pillars of this research effort focused on LC-VCO
topologies at high frequency:
• We implement the proposed design of LC-VCO with tuned MOS varactors and
on-chip inductor based on UMC’s 130 nm RF-CMOS process technology, which is
a proven industry standard.
• The prototype model of LC-VCO for XLAN application (Bluetooth and WiFi) onto
the physical chip has been demonstrated, which is the first time in the state-of-the-
artwork.
• We estimate the driving specifications of the LC resonator for the required tuned
frequency which in the present case is 5400–5495 MHz (C-Band).
• We evaluate that the proposed stacked on-chip inductor has low losses for C-Band
applications that acquire with sufficient size to be practical enough to be imple-
mented with the stated 130 nm RF-CMOS technology.
• We perform the simulation of the combined LC-VCO designs using UMC’s 130 nm
RF-CMOS process technology using the industry-standard ADS (Keysight technol-
ogy) platform.
• Post-simulation analysis has been performed and showed that the combined LC-
VCO design achieves the best and/or optimal parameters like extremely low phase
noise, low power dissipation, and high Q operation as compared to the best existing
designs in the literature and this proposed design is very useful for Wi-Fi applica-
tions.
• The parameters of the proposed design of LC-VCO have been estimated (rather
precisely calculated) based on the simulation results such as power Dissipation of
6.52 mW, Phase Noise of 160 dBc/Hz at 1 MHz, Tuning Range of 5400–5495 MHz,
Voltage tuning of 150–250 mV and Kvco: 2.375 MHz/mV.
• At the conclusion of the article, a rigorous performance comparison of LC-VCO
topologies at high frequency has been performed, and the suggested design work
exhibits the best results when compared to the most recent existing works (high-
lighted in Table 4).The result of the LC-VCO topologies at high frequencies is

compared in Table 4, which shows the superiority of the proposed design of the
LC-VCO topologies with the latest existing state-of-the artwork.
The remaining of the article is as below: Sect. 2 explains the realization of the newly
designed QVCO architecture based on CMOS technology intent. On-chip stacked
inductor and MOS varactor implementation for fine LC tuning are demonstrated in
Sect. 2.1. The simulation outcomes of the proposed circuit like the LC-QVCO design
are displayed in Sect. 3. Finally, a strong conclusion is provided to this research work
in Sect. 4.
2 Analysis of the Proposed QVCO Design
Figure 2 shows the complete proposed design of the LC—Quadrature VCO. Individual
blocks have been nomenclature. Two similar sections of CMOS cross-coupled pair
along with LC resonator are employed in back-gate topology to achieve the quadrature
operation. Iplus and Iminus are the pair of inverted outputs, whereas Qplus and Qminus
are the quadrature outputs. As can be seen, the LC resonator section is employed using
NMOS-varactor and a stacked on-chip inductor. Back gate topology employed with
M33-M40 performs the current reuse via shared cross-coupled drain terminals. The
complete schematic of quadrature LC-VCO is presented in Fig. 2.
Fig. 2 Complete design of quadrature LC-VCO topology implemented using stacked inductor proposed in
this work

Lots of aspects have been investigated and quantitative efforts have been reported
already by many published articles. The conclusive results and analysis from there
have been sought as the foundation for the following aspects of the designed VCO
here:
(i) Superior Phase Noise Performance Integrated on-chip Inductor topology along
with MOS varactors in CMOS implementation of CCP (Cross Coupled Pair) has
been opted to obtain the same.
(ii) Highly Compact and Integrated Solution The whole design and implementation
is targeted in 130 nm RF-CMOS technology, which for analog-RF technologies,
considered to be the most optimum process node. On-chip inductor implemen-
tation adds to this aspect again.
(iii) Most Sought WLAN Application (WiFi) To obtain the frequency tuning at such a
higher frequency range of 5.4 GHz, specific constraints on LC resonator are to
be imposed, like on-chip implementation with small values (1–10 nH for L, and
500–1000 fF for C). Designing these lower ranges passive components requires
a high level of accuracy in modelling and calculations.
(iv) Low Power Dissipation While serving for loss compensation, the active circuitry
of a VCO utilizes relatively a larger power than conventional analog blocks.
CMOS cross-coupled differential amplifier structure has been adopted to tackle
the lower power aspect of the active part.
The following sub-sections A, B and C (along with steps 1 to 4 mentioned within),
will now complete the design flow of the proposed LC-Quadrature VCO.
2.1 On-Chip Stacked Inductor and MOS Varactor Implementation for Fine LC
Tuning
For any tuned oscillator, fixing the LC resonator design is the first thing to start with.
Two important aspects are encountered in this first step, one is the frequency tuning
coverage, which sets the designed values for inductor and varactors. The losses expe-
rienced in the LC resonator are also significant, which necessitates the addition of the
active component to compensate. The parasitic resistive losses with inductor imple-
mentation are more significant than those of capacitors [2]. The topologies adopted
in the IC implementation of the inductors mainly involve their implementation in the
one-dimensional plane, which then suffers from the substrate loss, and places tight
constraints over the physical of inductors. This, in turn, results in the Q factor below 20
at the high-frequency applications (gigahertz range) in general. These losses and there-
fore the quality factor determine the phase noise performance of voltage-controlled
oscillators. Consequently, an integrated inductor needs to be designed with extreme
care to meet the design challenges specifically to achieve a reasonable Q factor [1].
Steps 1 to 4 below (1 and 2 in this section + 3 and 4 in the next section), discuss and
summarize the design and implementation of the LC-resonator section of the proposed
design, using Advanced Design System (ADS from Keysight Technologies), in 130 nm
RF-CMOS process (by UMC).

Fig. 3 Design a LC resonator loss model b resonator implementation and loss estimation setup
Step 1 (Start Point) Targeting tuned frequency of 2.4 GHz, for a considerable
phase noise performance (this re-establishes the adoption of LC tank based resonating
structure).
Step 2 (LC values’ estimation) While implementing the LC Tank resonator (Fig. 3),
the design efforts have mainly been focused on Inductor, rather than MOS-Capacitor.
The value of Cres is speculated using Eq. (1) mentioned below, for a feasible inductor
size in the range 1–10 nH (for the technology in hand) and targeted frequency of
operation (5400 MHz).
Cres =
1
Lres(2π fres)2
(1)
This gives an approximated value of Cres (which is to be obtained from MOS-
Varactor), in the range of 850 (for 1 nH)–180 fF (for 5 nH). This gives the opportunity
and a node of technological permission to go for the inductor design of a certain
value, as the range of capacitance is feasible with the 130 nm CMOS technology with
optimal dimensions of the device (W/L) giving expected Cmax/Cmin ratio. To fix the
tuning responsibility with capacitors (that is varactors) only, the inductor value needs
to be fixed (as estimated within 1–10 nH), before one plans to fix the tuning range of
capacitance values.
Step 3 (MOS varactor design) Value of Cres in the range of 840–870 fF seems to be
feasible to go for obtaining Cmax/Cmin as 1.036. This range of capacitance is in good
agreement with the technology of implementation here. But a little overestimation in
Cres is also considered, as some of the capacitive parasitics are also to be obtained
from adjacent nodes (port 1 and 2 of Fig. 3) when it is implemented on Silicon. Now
to obtain the tuned capacitance of the obtained values above, the well-established
methods of varactor implementation are mostly used. NMOS-based varactor has been
the most favourable choice for most of the modern CMOS processes, where the thin
and high-quality gate oxide is used as the tuned capacitance. The accumulation mode
of the NMOS-based varactors is best suited for the wider tunable capacitance [1, 9].
The drain-source sides are more sensitive to the signal noise perturbations, therefore

as a good practice, the gate side of the transistors are offered to withstand the larger
signal variation concerning the drain-source terminal as shown in Fig. 3b. This, in turn,
otherwise might observe the poor signal integrity and noise coupling from adjacent
devices of integrated PLL synthesizer where this LC-VCO has to sit.
Obtaining the required Cmax/Cmin of 1.036 for L = 1 nH:
• Required Cmin (for f max = 5495 MHz of WiFi/IEEE 802.11 standard) = 840 fF
• Required Cmax (for f min = 5400 MHz of WiFi/IEEE 802.11 standard) = 870 fF
Hence Cmax/Cmin = 1.036, this low value does not place any significant constraints
on MOS varactor sizing. The simulation setup is presented in Fig. 3, which performs
the s-parameter simulation and provides the desired W/L ratio (for L = Lmin = 120 nm)
of M31 and M32 (acting as MOS varactors) for given Cmax and Cmin values from the
reactive component of the impedance evaluated from termination. The technology
(0.13 µm CMOS) in hand, offers the required range of capacitance for the targeted
range (5400 MHz- 5495 MHz) as 870 fF for 5400 MHz to 840 fF for 5495 MHz using
a standard inductance of 1 nH (Eq. (1)).
Step 4 (Inductor Implementation) The proposed work describes the design and
implementation of an on-chip stacked inductor topology that benefits from high quality
factor and better phase noise performance. An effective on-chip stacked inductor
design, therefore, has been achieved in this work in UMC’s 130 nm N-well RF-CMOS
process (Fig. 4). The process foundry provides the layout design specifications of the
inductor is:
InductorValue(L) ≈ 1.3 × 10−7
·

A
5/3
m
A
1/6
tot · W1.75 · (W + S)1/4

(2)
Equation (3) is one of the possible models for the spiral on-chip inductor design
and has been incorporated here due to its simplicity. Other complicated and more
statistical models are also available for better accuracy. In Eq. (3(a)), Am is the metal
area (spiral periphery) and Atot is the total inductor area, given by:
Am = 2π ·

Do
2

· W · Nt (3(a))
Fig. 4 Prototype physical layout
of the inductor topology chosen
in the design

Atot = π ·
D2
o
4
(3(b))
The implemented inductor topology and its layout are shown in Fig. 4 and the
theoretically obtained parameter values for 1 nH have been listed out in Table 1. The
figure shown is a prototype model of the actual designed Inductor.
The required dimensions for the inductor layout have been evaluated according to
Eqs. (2) and (3(a)) and values are listed in Table 1 below:
Table 2 displays the simulation results for the inductor modelling as well as the
loss calculations. The losses were modelled as typical parallel resistance (Rp), which
would subsequently make the task of compensating by the active component (cross-
coupled differential amplifier) in the shunt easier. Table 2 also includes a summary of
the relevant quality factor.
The effective loss component of this LC resonator with the designed values men-
tioned above comes out to be in the range 400–500 approximately at the desired
Table 1 Design parameters and layout specification of the implemented inductor in the proposed work
Parameter Description Value
L Implemented inductor value (for layout in Fig. 4) 1 nH
Do (od) The outermost diameter of inductor 150 µm
W (W) Inductor’s top metal width (process governed completely) 9.7 µm
S Inductor’s top metal spacing 2.5 µm
Nt Inductor’s turn number 2.5
Table 2 Result of On-Chip Inductor with equivalent losses (L, QL and RP)
Frequency (GHz) L Frequency (GHz) QL Frequency (GHz) RP
1 1.054E−9 1 5.011 1 33.185
2 1.049E−9 2 8.540 2 112.532
3 1.045E−9 3 10.951 3 215.760
4 1.046E−9 4 12.783 4 335.966
5 1.050E−9 5 14.221 5 46.162
6 1.058E−9 6 15.300 6 610.268
7 1.069E−9 7 16.033 7 753.852
8 1.083E−9 8 16.443 8 895.150
9 1.100E−9 9 16.567 9 1030.562
10 1.120E−9 10 16.450 10 1157.705
11 1.143 E−9 11 16.137 11 1275.246
12 1.170E−9 12 15.66 12 132.648

frequency range of 5.4 GHz (Table 2). Now the cross-coupled active differential pair
will have an initial design constraint of compensating this lossy component.
2.2 Quadrature Signal Generation uses Current Reuse Technique (Back-Gate
Topology)
Quadrature signals are one, which maintains the phase difference of 90° between
each other, at the same carrier frequency. Most of the modern wireless and digital
communication systems employ the use of quadrature signals, due to the generation
and transmission efficiency and higher data rate. The image cancellation method is
extremely successful in quadrature signal processing, which eliminates the need for
an IF filter step. As a result, quadrature structures have become the preferred option
for direct conversion receivers [15].
Various methods like poly-phase filters, delay-locked loops, ring oscillators, fre-
quency dividers and quadrature VCOs have been developed and implemented in
various works, but the Quadrature-VCOs usually outperform among all the possi-
ble methods of quadrature generations discussed above. The most significant benefit
of using QVCO is the low power dissipation characteristic, despite having a conse-
quence of the relatively larger chip area. To exploit this remarkable advantage, plenty
of schemes to incorporate the quadrature generation with voltage-controlled oscilla-
tors have been reported and published, like VCO with polyphase filter [26], VCO
comprising frequency doubler in ring oscillator architecture [2] and Quadrature VCO
[11]. The LC-VCO topology has shown its superiority ineffectiveness in the quadra-
ture generation with a little more power dissipation relatively. This also adds on to
achieve low phase noise among all possible quadrature signal generation techniques
[16]. In this trend, a Back-Gate topology for LC-QVCO employing the current reuse
phenomenon in the differential structure has been adopted in this work (Fig. 5).
Fig. 5 Proposed design a Back-Gate topology for quadrature generation b Small signal diagram of back
gate coupled transistors

In the back-gate topology adopted above (Fig. 5a), MS1 and MS3 from the pair
with MS2 and MS4, respectively. This Quadrature VCO configuration is very effective
in producing the negative conductance with relatively less power consumption due
to the current reuse from the drain terminal used here. Whereas an additional noise
and power dissipation of 40–70% in the core transistors is generally observed with
other contemporary topologies [12]. This negative conductance then performs the
loss compensation to the LC resonator section and thereby helps in sustaining the
oscillations. The additional transistors (MS3–MS4) at the same drain terminal of MS1
and MS2 maintain the quadrature with another similar block of the cross-coupled
structure as shown in Fig. 2. The ports A, B, C and D are accessed as the quadrature
phased signals along with the other differential pair. The small-signal diagram of the
back gate coupled transistors (Fig. 5b), clearly depicts the phenomenon of current
reuse at node A via parallel transistors MS3 and MS1.
So far, the LC-VCO design stages and implementation details have been given. The
section that follows will now detail the operational performance of the proposed VCO
design, which is built in 130 nm CMOS technology and is based on RF simulations
in ADS (from Keysight Technologies). Even though the major focus is kept on tuning
coverage with power dissipation and phase noise performance, the other important
aspects such as linearity, gain sensitivity and Figure of Merit (FoM) are also briefly
discussed and evaluated.
2.3 Cross-Coupled Pair (CCP) Active Part Design
As previously stated, in order to compensate for the LC resonator portion, an active
component must be constructed with suitable design to fit within the work’s noise and
power constraints. Because of the CMOS compatibility, a cross-coupled pair (CCP)
with NMOS-PMOS offers the necessary negative conductance and is ideally suited for
this task (shown in Fig. 2). The design results with transistor sizes are tabulated below
(Table 3), providing a negative conductance of 2 mS to compensate for the worst-hit
500 loss component achieved above (Table 2). The design results are performed for
the bias current of 5.5 mA with 1.2 V bias supply of 130 nm CMOS process.
The added benefit of using the CMOS architecture for CCP implementation is that
it reduces current bias and therefore power dissipation since the responsibility for
supplying negative conductance is half and divided between the NMOS and PMOS
cross-coupled pairs. The overall conductance has been achieved as 2.55 mS adding the
Table 3 CCP-Differential Structure Design and Simulated Conductance for Loss Compensation
CCP-Transistors
(refer to Fig. 2)
W/L (aspect ratio)
Technology: 130 nm RF-CMOS
Trans-conductance (mS)
NMOS CCP
M33, M35, M39, M40
6/1 1.37
PMOS CCP
M45, M46
2/1 1.18

shunt conductance from Table 3. This conductance value has been estimated carefully,
to fully take on the resistive losses with some margin, and also to fit into the optimized
power requirements.
3 Proposed LC-QVCO Circuit’s Behaviour and Simulation Results
The s-parameter simulation results are shown in Fig. 6 where the frequency sweep has
been performed to cover the entire Wi-Fi range, which is from 5.400 to 5.495 GHz
(bandwidth of 95 MHz approximately) for a voltage tuning approximately from 160
to 240 mV. The complete proposed design architecture has already been presented in
Fig. 2. The frequency coverage again entitles the design for the Wi-Fi applications in
modern WLAN standards.
3.1 Linearity and VCO Tuning
The linearity and gain of the VCO are also essential parameters for most PLL imple-
mentations. On the one hand, linearity and gain determine the stability and dynamics of
the Phase-locked loop, while on the other hand, distortion and phase noise performance
of the VCO are taken into consideration. In most of the applications, the sensitivity
of VCO could be directly interpreted as the gain of the VCO (KVCO) and defined as
the output frequency per unit change in the input control voltage. Figure 7 depicts the
complete relation of the covered spectrum concerning the tuned input voltage which
therefore demonstrates the gain of the VCO also.
The simulation results, as shown in the graph above, demonstrate the benefit of
this suggested design for the good extent of linearity. This feature is highly essential
Fig. 6 RF (S-parameter simulation) for S21 Phase; showing the frequency range covered

5.39
5.419
5.429
5.442
5.453
5.463
5.471
5.478
5.485
5.49
5.495
5.32
5.34
5.36
5.38
5.4
5.42
5.44
5.46
5.48
5.5
5.52
188 192 196 200 204 208 212 216 220 224 228
TUNED
FREQUENCY
(GHZ)
CONTROL VOLTAGE-VTUNE (MILLI-VOLTS)
Fig. 7 Tuned frequency versus tuning range (m3–m4) demonstrating the Linearity of VCO
specifically in the applications sought by the design. Though a little nonlinearity
of the proposed design (Fig. 7) offers some non-ideal impairments like cross and
inter-modulation for the application targeted, a highly linear VCO is impractical with
the methodologies of implementation available. The tuned voltage (Vtune) for the
frequency coverage comes out to be 170–240 mV in the chosen process with 1.2 V
supply bias. This provides the gain of VCO (KVCO) to be 2.375 MHz/mV, which is a
fairly optimal value with the type of PLL applications it envisages, for the dynamics
concern.
3.2 Power Dissipation and Phase Noise Performance
An analog/RF circuit’s power dissipation and phase noise behavior are the two most
significant and inversely linked characteristics. The assessment of phase noise per-
formance alone would be a partial characterization for VCO, while the inclusion of
power analysis would paint a more complete picture of total performance and define
the Figure of Merit (FoM). The phase noise behavior could be characterized from both
the time domain jitter aspect and using the frequency domain spectrum purity [15, 16].
In this work, the characterization of the phase noise from the RF spectrum has been
used; the RF output noise in one sideband in a 1 Hz bandwidth is used to define Ltotal
is a well-established and standard definition and is given by Eq. (4).
Ltotal(ω) =
noisepowerin 1 HzBWat ωo + ω
totalcarrierpower
(4)
In this form Ltotal depends on the effect of phase and amplitude variations (Eq. (4)).
In many circuits, the effect of amplitude variations can be eliminated by passing the
signal through an explicit or implicit limiting stage but the effect of phase variations
cannot be reduced [14]. For most applications only the phase portion Lphase of Ltotal is

Fig. 8 Phase Noise results from HF simulations to fundamental at 5.450 GHz
important and is denoted as L(ω).The even harmonics are significantly suppressed
by the virtue of the balanced cross-coupled differential structure of the NMOS-PMOS
pair, used for the amplification. Another significant aspect of the differential structure
of the active design used in this study is that the differential structure topology avoids
even harmonics owing to its balanced nature.
The remarkable phase noise performance shown by the proposed LC-Quadrature
VCO has been analyzed and displayed in Fig. 8, where the differential output signal’s
(Iplus − Iminus) noise spectrum has been plotted. Phase noise of − 160.04 dB is
achieved at 1 MHz offset from 5.450 GHz which is the centre of the tuned frequency
range. This reasonable value confirms the benefits of on-chip inductor implementation,
particularly with a cross-coupled CMOS differential pair.
The power dissipation in most of the large-signal circuits like RF-Oscillators, for a
constant voltage swing (Vsw), can be derived and analyzed as in Eqs. (5) and (6) [16].
Vsw =
(ωL)2
Rs
Ibias =
(ωL)2
Rs
Power
VDD
(5)
Power =
Rs VswVDD
(ωL)2
(6)
Rs has been opted as approx. 400 ohms from the LC loss simulation in the previous
section, to calculate the maximum power loss. With the current nearly 2 mA (each
transistor) and power supply of 1.2 V in the work, the power dissipation comes out
to be 6.52 mW, which is fairly small and deserves to be appreciated for low power
dissipation.
The widely and frequently used figure of merit (FoM) is used in this work [18–20]
for the characterization of VCO’s performance, which is given by Eq. (7) below as
follows:
FoM = L{ f } − 20 log

fo
f

+ 10 log

PDC
1 mW

(7)

The effect of most important phase noise behavior is embodied in the first term
to the right-hand side of Eq. (7) with value − 160 dB, the second one stands for the
quality factor of tuning operation at the centre frequency (f o = 5.45 GHz), which came
out to be − 35.17 dB. The last term final accounts for the power dissipation and has
the value of 8.14 dB. This overall gives the value of Figure of Merit (FOM) as − 187
dBc/Hz, which again stands out to be a highly appreciable value for this frequency
tuning application. The well-known frequency tuning range for such tuned oscillators
is defined by Eq. (8) below as:
FTR(%) =

fmax − fmin
fcenter

∗ 100%, (8)
where f min = 5.40 GHz and f max = 5.495 GHz, which is already a verified result and
plotted in Fig. 6, provides frequency tuning (FTR) as 1.74%. The suggested LC-QVCO
architecture’s Frequency Tuning Range (FTR) contributes to the circuit’s uniqueness,
since the type of extraordinary phase noise behaviour obtained is noteworthy, espe-
cially for this tuning range. Table 4 lists the comparative analysis of the specifications
of various VCO topologies.
The task of consolidating and comparing various LC-VCO designs with the pro-
posed one is not easy, due to the variety of topologies and implementation available.
The suggested LC-VCO designs were validated using ADS software (from Keysight
Technologies) and functionally tested, yielding optimum characteristics like as power
dissipation, phase noise, tuning range, voltage tuning, and Kvco when compared to
the most recent current designs [17, 2, 5, 14, 21, 23–25]. Nonetheless, some rele-
vant contemporary designs from popular and recent articles have been chosen which
have intended to place the efforts in the similar direction of the present work. Table
4, therefore, illustrates the novelty in the methodology and the parameters’ results
obtained with the proposed LC-Quadrature VCO design. Here in the proposed design
of LC-VCO achieve the very low power dissipation of 6.52 mW, which is a notably
small value for such a high type gain and low noise type VCO, which is not achieved
in any existing works [17, 2, 4, 5, 7, 14, 21, 23–25]. The comparison of the proposed
LC-VCO design results with the counterpart designs showed that the LC-VCO designs
are improved such as power dissipation, phase noise, tuning range, voltage tuning, and
Kvco.
4 Conclusion
Anewmethodforlowpower,betternoiseperformanceQuadratureVCOwasprovided,
which demonstrated to serve the most desired WLAN applications (as defined by
IEEE 802.11) in modern wireless standards. A process compatible stacked on-chip
inductor of value 1 nH was implemented and its loss characterization was performed
which set the varactor design goal for LC resonator section. The results were achieved
utilizing the 130 nm CMOS technology and the s-parameter and harmonic balancing
simulationusingADSsoftware(fromKeysightTechnologies).Foreachpart,thewhole
design process was clearly described in different stages. A voltage tuning of 100 mV

Table 4 Performance Comparison of various contemporary LC-VCO topologies at high frequencies
VCO work
(presenter)
Features Specifications
Djahanshahi et al. [5]
and Badel et al. [17]
Current-controlled oscillator
Using current mode logic circuits
Two-stage topology 2G application
Supply voltage: 1.8/2 V
Power Dissipation: 11.38/18.95
mW
Tuning range:
186–1576/650–1040 MHz
Central Frequency:
850/913 MHz
Balodi et al. [1, 2] Superior phase noise performance
High-Frequency RF applications
On-Chip inductor implementation
High gain/sensitivity
Power Dissipation: 12, 8.56 mW
Phase Noise: − 164, −
140 dBc/Hz at 1 MHz
Central Frequency: 4.2,
2.45 GHz
Process: 130 nm RF CMOS
Hong et al. [6] QVCO uses considerably less power
(1.74 mA from a 1.25-V supply) and
has minimal phase noise
Power Dissipation: 2.2 mW
(1.2 V)
Phase Noise: − 124dBc/Hz at
1 MHz
Central Frequency: 900 MHz
Technology 0.18- m triple-well
CMOS technology
Poor et al. [14] Quadrature VCO
Low noise performance using PMOS
Superharmonic injection technique
Power Dissipation: 13 mW
(1.8 V)
1 MHz
Central Frequency: 900 MHz
180 nm CMOS process
Yoon et al. [25] Quadrature VCO
Wideband
Low Phase Noise
Tuning spectrum: 0.56–2.92 GHz
Silicon area: 0.13 mm2,
1 MHz offset
40 nm CMOS process
Ullah et al. [21] Wider tuning using varactor
Distributed biased parallel varactors
High-frequency differential operation
Phase noise: − 99.2 dBc/Hz at
1 MHz
Central Frequency: 25.3 GHz
130 nm SiGe BiCMOS 8HP
process
Wang et al. [23] Linearized tuning gain of VCO
Application to mm-Wave (40 GHz)
Use of triple coupled inductor
Varactor compensation
Phase Noise: − 82.5 dBc/Hz at
100 kHz
Tuning Range: 38.6–44.5 GHz
Frequency Tuning (FTR):
14.3%
90 nm RF-CMOS process

Table 4 (continued)
VCO work
(presenter)
Features Specifications
Xi et al. [24] High Freq. (Bluetooth) application
Low phase error LC-Quadrature VCO
Using dual tail current bias coupling
Reconfigurable phase shift
(1.2 V)
Phase Noise: − 130 dBc/Hz at
1 MHz
Central Frequency: 2.4 GHz
130 nm CMOS process
This work Extremely low phase noise
Low power dissipation
High Q operation
Wi-Fi Application (C-Band)
Optimum Linearity
Phase noise: − 160 dBc/Hz at
1 MHz
Tuning range: 5400–5495 MHz
Voltage tuning: 150–250 mV
Kvco: 2.375 MHz/mV
Stacked Inductor on Chip
Implementation in 130 nm
RF-CMOS process
(150–250 mV) performed the targeted frequency coverage of 5400–5495 MHz, with
the excellent phase noise performance of − 160 dB/c at 1 MHz. The proposed design
also showed a very low power dissipation of 6.52 mW, which is a remarkably small
value for such a high gain and low noise VCO. The resolution in the required frequency
range was rather high, allowing for fine-tuning for many users at the same time. With a
good FoM of − 187 dB, the quadrature signal generation utilizing back gate topology
qualifies the proposed design for most contemporary high data rate wireless systems.
The gain of VCO was moderately high at 2.375 MHz/mV and hence would attribute
to the faster settling characteristic of this VCO in PLL application.
Authors’contributions IUKinvolvedinconceptualization,methodology,software,writing.DBparticipated
in data curation, project administration, validation. NKM: involved in conceptualization, methodology,
software, visualization, writing—review and editing, validation, supervision, original draft.
Funding Not applicable.
Availability of data and material Data can be available on request to corresponding author.
Declarations
Conflict of interest The authors declare that they have no conflict of interest.
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