1. On the reliability of majority logic structure in quantum-dot
cellular automata
Bibhash Sen a,n
, Yashraj Sahu b
, Rijoy Mukherjee a
, Rajdeep Kumar Nath a
, Biplab K. Sikdar c
a
Department of Computer Science and Engineering, National Institute of Technology, Durgapur, India
b
Department of Computer Science and Engineering, SUIIT, Burla, Odisha, India
c
Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology, Shibpur, India
a r t i c l e i n f o
Article history:
Received 22 July 2015
Received in revised form
6 November 2015
Accepted 7 November 2015
Keywords:
Quantum-dot cellular automata (QCA)
Reliability
Fault tolerant logic
QCA tiles
QCA defects
Majority voter
a b s t r a c t
Quantum-dot cellular automata (QCA) is projected to be a promising nanotechnology due to its extre-
mely small feature size and ultra low power consumption. However, acceptance of a QCA design is
limited due to its high defect rate. Efficient fault tolerant schemes are, therefore, needed for reliable
design. This work targets design of a new fault tolerant scheme around QCA logic primitives which
encapsulates two different orientations of QCA cell. A 2 Â 2 array of four rotated (‘þ’) cells, called
complementary tile (CT), is introduced to maximize the throughput. It ensures 100% fault tolerance
under single cell missing defect. Two reliable majority voters (RMV), based on the CT, are designed which
outperforms the existing majority logic in QCA. The functional characterization and polarization of RMV
under different cell deposition (missing/additional) defects are covered. The significance of the clocking
in fault tolerance is also investigated with RMV with multi clock zone. The error probability model for the
proposed RMV, under cell deposition (missing/additional) defect, is developed to ensure better under-
standing of reliability in QCA.
& 2015 Elsevier Ltd. All rights reserved.
1. Introduction
As CMOS devices reach their fundamental limits, they will
increasingly suffer from lower design tolerances and fabrication
variability, which have negative impacts on reliability and result in
increased device failure rates. These future limitations of CMOS
have led many to consider novel nanometer-scale devices that are
expected to have faster switching speed, lower power consump-
tion, and better scaling characteristic [1]. Quantum-dot cellular
automata (QCA) have emerged as one of the promising new
technologies for future generation ICs that overcome the limitation
of CMOS [2]. In QCA, information is transferred and transformed
by Columbic interactions among basic elements (referred to as
cells) rather than electrical currents as in CMOS-based VLSI. So the
position of a cell in the logic gate/circuit is very important as it
may result in erroneous output.
Two arrangements of quantum-dot within a cell referred to as
the 90° (‘ Â ’) normal cell and the 45° (‘þ’) rotated cell can be
utilized to compute the binary information. The rotated cell is
identical in all ways to the standard cell except it is rotated by ‘45°’
[2,3]. The fundamental unit of QCA based design is the 3-input
majority gate. Due to the functional incompleteness of majority
logic, an additional inverter is mandatory for majority gate to
constitute the universal minority function. Rigorous research is
going on towards the implementation of complex logic structure
in QCA which can be viable for alternative current CMOS [4–16].
According to [17], the predictable huge complexity of nano
architectures enforces the requirement of a high fault tolerance.
QCA also confronts the challenges of many defects which is first
explained in [18,19]. Though other fault like stray charge and
rotational defect may also occur in QCA logic, the cell misplace-
ment (cell misalignment, presence/absence of a cell) has been
identified as the prime source of defect for QCA because the pro-
cess of cell deposition is very sensitive. The importance of the
reliability of majority voter stems from its use as logic primitives in
fault-tolerant architectures around QCA [20,21].
Several attempts are made to realize fault tolerant structure
around majority logic [22–28]. To achieve a reliable architecture,
QCA tiles with redundant cells are identified as prominent one.
This approach ensures at most 67% fault tolerance under single cell
missing defect [21,20]. Realization of coplanar wire-crossing using
both 45° cell and 90° cell, as in [30], is difficult, but such restriction
can be averted with the introduction of clock zone based approach
as described in [31,4]. The fabrication issue related to cell
Contents lists available at ScienceDirect
journal homepage: www.elsevier.com/locate/mejo
Microelectronics Journal
http://dx.doi.org/10.1016/j.mejo.2015.11.002
0026-2692/& 2015 Elsevier Ltd. All rights reserved.
n
Corresponding author. Tel.: þ91 343 275 4237.
E-mail addresses: bibhash.sen@cse.nitdgp.ac.in (B. Sen),
ysahu99@gmail.com (Y. Sahu), rijoy.mukherjee@gmail.com (R. Mukherjee),
rkd769@gmail.com (R.K. Nath), biplab@cs.becs.ac.in (B.K. Sikdar).
Microelectronics Journal 47 (2016) 7–18

2. placement of rotated and non-rotated cell towards the realization
of coplanar wire-crossing is addressed in [4].
On the other hand, Von Neumann proposes probabilistic char-
acteristics of a system in which each component can fail inde-
pendently with a probability of ε [32]. Neumann states that a
system built with unreliable components can compute reliably
when ε is sufficiently small. In general, a reliable system is defined
as one that performs computation with a probability of output
error less than 1=2. When the probability of output error reaches 1
2,
the results of computation become irrelevant to the inputs and
restoration of the outputs to correct signal values is not possible.
In this context, we attempt to design reliable QCA logic pri-
mitives that can ensure highly fault tolerant QCA designs, under
different cell deposition (missing/additional) defects. The issue of
fault tolerance has been so far analysed from an implementation
technology point of view [17,33] and very few on architectural
point of view [27,28]. In this paper we study the issue of fault
tolerance from an architectural point of view. At this point,
designing QCA is an “in-principle” activity meant to explore what
might be possible if and when the fabrication issues are overcome
[3]. This work focuses on the architectural issues associated with
cell deposition (missing/additional) defects which occur during
manufacturing of circuits. The major contributions of this work
around reliable QCA architecture can be summarized as follows:
This paper investigates a new design of the tiniest QCA tile
structure (2 Â 2) with hybrid cell (cell with ‘ Â ’ and ‘þ’ orien-
tation), called complementary tile (CT). The reliability of the
QCA structure CT is reported.
Based on the proposed QCA CT, a new reliable majority voter
(RMV) is developed which achieves a high degree of robustness
in terms of misalignment, missing, and dislocation of cells. The
effectiveness of the design is established as physical proofs as
well as through simulation.
Detailed characterization of functional properties of the pro-
posed logic is described.
Estimation of error-reliability trade off of a QCA circuit is
explored with error probability model.
It is established over the other existing implementations that
the proposed majority gate (RMV) demonstrates significant
improvement in terms of area, complexity, and robustness.
This paper is organized as follows. Section 2 deals with pre-
liminaries including a brief overview of QCA technology. Related
works on the fault tolerant architecture are explored in Section 3.
The proposed design of complementary tile is introduced in Sec-
tion 5. In Section 5.3, the performance of proposed CT is reported.
In Section 6, a reliable architecture of majority voter based on CT is
presented. The reliability of the proposed RMV is analyzed in
Section 7 followed by the introduction of error probability metric
around RMV, to measure its reliability, in Section 8. Simulation and
framework is elaborated in Section 4. The conclusion is in Section
10.
2. QCA basics
A QCA cell consists of four quantum dots positioned at the
corners of a square (Fig. 1(a)) and contains two free electrons [34].
The two free electrons can quantum-mechanically tunnel among
the dots and settle either in polarization P¼ À1 or in P¼ þ1 as
shown in Fig. 1(b). A QCA cell with polarization P¼ À1 denotes
logic 0 state. On the other hand, polarization P¼ þ1 defines the
logic 1 state of the cell. Timing in QCA is accomplished by the
cascaded clocking of four distinct and periodic phases [34,4] as
shown in Fig. 1(f).
The basic structure in QCA is the 3-input majority voter, MV(A,
B,C)¼ABþBCþCA (Fig. 1(e)). It can also function as a 2-input AND
or a 2-input OR logic, if one of the three input cells is fixed to
P¼ À1 or P¼ þ1. The QCA inverter realized in two different
orientations is shown in Fig. 1(d). Using simple chain of rotated
cell (45°)/þ-cell an inverter chain can be realised as shown in
Fig. 1(d). In QCA based logic, two kinds of wire crossover, called
coplanar crossover and multilayer crossover, are possible. Due to
the fabrication constraints, multilayer wire crossing is not
explained here. Fig. 1(e) describes the co-planar wire crossing
considering a 90° ( Â -cell) and a 45° (þ-cell) structure.
The position of the electrons can be found out using Eq. (1). The
state energy is found out by calculating electrostatic energy
between each cell and its adjacent cell. Electrostatic energy
between two quantum dots in cell i and cell j is calculated as
shown in the following equation [35]:
Ei;j ¼
qiqj
4πεoεr jri;j j
ð1Þ
where, ϵ0 is the permittivity of free space and ϵr is the relative
permittivity of the material of the quantum cell. qi and qj are the
charges of the electron dots at i and j and the distance between the
two dots is given by ri;j ¼ jri Àrj j . The above equation is used to
calculate the electrostatic energy of the electrons inside faulty
device cell for every different input. The configuration having the
minimum energy for a particular input is considered to be the
most stable orientation.
Kink energy: The energy of the cell can be calculated by sum-
ming over kink energy of all dots in each cell. The Kink energy
between two adjacent cells is defined as the difference in the
electrostatic energy between the two polarization states. The kink
energy between the two cells ’i’ and ’j’, Ei;j, is calculated by keeping
’i’ in its original state (constant) and ’j’ in the two different
polarization states, and then finding the difference between these
two energies:
Ekink ¼ Eopp: polarization ÀEsame polarization
Ei;j ¼ Ei;j opp: polarization ÀEi;j same polarization
A A
B
B
’+’ Cell
’X’ Cell
A
OutputInput
A’
Binary ’1’
P = +1
Binary ’0’
P = −1
FMaj
C
B
A
F = AB + BC + CA
A
C
B F
2
3
4
1
Switch Release
Relax
Hold
Tunnelling
Potential
JunctionQuantum
Well Tunnel
90−degreeorientation
Localised Electron
45degreeorientation
A A’
Inverter chain
Fig. 1. QCA basics. (a) Structure of a QCA cell. (b) QCA cell with two polarization.
(c) Majority voter. (d) Inverter. (e) Wire-crossing. (f) Clocking.
B. Sen et al. / Microelectronics Journal 47 (2016) 7–188

3. Ei;j ¼
1
4πεoεr
X4
m ¼ 1
X4
n ¼ 1
qi
mqj
n
jrm;n j
ð2Þ
The kink energy is thus the difference between these two energies
(Fig. 2).
2.1. Defects in QCA
According to [19,18], defects are more likely to occur during
deposition phase (which result in cell misplacement) (Fig. 3).
These defects are mainly categorized in three parts:
Cell omission/missing: A particular cell is missing or remains
undeposited (Fig. 3(b)).
Cell displacement and misalignment: The defective cell is dis-
placed from its original direction (Fig. 3(c) and (d)).
Additional cell deposition: An additional cell is deposited on the
substrate (Fig. 3(e)). This extra cell is erroneously deposited
along the device perimeter (adjacency boundary) of the original
(defect-free) configuration (Fig. 3(a))
Rotational defect: Cell rotation is defined in the case that a cell is
in the precise location, but not aligned in the same direction as
its neighbouring cell (Fig. 3(f)).
3. Related work
Initially, a fully/non-fully populated tile structures are investi-
gated to obtain a fault tolerant design in [36]. A new approach is
proposed for the design of QCA-based majority gate by considering
two-dimensional arrays of QCA cells (tiles) rather than a single cell
in the design of such a fate. In [20], the defect tolerance properties
of PBW (processing-by-wire) are investigated when tiles are
employed using molecular QCA cells. Based on a 3 Â 3 QCA array of
cells (Fig. 4), with different input/output arrangements, different
tiles are realized. The orthogonal tile which functions as majority
logic can achieve only 66.67% fault tolerance. TMR (Triple Modular
Redundancy), is also used for fault tolerant technique where input
lines of TMR are shared by all the copies [22]. A failure in the lines
may simultaneously affect two or all copies of computations and
results in a faulty output. A logic design majority multiplexing
(Maj-MUX) has been proposed in [23] which uses NAND gates and
random permutation multiplexing to restore a bundle of faulty
copies of the same signal. It has been shown that given a sufficient
number of restorative stages and redundant copies of the same
signal, the tolerable fault rate of a computing module is very high.
However, fault tolerance of this scheme is limited by the redun-
dancy rate that the overall system can afford. Also an imple-
mentation of Maj-MUX requires a large number of wire crossing
devices in QCA which leads to crosstalk and erroneous inter-
pretation of input bits. All these factors have motivated us to come
up with a novel gate structure which reduces the use of redun-
dancy as well as the costly wire crossings.
4. Simulation setup
The design is verified using QCADesigner ver. 2.0.3. All the
majority gates has been simulated using coherence vector simu-
lation with following parameter: cell size¼18 nm, dot size¼5 nm,
radius of effect¼80 nm, layer separation¼11.5 nm, other para-
meters is set as default. The adder and flip-flop has been simulated
using the bistable approximation and the following parameters
has been used: number of samples¼128,000, cell size¼18 nm, dot
size¼5 nm, radius of effect¼65 nm, layer separation¼11.5 nm,
other parameters are set as default.
5. Design of complementary tile with hybrid cell
This section investigates an alternative tile structure to achieve
the desired fault tolerance in QCA circuit realizing multiple func-
tions in its outputs simultaneously. It also targets a compact
implementation of such logic structure, minimizing the number of
logic gates. Rotated QCA cells (45°) have inherent inversion logic
which can make an inverter chain as shown in Fig. 1(d). A new
2 Â 2 tile structure based on the rotated cell, called com-
plementary tile (CT), is formulated in this work as shown in Fig. 5
(a). In Fig. 5(a), driver cell have ‘þ’ orientation and input-output
QCA cell have ‘ Â ’ orientation. In CT, outputs ðF1 ¼ F2Þ are com-
plementary to each other (Fig. 5(c)).
An alternative complementary tile with  -cell as the driver, is
also shown in Fig. 5(b). But due to lack of proper polarization
(o0:5) this structure is discarded.
2
1
3
4
i
3
4 1
22
1
3
4
i j
2
j
4 1
3
Fig. 2. Kink Energy (Ek) of QCA cell with (a) Opposite polarization. (b) Same
polarization.
Z
F FB
dm
F
F
Extra cell
dm
X
FY Y
Z
X
Z
Y
X
Y
X
Z
X
Y
Z Z
Fig. 3. (a) Defect free majority voter. (b) Missing cell. (c) Cell displacement. (d) Cell
misalignment. (e) Additional cell. (f) Rotational cell defects.
A
B
C
F
A
B
F
C
Fig. 4. (a) Cascaded tiles. (b) Orthogonal tiles.
B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 9

4. 5.1. Physical verification of complementary tile
To verify the functioning of the proposed complementary tile,
the polarization of input cell A as well as the polarization of output
cell F1 is considered as À1 (boolean 0). Firstly, to find the position
of an electron in the output cell, the electrostatic energies at dif-
ferent positions of the driver and input cells are considered. For
each input combination, the position of the electron having the
least energy is considered to be its target position. The quantum
dots in the input cell are marked with Ea to Eb and the driver cells
are marked from E1 to E8. The quantum dots of the output cell are
marked as x and y as shown in Fig. 6. Electrostatic energy at
position x due to electron at position EA in cell ’A’ is keq=ra, where
rax is the distance between Ea and x. Similarly electrostatic energy
at position x due to electron position at Eb and E1–E8 is calculated.
The deliberation of the total electrostatic energy at position x
(denoted as Ux) is shown below.
For test case A, UA ¼ ðkeq=raxÞþðkeq=rbxÞ ¼ 0:713 Â 10À20
j;
where, keq ¼ q2
=4πεoεr ¼ 23:04 Â 10À20
Likewise, electrostatic energy at position y is calculated as
indicated in Table 1. We consider two cases
Case A: Assume that the polarization of output cell F2 to be þ1
as shown in Fig. 6(a) and measure the kink energy of the electrons
x and y of the output cell F2.
Case B: Consider the polarization of output cell F2 to be À1 as
shown in Fig. 6(b).
The kink energy is presented in Table 1. It is clear from the
above observation that case (A) has lower kink energy and is more
stable. Thus the complementary behaviour of the proposed tile is
proved.
5.2. Reliability analysis of complementary tile
In order to develop a viable and usable QCA model, it is
necessary to understand the behaviour and robustness of QCA
devices. Specifically, the effects of cell misalignment, dot dis-
placement, thermal effects, and other faults must be thoroughly
investigated. The proposed fault-tolerant CT has four driver cells.
All the faults that may occur in driver cells should be checked to
verify the correctness of this tile. Here, one of the faults (missing
cell 1) is considered. The fault tolerant capability of the com-
plementary tile can be verified from Table 1 for case (A) and case
(B). If the cell numbered 1 is missing, then the kink energy of the
system can be UT- ðUx
1 þUx
2 þUy
1 þUy
2Þ (where Ux
and Uy
denote the
energy of electrons with respect to x and y electrons respectively).
The missing cell position for cell numbered 1 for the two cases are
shown in Fig. 7. Kink energy (UT) for Fig. 7(a) is 10.923 Â 10À20
and
Kink energy (UT) for Fig. 7(b) is 19.469 Â 10À20
. The kink energy in
Fig. 7(a) is less than that of Fig. 7(b) and hence is more stable
configuration. This is true for all other cases also. Considering the
above computing, it can be deduced that the proposed structure
for implementing a fault-tolerant design in QCA is correct and
resulted in a correct state for t s occur.
A F1
F2
A
F2
F1
Fig. 5. Complementary tiles with (a) ‘þ’ driver cell. (b) ‘ Â ’ driver cell. (c) Simula-
tion result.
E3
E4
E7
4
1
2
A
F2
3E1 E2
E5
E6
E8
Ea
Eb
F1
Y
X
E3
E4
E7
4
1
2
F1A
F2
3E1 E2
X
Y
E5
E6
E8
Ea
Eb
Fig. 6. Missing cell position of CT for (a) Case A. (b) Case B.
Table 1
Estimation of kink energy at F2 under dif-
ferent polarization.
Electron x Electron y
Case A
UA ¼0.713 Â 10À20
UA ¼0.475 Â 10À20
UB ¼0.713 Â 10À20
UB ¼0.475 Â 10À20
U1 ¼1.55 Â 10À20
U1 ¼0.571 Â 10À20
U2 ¼1.69 Â 10À20
U2 ¼0.751 Â 10À20
U3 ¼1.04 Â 10À20
U3 ¼0.525 Â 10À20
U4 ¼0.575 Â 10À20
U4 ¼0.379 Â 10À20
U5 ¼1.27 Â 10À20
U5 ¼1.15 Â 10À20
U6 ¼0.856 Â 10À20
U6 ¼0.606 Â 10À20
U7 ¼0.707 Â 10À20
U7 ¼0.464 Â 10À20
U8 ¼0.515 Â 10À20
U8 ¼0.460 Â 10À20
UT ¼15.485 Â 10À20
ðJÞ
Case B
UA ¼0.543 Â 10À20
UA ¼0.465 Â 10À20
UB ¼0.465 Â 10À20
UB ¼0.543 Â 10À20
U1 ¼0.751 Â 10À20
U1 ¼0.765 Â 10À20
U2 ¼0.765 Â 10À20
U2 ¼1.55 Â 10À20
U3 ¼0.575 Â 10À20
U3 ¼0.810 Â 10À20
U4 ¼0.397 Â 10À20
U4 ¼0.525 Â 10À20
U5 ¼0.835 Â 10À20
U5 ¼10.331 Â 10À20
U6 ¼0.542 Â 10À20
U6 ¼1.15 Â 10À20
U7 ¼0.460 Â 10À20
U7 ¼0.719 Â 10À20
U8 ¼0.408 Â 10À20
U8 ¼0.707 Â 10À20
UT ¼23.306 Â10À 20
ðJÞ
A
E3
E4
E7
E6
4
3
2
X
E8Eb
Ea
Y
E5
F2
F1
E3
E4
E7
42
F1A
F2
X
Y
E5
E6
E8
Ea
Eb
3
Fig. 7. Polarization of CT under #1 cell missing defect when (a) F2 with P ¼ þ1.
(b) F2 with P ¼ À1.
B. Sen et al. / Microelectronics Journal 47 (2016) 7–1810

5. If cell 3 is missing, a negligible drop in polarization is observed
at F2 due to slight changes in polarization of the cell at that zone
(red circled in Fig. 8(a)). However, a stable output has been pro-
pagated due to the radius of effect of each cell in complementary
tile which controls the polarization of the output cells. This change
of polarization can also be nullified placing an additional cell in
between driver cell in the output cell as shown in Fig. 8(b). These
additional cells incur no penalty in terms of area or latency. When
cell 3 is missing: for input¼0, F1¼0, F2¼1, the value of kink
energy is 11:603 Â 10À 20
ðJÞ and for input¼0, F1¼0, F2¼0: kink
energy is 10:448 Â 10À 20
ðJÞ. However, a very little difference of
kink energy is estimated. Simply due to the position of output cell
and interaction of other cells in CT, it achieves the complementary
output of the input signal. Since the CT is used as a basic unit to
synthesize primitive majority logic later, no such drop in polar-
ization is found due to the radius of effect of other signal cells in
majority logic (Fig. 8(c)).
5.3. Performance analysis
The fanout is important as it is necessary for complex digital
logic circuits and is essential for compact designs, as multiple cells
can be driven by a single driver cell. Fanout in QCA is also a direct
demonstration of power gain in QCA circuits. The smallest tile
(2 Â 2) having cells in same orientation (normal tile (NT)) achieves
only fanout without any inversion output (Fig. 9 (a)). Inversion can
be realized with a floating cell placed diagonally on that tile as
shown in Fig. 9(b). But it is more prone to defect as well as its
outputs are less polarized. Recently, two new fanout with com-
plementary outputs are explored in [37] for efficient wirecrossing
in QCA. These are solely useful wiring in QCA only. No primitive
majority logic can be derived efficiently, which is one of our goals
as well.
A comparative analysis of complementary tile structures is
provided in Tables 2 and 3. The proposed CT can tolerate up to
8 nm left/right/up/down direction where as other existing can
achieve maximum 3–4 nm only. In order to achieve more stability,
electrons of QCA cells are arranged in a manner to achieve mini-
mum kink energy [38]. All other existing complementary tile
never possesses 100% fault tolerance against all single cell
deposition (missing and additional deposition both) defect as
shown in Table 3. The removal of the cell (just before the output
cell) decreases the polarization in all existing complementary tiles.
But the removal of such cell from the proposed complementary
tiles never decreases polarization. It is apparent from Table 3 that
the CT is of more stable (less kink energy) and error tolerant
(almost 100%) structure in the absence of other deviation from the
ideal architecture than the fact of the missing and additional cell
defect.
The single, double and triple fan-out tiles are also used as part
of the interconnect. The triple fanout using CT is possible as shown
in Fig. 9(f). In Fig. 9(f), F2 and F3 are inverted fanout whereas F1 is
normal fanout. So without using additional inverter logic, com-
plemented and uncomplemented output can be generated simul-
taneously. The most effective use of CT can be observed in a design
where both the F1 and F2 are utilized simultaneously.
6. Design of reliable majority logic
Utilizing the varied functionality offered by complementary tile
(CT), a novel fault tolerant design of majority gate is proposed in
this work which has a non-fully populated tile structure (Fig. 10
F2
F1
A
F2
F1
B
C
A
F2
F1A
Fig. 8. CT under cell #3 missing defect. (For interpretation of the references to
colour in this figure caption, the reader is referred to the web version of this paper.)
A
F2
F1 A
F2
F1
Input
O1
O2
O3
Input
O1 O2
A
F2
F1
A F1
F2
Fig. 9. QCA 2 Â 2 tiles. (a) Fanout. (b) Conventional complementary tile. (c) Complementary tile 1 in [37]. (d) Complementary tile 2 in [37]. (e) Complementary tile proposed
here. (f) Complementary tile with triple fanout.
Table 2
Permissible displacement of output cells.
Design Function Right
(nm)
Left (nm) Up (nm) Down
(nm)
Conventional CT (Fig. 9
(b))
F1 4.0 2.8 1.5 –
F2 1.5 – 2.8 4.1
CT1 in [37] O1 3.0 3.0 1.0 –
(Fig. 9 (c)) O3 1.0 – 3.0 3.0
CT2 in [37] O1 3.0 3.0 – 1.0
(Fig. 9 (d)) O2 4.0 4.0 – 1.0
CT Proposed F1 4.7 – 8.0 8.0
here (Fig. 9 (e)) F2 8.0 8.0 4.9 –
CT ¼ ‘Complementary tile’/tile with two complementary outputs.
B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 11

6. (a)) as opposed to existing majority gate structure. Here, ‘reliable’
and ‘fault tolerant’ terms are used alternatively. A new Reliable
Majority Voter structure (RMV) based on CT is synthesized which
realizes 3-input majority logic is shown in Fig. 10(a). The QCA-
implementation of the proposed RMV (Fig. 10(a)) has a cell count
of 12 and a delay of 1 clock zone (0.25 clock cycle). The design
covers an area of 0:01 μm2
.
On the other hand, clocking has been shown to have a sub-
stantial effect on functionality of QCA. Further, to extend the fault
tolerance capability of proposed reliable majority logic with the
introduction of clocking, an alternative structure using two clock
zones, referred to as RMV-II, is also reported in Fig. 10(b). RMV-II
can be useful in complex circuit synthesis where inputs are routed
to majority voter non-uniformly, i.e inputs are not arriving to
majority logic gate with same delay. The simulation result is
shown in Fig. 10(c) which verifies the majority logic function F ¼
ABþBC þCA of proposed RMVs.
7. Defect characterization of RMV
In the first part of this work, we discuss how the proposed
majority gate performs with respect to missing and additional cell
defects in QCA. In [39], it has been mentioned that with increase in
circuit area, number of stray charges could increases. So with the
increase in surface area, the probability of generating the desired
logic decreases. The RMV gate has a surface of 11564 nm2
% 0:01
μm2
which is almost comparable to the surface area of existing MV
gate in the literature ð9800 nm2
% 0:01 μm2
Þ. So, the performance
of both RMV and MV gate towards the effect of stray charge pre-
sent in its plane is less comparable. That is why to examine the
fault tolerance capability of the proposed logics, missing cell and
additional cell deposition defects are focused to a greater extent
here. To make concrete discussion, the object of the work is
completely centred in the missing and addition cell deposition as
identified the outstanding source of QCA defects in [40]. Here, the
term ‘DEPOSITION’ is used to refer only cell missing and extra/
additional cell defects alternatively.
7.1. Missing cell defect
The cell deposition location of the faulty majority voter is
depicted in Fig. 11. One or more cells may be missing from its
position in a QCA circuit. Table 4 shows the simulation result when
at most one cell is undeposited from the RMV and RMV-II. The
probability of generating different boolean functions versus the
number of undeposited cells is shown in Fig. 12. An exhaustive
simulation has also been pursued for the RMVs, i.e., with i unde-
posited cells, i¼1, …, 8 from the layout. For RMV, the number of
patterns of every output function when i cells are undeposited, are
shown in Table 4. Once undeposited cell defects are present, the
three input signals may also interact and different functions can be
generated at the output. In particular, variants of the majority
function (with complemented input variables) are expected due to
possible input inversion through the cells of the tile. The variants
of the majority function are referred to as MV-like functions.
The following observations can be made from the simulation
results:
(1) In almost all cases, our proposed RMV with undeposited cells
(as defects) behaves in the following two ways: wire functions
or MV/MV-like functions.
(2) Undeposited cell defects occurring in corner cells (cells 5 and
7) change the logic function of the RMV to the wire. In all
other cases of single cell missing defect, have no effect on
output and thus confirming the 75% defect tolerant design. In
Table 3
Performance of complementary tiles.
Parameter Conventional tiles (Fig. 9(b)) In [37] (Fig. 9(c)) In [37] (Fig. 9(d)) Complementary tiles proposed here (Fig. 9(e))
No. of cells 4 8 8 4
Inversion cells 1 0 0 0
Fault tolerance under single cell missing defect 50% 37.5% 100% 100%
Fault tolerance under extra single cell deposition 50% 100% 40% 100%
Kink energy 9:714 Â 10À 20
J 9:714 Â 10À20
J – 0:536 Â 10À20
J
F1
A
C
B F1
A
C
B
Fig. 10. (a) Reliable majority logic gate (RMV). (b) Alternative layout of RMV-II.
(c) Simulation result.
3
B
C
1
42
6
7 8
F1
5
P
Q R
S
T W
A
Fig. 11. Missing/additional cell position in majority gate.
B. Sen et al. / Microelectronics Journal 47 (2016) 7–1812

7. RMV-II, due to introduction of second clock zone it has no
influence on cell missing defect and thus confirms 100% defect
tolerant.
(3) In the simulations using the coherence vector engine, the
polarization level never experiences a significant drop under
cell missing defect. In all simulated occurrences, the magni-
tude of the maximum polarization is above 0.9 eV. The sta-
tistical results in the presence of up to eight undeposited cells
are summarized in Table 4. Note that by definition, the MV-
like function set does not include the MV function.
We analyze the behaviour of proposed majority gate (RMV) and
the other majority gates/tiles present in the literature with respect
to cell missing defect. Single and double-cell missing defects of the
majority gates are given in Table 5. From Table 5, it can be
observed that under one cell missing defect, the probability of
having the correct majority function at the outputs is 75% for the
RMV and 100% for the RMV-II whereas the existing majority logic
gates achieve only 20% success. Again, in double cell missing
defect the proposed RMV logics achieve 42–75% tolerance,
whereas existing majority logic gates show 0% tolerance. Even
with multiple undeposited cells, in most cases the proposed RMV
produces a stable logic function: either the wire function, or the
majority-like function (as shown in Fig. 13) which are very useful
for logic design. The average magnitude of the maximum polar-
ization level of the output when a number of cells are undeposited
as defects, is shown in Fig. 13.
7.2. Additional cell deposition defect
An extra cell (both  and þ orientation) is placed in the
regions around the driver cells of the RMV to investigate the
effects of defect arising out of additional cell deposition. The
possible additional cell depositions in RMV are P, Q, R, S, T, and W
(Fig. 11). Additional cell deposition is applied with different clock
zones to cover all possible defects of RMV-II synthesized with two
clocks-zones. All possible extra cell deposition in RMV is reported
in Table 6. The additional cell with ‘þ’ orientation at position Q
and T in RMV results in wire function. The same thing happens in
case of RMV-II due to the presence of an extra cell with ‘þ’
orientation at position Q and T irrespective of a clock-zone. Both
the proposed RMVs show inherent immunity to the remaining all
Table 4
Overall functional characterization of RMV under multiple undeposited cell defects.
Observation Results
RMV
No. of defective cells 1 2 3 4 5 6 7 8
Total defective patterns 8 28 56 70 56 28 8 1
Occurrence of wire function 2 14 36 46 31 12 2 0
Wire function percentage 25% 5% 64.28% 65.71% 55.35% 42.85% 25% 0
Occurrence of MV function 6 12 11 6 2 0 0 0
MV function percentage 75% 42.85% 19.64% 8.57% 3.57% 0 0 0
Occurrence of MV like function 0 1 2 3 2 1 0 0
MV like function percentage 0 3.57% 3.57% 4.28% 3.75% 3.57% 0 0
Occurrence of undefined function 0 1 7 15 21 15 6 1
Undefined function percentage 0 3.57% 12.5% 21.42% 37.5% 53.57% 75% 100%
RMV-II
No. of undeposited cell 1 2 3 4 5 6 7 8
No. of defective patterns 8 28 56 70 56 28 8 1
Occurrence of wire function 0 2 14 34 30 12 2 0
Wire function percentage 0% 7.14% 25% 48.57% 53.57% 42.85% 25% 0
Occurrence of MV function 8 24 33 18 6 0 0 0
MV function percentage 100% 85.71% 58.92% 25.71% 10.71% 0 0 0
Occurrence of MV like function 0 1 3 3 1 1 0 0
MV like function percentage 0 3.57% 5.35% 4.28% 1.78% 3.57% 0 0
Occurrence of undefined function 0 1 6 15 19 15 6 1
Undefined function percentage 0 3.57% 10.71% 21.42% 33.92% 53.57% 75% 100%
0
10
20
30
40
50
60
70
80
90
100
1 2 3 4 5 6 7 8
MV
MV-like
Wire
Undefined
0
10
20
30
40
50
60
70
80
90
100
1 2 3 4 5 6 7 8
MV
MV-like
Wire
Undefined
Fig. 12. Probability of output function under missing cell defect of (a) RMV.
(b) RMV-II.
B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 13

8. other cases ensuring a reliable system with more than 83% fault
against the additional cell deposition defect.
8. Error characteristics of majority gates
In this section, the error probability of the majority logics is
estimated based on the results reported in this paper. In [7], a
family of new appropriate QCA cost functions, based on its basic
logic elements (MV, inverter, wire-crossing, etc.) and delay are
proposed to evaluate a QCA design. But these are not appropriate
for evaluating the reliability of the QCA logic circuit. In this work,
the effect of different QCA defects is studied. It is found that the
number of occurrences of missing/extra cell deposition defects is
the important metrics that should be considered when comparing
reliable QCA designs. A family of new metrics for evaluating reli-
able/fault tolerant QCA circuits is next introduced.
In [41], an analytical method was provided to characterize the
input to the output error probability of majority logic with a gate
error ε. But, the defect in wires, crossovers and inverter are not
considered in the analysis. Two expressions were derived from
Von Neumann's work [32]. When all the nominal inputs are equal,
the output probability p0
is computed with respect to gate error ε
and input error p as
p0
¼ εþð1À2εÞð3p2
À2p3
Þ ð3Þ
When two of the nominal inputs are equal, the same can be
expressed as :
p0
¼ εþð1À2εÞð2pÀ3p2
þ2p3
Þ ð4Þ
In the accompanying discussion, we provide a mechanism to
compute the error probability in QCA under different cell deposi-
tion (missing/additional) defects and then we apply the above
equations of the majority logic developed in this work.
8.1. Error probability model under cell deposition defect (missing/
additional)
Error in output of the molecular QCA component can result in
due to cell missing defect, extra cell defect. Here, to compute error
Table 5
Comparative analysis of functional behaviour of majority gates under missing cell defect.
Observation Results
MV [34] OT [20] RMV RMV-II
No. of defective cells 1 2 1 2 1 2 1 2
Total defective patterns 5 10 9 36 8 28 8 28
Occurrence of wire func. 2 3 0 4 2 14 0 2
Wire func. percentage 40% 30% 0% 11.1% 25% 50% 0% 7.14%
Occurrence of INV func. 0 2 0 4 0 0 0 0
INV func. percentage 0% 20% 0% 11.1% 0% 0% 0% 0%
Occurrence of MV func. 1 0 6 13 6 12 8 24
MV func. percentage (FT%) 20% 0% 66.7% 36.1% 75% 42.86% 100% 85.71%
Occurrence of MV like func. 1 1 3 11 0 1 0 1
MV like func. percentage 20% 10% 33.3% 30.5% 0% 3.57% 0% 3.57%
Occurrence of undefined state 1 4 0 4 0 1 0 1
Undefined state percentage 20% 40% 0% 11.1% 0% 3.57% 0% 3.57%
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1 2 3 4
MV
MV-like
Wire
Undefined
Total
Fig. 13. Average polarization of RMV under cell deposition.
Table 6
Analysis of additional cell deposition defect in RMV.
Position Type Clock Polarization Output
RMV
P Â 0 0.968 Maj(A,B,C)
þ 0 0.968 Maj(A,B,C)
Q Â 0 0.969 Maj(A,B,C)
þ 0 0.968 A
R Â 0 0.968 Maj(A,B,C)
þ 0 0.970 Maj(A,B,C)
S Â 0 0.968 Maj(A,B,C)
þ 0 0.968 Maj(A,B,C)
T Â 0 0.969 Maj(A,B,C)
þ 0 0.968 C
W Â 0 0.968 Maj(A,B,C)
þ 0 0.970 Maj(A,B,C)
RMV-II
P Â 0 0.968 Maj(A,B,C)
þ 0 0.968 Maj(A,B,C)
 1 0.968 Maj(A,B,C)
þ 1 0.968 Maj(A,B,C)
Q Â 0 0.969 Maj(A,B,C)
þ 0 0.968 A
 1 0.969 Maj(A,B,C)
þ 1 0.968 A
R Â 0 0.968 Maj(A,B,C)
þ 0 0.970 Maj(A, B,C)
 1 0.968 Maj(A,B,C)
þ 1 0.970 Maj(A,B,C)
S Â 0 0.968 Maj(A,B,C)
þ 0 0.968 Maj(A,B,C)
 1 0.968 Maj(A,B,C)
þ 1 0.968 Maj(A,B,C)
T Â 0 0.969 Maj(A,B,C)
þ 0 0.968 C
 1 0.969 Maj(A,B,C)
þ 1 0.968 C
W Â 0 0.968 Maj(A,B,C)
þ 0 0.970 Maj(A,B, C)
 1 0.968 Maj(A,B,C)
þ 1 0.970 Maj(A,B,C)
B. Sen et al. / Microelectronics Journal 47 (2016) 7–1814

9. probability, we consider the error due to cell missing defect and
extra cell defect is defined. The error probability due to cell
missing defect εm is defined as
εm ¼
ε1m þε2m þε3m þε4m þ⋯þεnm
n
; ð5Þ
for a QCA component with nþ1 cells, where εim is error prob-
ability due to i cells missing from the components. For better
understanding, we limit the computation up to 2 missing cell
defects. From the missing cell defect analysis, the error probability
can be computed as
εim ¼
Number of wrong output patterns
Number of defective patterns
: ð6Þ
Similarly the error probability due to additional cell deposition
defect εd is computed as
εd ¼
Number of wrong output patterns
Number of cells deposited
: ð7Þ
Finally, the error probability ε is defined as
ε ¼
εm þεd
2
: ð8Þ
The above equations are considered to the 3 majority gates. The εm
computed based on the data provided in Table 5 for missing cell
defect are
ε1m ¼ 4
5 ¼ 0:80 using ð6Þ
ε2m ¼ 10
10 ¼ 1 using ð6Þ
εm ¼ 0:80 þ 1
2 ¼ 0:90 using ð5Þ
8
:
9
=
;
For existing majority gate
ε1m ¼ 2
8 ¼ 0:25 using ð6Þ
ε2m ¼ 16
28 ¼ 0:57 using ð6Þ
εm ¼ 0:25 þ 0:57
2 ¼ 0:41 using ð5Þ
8
:
9
=
;
For proposed RMV
ε1m ¼ 0
8 ¼ 0 using ð6Þ
ε2m ¼ 4
28 ¼ 0:143 using ð6Þ
εm ¼ 0þ 0:143
2 ¼ 0:0715 using ð5Þ
8
:
9
=
;
For proposed RMVÀII
The εd, using data in Table 6, for additional cell deposition
(applying Eq. (7)) are
εd ¼
0
4
¼ 0; for existing majority gate
εd ¼
2
12
¼ 0:167; for RMV
εd ¼
6
24
¼ 0:25; for RMVÀII
Next, we calculate the error probability ε for each majority gate
following Eq. (8):
ε ¼
0þ0:90
2
¼ 0:45; for existing majority gate
ε ¼
0:41þ0:167
2
¼ 0:2885; for RMV
ε ¼
0:0715þ0:25
2
¼ 0:161; for RMVÀII
Now, substituting the value of ε in Eqs. (3) and (4), we plot a graph
between input and output probability for 3 identical inputs
(Fig. 14) and for 2 identical inputs (Fig. 15). It can be found that the
proposed gates can provide output with less error probability for
an input error. So from both the figures, it can be concluded that
the RMV is more reliable than the existing majority gate.
9. Analysis of fault tolerance in circuit synthesized with RMV
It can be observed that in a QCA circuit, uniform clock dis-
tribution results in more reliable circuit over the random clock
distribution [42]. An coplanar adder can be designed in many ways
with the orientations of input and output [4,?,?]. Recently, a new
coplanar wire-crossing is proposed which uses aforesaid non-
adjacent clock zones for the two crossing wires [4] which incurs
most optimum circuit area. In [5], Angizi et al. stated that cells on
the hold phase (clk 1) can cross cells on the relax phase (clk 3) and
cells on the switch phase (clk 0) can cross cells on the release
phase (clk2) without polarization effect. In this work, all the wir-
ecrossings in full adder are organised with (clk 0, clk2) or (clk 1, clk
3) clock phases. Based on the clock based approach, as in [4], the
full adder circuit is synthesized using both conventional and
proposed RMV gate as shown in Fig. 16. The simulation results in
Fig. 17 verifies the correct functionality of the adder. The fault
tolerance capability implementing full adder is reported in Table 7.
It is evident that proposed RMV logic outperforms over the con-
ventional majority logic with enviable 90.58% fault tolerance. Also,
a 4-bit ripple carry adder is implemented with the proposed RMV
as shown in Fig. 18.
However, it is found that for a complex circuit, the incoming
signals to driver cell of majority logic may traverse an unequal
MV
RMV
RMV-II
p=p’
Fig. 14. Output error probability vs. input error probability of majority gates with
all inputs identical.
MV
RMV
RMV-II
p=p’
Fig. 15. Output error probability vs. input error probability of majority gates with
2 inputs identical.
B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 15

10. number of cells/wire-length and that results in more delay in
signal propagation and switching. So, if the driver cell is placed in
the same clock zone as that of the wire for the incoming signal, the
desired function may not be generated. The input signal with less
propagation time controls the device cell. Therefore, if the wires
from the inputs are in clock zone d, then majority gate is placed in
ðdþ1Þmod 4 clock zone. If the generated function is to be used as
input to another gate then the wires leading to that gate is placed
in ðdþ2Þmod 4 clock zone and so on. So number of clock zones
required for such complex circuit increases. In this scenario, the
proposed majority gate (RMV-II) with 2 clock zones, is found to be
most efficient. The wire from the inputs of various lengths leading
to the gate can be in the same clock zone (assume d) as that of the
driver cell. Only, CT needs to be in a different clock zone of
ðdþ1Þmod 4. Already the performance of proposed RMV is found
impressive over conventional logic implementing full adder cir-
cuit. In the following paragraph, we described the performance of
the proposed RMV-II implementing D flip-flop which utilizes
aforesaid clocking scheme.
The D flip-flop circuit is synthesized using both the proposed
RMVs gate as shown in Fig. 19. Missing cell deposition defects of
RMV and RMV-II in implementing adder circuits and D Flip-flops
are reported in Table 8. The Majority with two clock zone (RMV-II)
is much more fault tolerant in both the cases. Thus, it can be
concluded that the very large/complex circuit constructed with
RMV-II is more cost effective in terms of both signal propagation
and fault tolerance.
Table 7
Performance of majority logics implementing full adder.
Design Observation No. of missing cell deposition
1 2 3
No. of defective patterns 15 30 30
Majoritya
No. of correct output 1 0 0
Fault tolerance (%) 6.67 0 0
No. of defective patterns 24 84 168
RMV No. of correct output 17 33 30
Fault tolerance (%) 70.83 41.67 17.85
Improvement in fault tolerance is 90.58%.
a
Conventional majority logic.
A0B0
Cin
B1 A1
B2 A2
B3 A3
Cout
S0S1S2
S3
Fig. 18. 4-bit ripple carry adder's (RCA) using RMV.
Fig. 17. Simulation result of adder circuit using RMV gate.
S
Cout
XY
Cin
XY
Cin
Cout
S
Fig. 16. Adder circuit using (a) conventional majority. (b) RMV gate.
B. Sen et al. / Microelectronics Journal 47 (2016) 7–1816

11. 10. Conclusion
This work has presented a novel design of fault tolerant
majority logic primitives by employing basic block (referred to as
complementary tile) for assembling QCA circuits prior to cell
deposition on a substrate. The complementary tile proposed here
consists of 2 Â 2 grid of cells with two complementary outputs
(F1 ¼ F2) achieving 100% fault tolerance under single cell missing
defect. A reliable majority voter (RMV) is then developed around
the proposed CT. The proposed RMV structure is also found to be
fault tolerant under cell deposition (missing/additional) defects.
Further, the reliability of RMV is estimated based on the analysis of
output error probability. It ensures the better robustness of RMV
and is at least 50% more than that of the existing majority logic in
QCA. The multiple undeposited cell defects in RMV deterministi-
cally lead to a new logic functions in some cases. Thus, the simple
arrangement in the cells and clocking makes RMV tile a viable
fault tolerant design technique for QCA. To surmount the limita-
tion signal distribution in circuit level, the proposed RMV-II model
is evolved as an effective module minimizing overall delay and
cost of the circuit.
Acknowledgements
The authors would like to convey their sincere thanks to the
anonymous reviewers for their valuable suggestions that helped in
improving the paper.
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FT 87.5 70.24% 54.76%
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FT, Fault tolerance.
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