Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer scale with high integration density, and significant low power. For the QCA technology, making these high-density design means an increase in the complexity which in turn leads to growth in the number of faults. The defect model presented in this paper categorized into two types, which include single missing and additional cell considering for QCA fault. Proposed gates have been designed in the QCA and verified. The proposed Fredkin gate design has been compared with an existing design, and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli design in QCA which achieve some parameters such as cell complexity of 39, and the average fault tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the fault pattern look-up table.

1. RESEARCH
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Copyright © 2019 American Scientific Publishers
All rights reserved
Printed in the United States of America
SENSOR LETTERS
Vol. 17, 1–8, 2019
Analysis on Fault Mapping of Reversible Gates with
Extended Hardware Description Language for Quantum
Dot Cellular Automata Approach
Bandan Kumar Bhoi1
, Neeraj Kumar Misra2∗
, and Manoranjan Pradhan1
1
Department of Electronics Telecommunication Engineering, Veer Surendra Sai University of Technology, Burla 768018, India
2
Department of Electronics and Communication Engineering, Bharat Institute of Engineering and Technology, Hyderabad, India
(Received: xx Xxxx xxxx. Accepted: xx Xxxx xxxx)
Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer
scale with high integration density, and significant low power. For the QCA technology, making these
high-density design means an increase in the complexity which in turn leads to growth in the number
of faults. The defect model presented in this paper categorized into two types, which include single
missing and additional cell considering for QCA fault. Proposed gates have been designed in the
QCA and verified. The proposed Fredkin gate design has been compared with an existing design,
and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli
design in QCA which achieve some parameters such as cell complexity of 39, and the average fault
tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has
been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input
Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis
based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the
fault pattern look-up table.
Keywords: Quantum-Dot Cellular Automata, Verilog HDL, Fault-Tolerance, HDLQ, Fredkin Gate,
Toffoli Gate.
1. INTRODUCTION
One of the difficult tasks in the computational paradigm is
information loss. Reversible logic computation is meet this
responsibility by establishing a bijective mapping between
the inputs and outputs vectors [1]. Several efforts have
presented the idea for the use of QCA technology for
reversible circuit design [2].
A QCA is a nanometer scale based computing paradigm
such as the construction of circuits. Nowadays, increasing
the computing speed and miniaturization of the devices
become essential due to the advance of the nano-level
computing. However, the CMOS device has dissipated
energy due to logic bits computing. QCA computing is
based on the encoding of binary logic bits on the electron
charge from within the quantum dot cell. In quantum dot
cell no current flow and no external source are required to
flow the information [3, 4]. QCA defect has attracted con-
siderable attention in current research in nanoscale based
∗
Corresponding author; E-mail: neeraj.mishra3@gmail.com
testing, because of its high possibility of occurrence in
nano-scale [5]. As in nanoscale paradigm, the manufac-
turing of QCA device is yet to possible and hence, the
challenge from a high fault [6, 7]. In the manufacturing
fault in a QCA device may be categorized in the deposition
phase and synthesis phase. However, cell wrong position
fault introduced in the category of the deposition phase
has been found to be more common. These defects are
tackled by a testing engineer, which may occur in the
chemical synthesis phase. These fault tolerance usually
gain their reliability of QCA design. Testing is required
for this type of defects in QCA circuits. The defect char-
acterization and HDL modelling of basic QCA primitives
such as Majority voter (MV), inverter (INV), L-shaped
wire (LS), Fan-out wire (FO) and coplanar wire crossing
(CW) are available in the literature [8, 9]. The fault sets
corresponding to these QCA devices under missing and
additional cell deposition defects are illustrated in Table I.
The logic-level characterization of defects in devices and
circuits are performed in Refs. [10, 11]. In digital circuits,
Sensor Lett. 2019, Vol. 17, No. xx 1546-198X/2019/17/001/008 doi:10.1166/sl.2019.4078 1

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Analysis on Fault Mapping of Reversible Gates with Extended HDLQ Approach Bhoi et al.
Table I. Fault set of QCA devices [8].
Device Fault set
Majority voter (MV) F = S-a-B
F = Maj(A
, B, C
)
Inverter (INV) F = S-a-A
Straight wire No faults
L-shaped wire (LS) F = S-a-A
Fan-out wire (FO) F = S-a-A
Coplanar wire crossing (CW) FA = S-a-A
FB = S-a-A
’
AND, OR, NOT, NAND, NOR, Ex-OR and Ex-NOR logic
gates are primary devices to design complex circuits. With
QCA technology all these gates can be designed using the
basic QCA primitives. However, recently, researchers have
developed QCA layouts of Ex-OR gate [10] and the mul-
tiplexer circuit [11] without using these primitives. These
modified structures are highly efficient in cell count, area
and power consumption than its counterparts.
In this work, we have modelled the fault sets present
in these QCA structures. Therefore, reliability analysis
can be performed for QCA devices which are designed
using these circuits. Reversible logic is the future of
computing technology for low power design. Reversible
logic gates are building blocks of reversible circuits, and
parity-preserving reversible gates have the advantage of
the fault-tolerance capability. In parity-preserving gates,
the parity of input and output vectors are the same.
So any single fault can be easily detected by matching
the parity of these two vectors. Three parity-preserving
reversible logic gates are reported on QCA technology,
i.e., Fredkin gate [12, 13], Parity Preserving Reversible
Gate (PPRG) [14] and Reversible conservative QCA gate
(R-CQCA) [15]. In this work, we proposed a new QCA
layout of Fredkin gate and analyzed its fault-tolerant capa-
bility using the proposed defect model of the multiplexer.
We organized this paper as follows: the overview of
QCA includes of quantum-dot architecture are discussed in
Polarization P=+1 Polarization P=–1
Clock
0
Clock
1
Clock
2
Clock
3
Release
Hold
Switch
(a)
(b) (c)
Relax
Fig. 1. (a) Polarization of cell (B) four-phase clock (c) QCA basic gates AND, NAND, OR, NOR, INVERTERS.
Section 2, which is essential to reliability analysis under-
standing. Modelling of defects for QCA layout for three
input Ex-OR and 2:1 multiplexer is addressed in Section 3.
Fredkin and Toffoli gates fault-tolerant analysis based on
HDLQ and simulation results is presented in Section while
the design is validated on QCADesigner and Verilog cod-
ing based on HDLQ in Section 4. Finally, the conclusion
is drawn in Section 5.
2. OVERVIEW OF QCA
Before presenting the reliability analysis of QCA devices,
it is essential to show the basic features of QCA. This
section contributes fundamental of the quantum-dot archi-
tecture of QCA, basic gates, four-phase clock, QCA defect,
and QCA crossing.
2.1. The Quantum-Dot Architecture of QCA
QCA cells are the essential elements of QCA devices.
Each cell has four quantum dots arrangement with two
free electrons as shown in Figure 1(a). The sufficient elec-
tric field is required for tunnelling the junctions so that
two electrons can move between four quantum dots. The
null state is the first state in which barriers are minimized;
this reserve the electron to be set up on any dots. Posi-
tive polarization i.e., P =‘+1’ means barriers are raised.
Whereas negative polarization i.e., P =‘−1’ means bar-
rier increases in negative. Positive and negative polariza-
tion is responsible for binary ‘1’ and ‘0’ logic information
respectively. The polarization in the QCA cell is shown
in Figure 1(a). QCA wire allows binary information from
input to output through cells Columbia interactions.
2.2. QCA Clocking
In a conventional CMOS device, the clock has high and
low phases, but in QCA clock has four clock zones [16].
Each clock zone has four phases such as release, relax,
switch, and hold, as shown in Figure 1(b). In QCA designs,
the clock is not only flow data but also lower power
2 Sensor Letters 17, 1–8, 2019

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Bhoi et al. Analysis on Fault Mapping of Reversible Gates with Extended HDLQ Approach
(a) (b)
Fig. 2. Wire crossing method (a) multilayer approach (b) coplanar
approach.
dissipation. All the design in this work has been simulated
using Bistable approximation engine with clock high 9.8e-
22J, clock low of 3.8e-23J, and convergence tolerance of
0.001000.
2.3. QCA Basic Gates
The attraction and adopting of a QCA design is the major-
ity voter and inverter gates. The majority voter gate and
inverter consist of five, and two cells respectively. In the
majority voter gate, inputs are A, B, and C, and its logic
expression is Maj(A, B, C) = AB + BC + AC. The OR
and AND logic are synthesized by fixing the polariza-
tion of one of any three inputs to P = +1 and P = −1
respectively. The other primary QCA design is the inverter
where the input signal is flip due to the different polar-
ization that is coordinated between the adjacent corners
of cells [17, 18]. The NAND design is formed from the
AND followed by an inverter. Similarly NOR is formed by
NAND followed by an inverter. The QCA basic gates such
as AND, NAND, OR, NOR, INVERTERS are presented in
Figure 1(c).
Missing cell ‘C’
d
C Displaced cell
Two extra cell
Two extra cell
(a) (b) (c)
Fig. 3. QCA defect (a) extra cell (b) missing cell (c) displaced cell.
2.4. QCA Crossing
The design approaches for the crossing in QCA are mul-
tilayer and coplanar. The coplanar technique is gaining
popularity for robust design as well as the feasibility of
manufacturing. Figure 2(a) shows the multilayer design.
The crossing in coplanar is achieved by horizontal cells
of 90
orientations and vertical cells of 45
orientations as
depicted in Figure 2(b).
2.5. QCA Defect
The high device density of nanoscale is a high possibil-
ity of defect. In QCA, the defect has occurred during the
deposition process. The defect is taking into account for
the incorrect outcomes. The deposition phase defect is cat-
egorized as (1) Addition cell defect (shown in Fig. 3(a))
(2) Missing-cell defect (shown in Fig. 3(b)) (3) Cell mis-
alignment (shown in Fig. 3(c)).
2.6. Existing Reversible Logic Gates
The existing reversible logic gates such as Toffoli
gate (TG), and Feynman gate (FG), have attracted the
researcher’s attention during last four decades for the syn-
thesis and optimization of various kind of circuits [12].
3. MODELLING OF DEFECTS FOR QCA
LAYOUTS OF Ex-OR GATE AND
MULTIPLEXER
The Boolean expression for the output of three input
Ex-OR gate is defined as Y = A ⊕ B ⊕ C, for inputs
A, B, and C. Similarly for 2:1 Multiplexer output is
described as Y = S
A+SB, where A, B are primary inputs
and S is select input. The QCA layouts of three input
Ex-OR gate and 2:1 multiplexer circuits are shown in
Figures 4(a), and (c) respectively. The three input majority
voters and inverters are absent in this structure. There-
fore, in this work, we have modelled these two circuits
to include in the HDLQ library for the analysis of cell
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Analysis on Fault Mapping of Reversible Gates with Extended HDLQ Approach Bhoi et al.
Fig. 4. QCA layouts (a) three-input ex-or gate (b) cell positions of ex-or gate (c) 2:1 multiplexer (d) cell positions of 2:1 multiplexer.
deposition defects. The QCA layouts with cell positions
of Ex-OR and 2:1 multiplexer in Cartesian coordinates is
shown in Figures 4(b), and (d) respectively. Here input
and output cells are considered outside the layout dia-
gram. For finding out the faults in Ex-OR and multiplexer,
we have simulated these QCA layouts in QCADesigner
tool [20, 21] under all single missing and additional cell
defects. The simulation result of the outputs for defects is
given in Tables II and III.
In these tables, CM and CA indicate the position of
the missing cell and additional cell respectively. Here F
denotes functionality of the circuits after the correspond-
ing cell deposition defects, and Pmax shows the maximum
polarization of the output cell. From Table II, we found
that the faults for the three input Ex-Or gate are Maj(A
,
B
, C
), Maj(A, B, C), Maj(A
, B, C), Maj(A, B, C
),
Maj(A, B
, C
), Maj(A, B
, C), A
, A, B, and C.
A total of ten numbers of unique faults can be possible
through this gate. Similarly, faults found from Table III are
A, B (S+A), Maj(S, A, B), (A+SB), B, Maj(S, A
, B
),
(S
A+B), A (S
+B). Therefore a total of eight numbers
of unique faults can be possible in 2:1 multiplexer due
to cell deposition defects. In HDLQ library [9] all basic
QCA devices such as MV, INV, FO, LS, and CW are
defined using hardware description language having fault
injection capability. In this work, we modelled the cell
Table II. Analysis of cell defects in three input Ex-OR gate.
CM F Pmax CA F Pmax
1,4 Maj(A
,B
,C
) 0.88 1,3 A⊕B⊕C 0.88
2,4 Maj(A
,B
,C
) 0.88 1,5 A⊕B⊕C 0.88
3,3 Maj(A,B,C) 0.95 2,3 A 0.88
3,4 Maj(A
,B,C) 0.87 2,5 A 0.88
3,5 Maj(A,B,C) 0.95 3,1 Maj(A
,B,C) 0.88
4,1 A
0.88 3,2 C 0.88
4,2 A
0.88 3,6 B 0.88
4,3 Maj(A,B,C
) 0.93 3,7 Maj(A
,B,C) 0.88
4,4 Maj(A,B
,C
) 0.94 5,1 A⊕B⊕C 0.89
4,5 Maj(A,B
,C) 0.93 5,2 A⊕B⊕C 0.89
4,6 A
0.88 5,3 Maj(A
,B
,C
) 0.98
4,7 A
0.88 5,5 Maj(A
,B
,C
) 0.98
5,4 – – 5.6 A⊕B⊕C 0.89
5,7 A⊕B⊕C 0.89
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Bhoi et al. Analysis on Fault Mapping of Reversible Gates with Extended HDLQ Approach
Table III. Analysis of cell defects in 2:1 multiplexer.
CM F Pmax CA F Pmax
1,3 A 0.94 1,2 S
A+SB 0.95
2,2 B(S+A) 0.94 1,4 S
A+SB 0.95
2,3 Maj(S,A,B) 0.94 3,1 S
A+SB 0.95
2,4 A+SB 0.94 3,3 Maj(S,A,B) 0.95
3,2 B 0.95 3,5 S
A+SB 0.95
3,4 A 0.94 5,1 A+SB 0.95
4,1 A 0.87 5,2 S
A+B 0.98
4,2 A 0.92 5,4 A(S
+B) 0.97
4,3 Maj(S,A
,B
) 0.95 5,5 B(S+A) 0.94
4,4 B 0.92
4,5 B 0.94
5,3 – –
deposition defects of the QCA layout of three input Ex-
Or gate and 2:1 multiplexer circuit. The Verilog HDL [18]
pseudo codes for the HDLQ model of proposed circuits
are illustrated below.
Pseudocode: module Ex-Or gate;
input: A, B, C, fault9, fault8, fault7, fault6, fault5, fault4,
fault3, fault2, fault1, fault0;
output: out;
wire: w0, w1, w2, w3, w4, w5, w6, w7, w8, w9;
assign w0 = A∧
B∧
C;
assign w1 = (fault0)? (A
B
+A
C
+B
C
): w0;
assign w2 = (fault1)? (AB+BC+AC): w1;
assign w3 = (fault2)? (A
B+BC+A
C): w2;
assign w4 = (fault3)? (AB+BC
+AC
): w3;
(a) (b)
Fig. 5. Fredkin gate (a) QCA layout (b) simulation result.
assign w5 = (fault4)? (AB
+B
C
+AC
): w4;
assign w6 = (fault5)? (AB
+B
C+AC): w5;
assign w7 = (fault6)? (A
): w6;
assign w8 = (fault7)? (A): w7;
assign w9 = (fault8)? (B): w8;
assign out = (fault9)? (C): w9;
endmodule
Pseudocode: module Multiplexer 2:1
input: S, A, B, fault7, fault6, fault5, fault4, fault3, fault2,
fault1, fault0;
output: out;
wire: w0, w1, w2, w3, w4, w5, w6, w7;
assign w0 = S
A+SB;
assign w1 = (fault0)? (A): w0;
assign w2 = (fault1)? (B(S+A)): w1;
assign w3 = (fault2)? (SA+SB+AB): w2;
assign w4 = (fault3)? (A+SB): w3;
assign w5 = (fault4)? (B): w4;
assign w6 = (fault5)? (SA
+SB
+A
B
): w5;
assign w7 = (fault6)? (S
A+B): w6;
assign out = (fault7)? (A(S
+B)): w7;
endmodule
4. RELIABILITY ANALYSIS OF QCA CIRCUIT
In this section by using proposed models of multi-
plexer and Ex-OR gate, the fault-tolerance analysis is
performed for the reversible Fredkin and Toffoli gate
respectively.
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Analysis on Fault Mapping of Reversible Gates with Extended HDLQ Approach Bhoi et al.
4.1. Fredkin Gate
Here we proposed a new QCA layout of the reversible
Fredkin gate, which is shown in Figure 5(a). Here inputs
to output mapping are defined as P = A, Q = A
B + AC,
and R = AB + A
C. This proposed QCA layout is simu-
lated in QCADesigner tool, and the simulation result is
shown in Figure 5(b). Here Q and R outputs are generated
after a delay of 1 clock. The QCA metrics are presented
in Table IV. It shows a 43% improvement in cell count
and 70% improvement in the area. This QCA layout has
no three input majority gates and inverters. The HDLQ
model of the proposed reversible Fredkin gate is shown
in Figure 6, which is derived from its QCA layout. This
model contains the whole 15 numbers of QCA elements
(LS = 6, CW = 3, FO = 4, proposed multiplexer = 2). Here
we are not considering the straight wires because they have
no cell deposition defects according to Table I. Therefore
a total of 32 numbers of faults (LS = 6, CW = 6, FO = 4,
Proposed multiplexer = 16) can be possible in this model
according to fault sets defined in Tables I and III. So by
considering these 32 numbers of probable faults along with
regular inputs A, B, and C, we have done the reliability
analysis of the proposed Fredkin gate. We simulated this
HDLQ model of Fredkin gate using Verilog HDL simula-
tor, where for each single fault inputs we found the cor-
responding outputs. Out of 32 numbers of fault patterns,
27 patterns are unique. These are listed in 27 numbers of
columns in Table V. Here ai indicates the binary equiva-
lent of decimal number i. It shows either input vectors or
output vectors. For example, if the vector of entry is a4,
then A, B, C represents 1, 0, 0 respectively. In this table
from each row total number of expected output, patterns
are counted. Here in first row 19 numbers of a0 correct pat-
terns are formed. Therefore, out of 27 numbers of defects,
19 numbers are correct. It means that there are 19 numbers
of correct outputs in the presence of errors. Therefore, for
input vector a0, this Fredkin gate has 70% (= 19/27 ×100)
fault tolerance capability. Similarly, for other input vec-
tors, this capability is shown in Table V. Here the
average fault tolerance of all the eight input vectors
is 58%.
Table IV. Comparison of parity preserving reversible gates.
Input pins
availability for
Reversible Area external wire
gates Cell count (m2
) Delay connection
Fredkin [11] 191 0.37 1 Yes
PPRG [12] 171 0.19 1 Yes
R-CQCA [13] 177 0.24 1 Yes
Fredkin [19] 73 NS* 0.75 No
Proposed Fredkin 109 0.11 1 Yes
Note: NS* = not specified.
LS2
CW2 LS3
CW1
FO2
A
LS4 LS5
CW3
FO3
C
P
Proposed
Multiplexer
FO4
Proposed
Multiplexer
LS6
LS1
B
Q
R
FO1
Fig. 6. HDLQ model of proposed QCA layout of Fredkin gate.
4.2. Toffoli Gate
The Toffoli gate can be expressed as P = A, Q = B, R =
AB ⊕ C: where A, B, C are inputs and P, Q, R are the
outputs [17, 18]. It is a universal category of the reversible
gate and can be utilized in the design of AND, OR and
signal duplication. The QCA layout and simulation result
is shown in Figure 7. The proposed Toffoli gate QCA
Table V. Fault-tolerance analysis of Fredkin gate.
IV EV 1 2 3 4 5 6 7 8 9 10
a0 a0 a1 a2 a0 a2 a0 a1 a0 a0 a0 a4
a1 a1 a0 a1 a2 a3 a0 a1 a3 a1 a1 a5
a2 a2 a3 a2 a1 a2 a3 a3 a0 a2 a2 a6
a3 a3 a2 a1 a3 a3 a3 a3 a3 a3 a3 a7
a4 a4 a6 a4 a4 a4 a4 a4 a4 a6 a5 a0
a5 a6 a4 a6 a5 a6 a7 a4 a4 a4 a7 a2
a6 a5 a7 a5 a6 a5 a4 a5 a7 a7 a4 a1
a7 a7 a5 a7 a7 a7 a7 a5 a7 a5 a6 a3
11 12 13 14 15 16 17 18 19 20 21 22
a2 a0 a0 a0 a0 a0 a2 a0 a0 a0 a0 a0
a3 a1 a1 a1 a1 a3 a1 a3 a1 a1 a0 a0
a0 a2 a0 a0 a2 a0 a0 a2 a2 a2 a2 a2
a1 a3 a3 a3 a3 a3 a1 a1 a1 a3 a3 a3
a4 a4 a4 a4 a4 a4 a6 a4 a4 a4 a4 a4
a6 a4 a6 a6 a6 a6 a6 a6 a4 a7 a6 a7
a5 a7 a5 a7 a7 a5 a7 a5 a5 a4 a5 a5
a7 a7 a5 a7 a5 a7 a5 a7 a7 a7 a6 a7
23 24 25 26 27 FT(%)
a0 a0 a1 a0 a0 70
a1 a0 a0 a1 a1 51
a2 a3 a2 a3 a2 51
a3 a3 a2 a2 a2 63
a4 a4 a5 a4 a4 77
a7 a6 a7 a6 a6 48
a5 a5 a5 a5 a4 52
a6 a7 a6 a7 a7 55
Notes: Avg.—58%, FT = Fault tolerance, IV = input vectors, EV = expected
vectors.
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Bhoi et al. Analysis on Fault Mapping of Reversible Gates with Extended HDLQ Approach
Fig. 7. Toffoli gate (a) QCA layout (b) simulation result.
layout requires only 39 QCA cells with an overall area
of 0.07 m2
. From the simulation result, it is shown that
there is a maximum delay of 0.75 clocks at R output.
Comparison with existing QCA Toffoli gate is provided
CW FO
LS MV
Proposed Ex-OR
–1
Q
A
C
R
B
–1
FO LS
CW
MV
Fan-out
L-Shape
wire
Crosswire
Majority
voter
Fig. 8. HDLQ model of Toffoli gate.
in Table VI. Here we performed the fault-tolerant capabil-
ity of this gate using our proposed cell deposition defect
model of the Ex-OR gate. The HDLQ model of the Toffoli
gate is shown in Figure 8. This model contains a total of
5 QCA elements (CW = 1, FO = 1, LS = 1, MV = 1, Pro-
posed Ex-OR = 1). Therefore 16 numbers of faults (CW =
2, FO = 1, LS = 1, MV = 2, Proposed Ex-OR = 10) are
possible in this logic gate. After simulating it in Verilog
HDL simulator, we found 13 numbers of unique fault pat-
terns, which is illustrated in Table VII. Here it is shown
that the proposed Toffoli QCA layout has overall 53.5%
fault-tolerance capability in the presence of cell deposition
defects. In this type of HDL approach, we can find the
reliability or fault-tolerance capability of any QCA circuits
under missing and additional cell defects, so that circuit
designer can select the more reliable circuits by seeing the
percentage of reliability.
Table VI. Comparison of QCA layout of Toffoli gates.
Input pins
Toffoli availability for
gate Cell count Delay external wire connection
[20] 59 0.75 Yes
[21] 45 0.75 No
Proposed 39 0.75 Yes
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Analysis on Fault Mapping of Reversible Gates with Extended HDLQ Approach Bhoi et al.
Table VII. Fault-tolerance analysis of Toffoli gate.
IV EV 1 2 3 4 5 6 7
a0 a0 a0 a2 a2 a0 a0 a0 a0
a1 a1 a1 a3 a3 a1 a1 a1 a0
a2 a2 a3 a2 a0 a2 a2 a2 a2
a3 a3 a2 a3 a1 a3 a3 a3 a2
a4 a4 a4 a4 a6 a5 a5 a4 a4
a5 a5 a5 a5 a7 a4 a4 a5 a4
a6 a7 a6 a4 a5 a7 a7 a6 a6
a7 a6q a7 a5 a4 a6 a6 a6 a6
8 9 10 11 12 13 FT (%)
a0 a1 a0 a1 a0 a0 61
a1 a0 a0 a1 a0 a1 46
a2 a3 a2 a3 a2 a2 69
a3 a2 a2 a3 a2 a3 53
a4 a5 a4 a5 a4 a4 61
a5 a4 a4 a5 a4 a5 46
a7 a7 a7 a6 a7 a6 46
a7 a7 a6 a6 a7 a7 46
Notes: IV = Input vectors, Avg. 53.5%, EV = Expected vectors.
5. CONCLUSIONS
In this paper, fault-tolerance of the three input Ex-OR
and 2:1 multiplexer was examined under single missing
cell and additional cell missing. As can be seen from the
defect, the polarization of signal variations with the miss-
ing cells was studied. Average fault tolerant results show
the effectiveness of the proposed Fredkin and Toffoli gate
design, i.e., analysis using HDLQ based. Here the func-
tional verification and primitive’s results of Fredkin and
Toffoli gate have been proved to be effective for the QCA
design optimization problem. The brief comparative study
shows that the new fault-tolerant approach not only uti-
lized minimum test vectors and maximum fault tolerant
coverage but also better QCA primitives as compared to
the previous design approach, thereby checking the prac-
tical reliability of the introduced designs. However, the
reliability model for fault tolerance of QCA designs offers
a good framework to be used for inclusion of the fault
tolerance area. For future scope, the proposed models of
testing and approaches can be utilized for high-complexity
designs.
FIRST TIME USE OF ABBREVIATIONS
Hardware Description Language for QCA (HDLQ), Quan-
tum dot cellular Automata (QCA), Majority voter (MV),
Inverter (INV), L-shaped wire (LS), Fan-out wire (FO),
Coplanar wire crossing (CW), etc.
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8 Sensor Letters 17, 1–8, 2019