This document contains 50 titles of VLSI projects presented at the IEEE conference in 2014. The projects cover a range of topics related to digital circuit design including adder circuits, multiplier designs, DSP applications, cryptography, and neural networks. Each project listing includes the title, year presented, and design tools used such as Quartus, Xilinx, Tanner, and Simulink.

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VLSI (IEEE 2014) TITLES FOR
BE, B.TECH
S.N
o Project Title Year Tool
1 Area–Delay–Power Efficient Carry-Select Adder IEEE 2014 Quartus
2 Shift Register Design Using Two Bit Flip-Flop IEEE 2014 Quartus
3
Input Vector Monitoring Concurrent BIST Architecture Using SRAM
Cells IEEE 2014 Quartus
4 Design and Analysis of Approximate Compressors for Multiplication IEEE 2014 Quartus/Xilinx
5 High Speed Vedic Multiplier Designs-A Review IEEE 2014 Quartus/Xilinx
6 Efficient Integer DCT Architectures for HEVC IEEE 2014 Quartus/Xilinx
7 SDR - Implementation Of Low Frequency Trans-Receiver On FPGA IEEE 2014 Simulink-XSG
8
Design of Dedicated Reversible Quantum Circuitry for Square
Computation IEEE 2014 Quartus/Xilinx
9 ASIC Design of Reversible Multiplier Circuit IEEE 2014 Quartus/Xilinx
10
High throughput pipelined 2D Discrete cosine transform for video
compression IEEE 2014 Quartus
11
Multiplication Acceleration Through Quarter Precision Wallace Tree
Multiplier IEEE 2014 Quartus/Xilinx
12 Power Evaluation of Sobel Filter on Xilinx Platform IEEE 2014 Simulink-XSG
13
FPGA Based Implementation & Power Analysis of Parameterized
Walsh Sequences IEEE 2014 Simulink-XSG
14 A 1-GHz Direct Digital Frequency Synthesizer in an FPGA IEEE 2014 Simulink-XSG
15 Realization of 2:4 reversible decoder and its applications IEEE 2014 Tanner
16
On The Systematic Creation of Faithfully Rounded Truncated
Multipliers and Arrays IEEE 2014 Quartus/Xilinx
17
Low-Complexity Low-Latency Architecture for Matching of Data
EncodedWith Hard Systematic Error-Correcting Codes IEEE 2014 Quartus/Xilinx
18 Radix-2r Arithmetic for Multiplication by a Constant IEEE 2014 Quartus/Xilinx
19 Low power Square and Cube Architectures Using Vedic Sutras IEEE 2014 Quartus/Xilinx
20
A Novel Parallel Multiplier for 2’s Complement Numbers Using
Booth’s Recoding Algorithm IEEE 2014 Quartus/Xilinx
21 4-2 Compressor Design with New XOR-XNOR Module IEEE 2014 Tanner
22 A New Design of Low Power High Speed Hybrid CMOS Full Adder IEEE 2014 Tanner

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23 Improved design of high-frequency sequential decimal multipliers IEEE 2014 Quartus/Xilinx
24
A Decimal / Binary Multi-operand Adder using a Fast Binary to
Decimal Converter IEEE 2014 Quartus/Xilinx
25 FPGA based Partial Reconfigurable FIR Filter Design IEEE 2014 Quartus/Xilinx
26
Improved matrix multiplier design for high-speed digital signal
processing applications IEEE 2014 Quartus/Xilinx
27
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR
Interpolation Filter for Multistandard DUC IEEE 2014 Quartus/Xilinx
28
Power- and Area-Efficient Approximate WallaceTree Multiplier for
Error-Resilient Systems IEEE 2014 Quartus/Xilinx
29 HDL Based Implementation of NxN Bit-Serial Multiplier IEEE 2014 Quartus/Xilinx
30
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With
Low Adaptation-Delay IEEE 2014 Quartus/Xilinx
31
Single-Bit Pseudo parallel Processing Low-Oversampling Delta–Sigma
Modulator Suitable for SDR Wireless Transmitters IEEE 2014 Quartus/Xilinx
32
Software/Hardware ParallelLong-Period Random Number Generation
Framework Based on the WELL Method IEEE 2014 Quartus/Xilinx
33 Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating IEEE 2014 Quartus/Xilinx
34
Gate Mapping Automation for Asynchronous NULL Convention Logic
Circuits IEEE 2014 Quartus/Xilinx
35 Mapping Loop Structures onto Parametrized Hardware Pipelines IEEE 2014 Quartus/Xilinx
36 Multifunction Residue Architectures for Cryptography IEEE 2014 Quartus/Xilinx
37
Logical Computation on Stochastic Bit Streams with Linear Finite-State
Machines IEEE 2014 Quartus/Xilinx
38 Recursive Approach to the Design of a Parallel Self-Timed Adder IEEE 2014 Quartus/Xilinx
39 Two Phase Clocking Subthreshold Adiabatic Logic IEEE 2014 Tanner
40 2-Bit Magnitude Comparator using GDI Technique IEEE 2014 Tanner
41
Implementation Of BarrelShifter using Diode free Adiabatic Logic
(DFAL) IEEE 2014 Tanner
42
Implementation of Optimized High Performance 4x4 Multiplier using
Ancient Vedic Sutra in 45 nm Technology IEEE 2014 Tanner
43
Comparative Analysis of Carry Select Adder using 8T and lOT Full
Adder Cells IEEE 2014 Tanner
44
Design of Low Power Split Path Data Driven Dynamic Ripple Carry
Adders IEEE 2014 Tanner
45
Improved 8-Point Approximate DCT for Image and Video Compression
Requiring Only 14 Additions IEEE 2014
Quartus/Xilinx
46
Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet
Filter Banks With Low Adder-Count IEEE 2014 Quartus/Xilinx
47
Efficient VLSI Implementation of Neural Networks With Hyperbolic
Tangent Activation Function IEEE 2014 Quartus/Xilinx

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48
Design and Simulation of Software Defined Radio Using MATLAB
SIMULINK IEEE 2014 Simulink-XSG
49 FPGA Implementation of Stream Cipher Using Toeplitz Hash Function IEEE 2014 Simulink-XSG
50
Implementation of Error Correcting methods for asynchronous
communication and Modified Completion Detector with reduced area
overhead IEEE 2014
Simulink-
XSG