Verifikation - Metoder og Libraries

SynthWorks
Presented by
Martin Rønne, MR Logic
Slides prepared by
Jim Lewis, jim@SynthWorks.com
SynthWorks
Copyright © 2016 SynthWorks Design Inc.
Copyright © 2017 by SynthWorks Design Inc.
Reproduction of this entire document in whole for individual usage is permitted.
All other rights reserved.
In particular, without express written permission of SynthWorks Design Inc,
You may not alter, transform, or build upon this work,
You may not use any material from this guide in a group presentation,
tutorial, training, or classroom
You must include this page in any printed copy of this document.
This material is derived from SynthWorks' Advanced VHDL Testbenches and Verification class
This material is updated from time to time and the latest copy of this is available at
http://www.SynthWorks.com/papers
Contact Information
Jim Lewis, President
SynthWorks Design Inc
11898 SW 128th Avenue
Tigard, Oregon 97223
503-590-4787
jim@SynthWorks.com
www.SynthWorks.com

SynthWorks
SynthWorks

SynthWorks
UartTbTxProc : process
begin
. . .
UartSend(UartTxRec, X"4A") ;
UartSend(UartTxRec, X"4B") ;
. . .
SynthWorks

SynthWorks
architecture UartTx1 of TestCtrl is
. . .
begin
ControlProc : process
begin
. . .
WaitForBarrier(TestDone, 5 ms) ;
ReportAlerts ;
std.env.stop;
end process ;
CpuTestProc : process
begin
wait until nReset = '1' ;
CpuWrite(. . .) ;
Toggle(CpuRdy);
. . .
WaitForBarrier(TestDone) ;
end process ;
UartTbTxProc : process
begin
WaitForToggle(CpuRdy);
UartSend(. . .) ;
. . .
WaitForBarrier(TestDone) ;
end process ;
. . .
SynthWorks
UartSend(...)
type CpuRecType is record
Rdy : std_logic_max ;
Ack : std_logic_max ;
Data : unsigned_max(7 downto 0) ;
ErrMode : unsigned_max(2 downto 0) ;
end record ;

SynthWorks
procedure UartSend (
. . .
) is
begin
-- Copy Transaction to Record
UartTxRec.Data <= . . . ;
UartTxRec.ErrMode <= . . . ;
-- Handshake with UartTx
RequestTransaction(. . .);
-- Copy results from Record
. . .
end UartSend ;
entity UartTx is
port (. . .) ;
end UartTx ;
architecture Model of UartTx is
. . .
begin
. . .
UartTxFunction : process
-- declarations not shown
begin
-- Handshake with UartSend
WaitForTransaction(. . .);
-- Create UART waveforms
. . .
end process ;
end Model ;
SynthWorks

SynthWorks
Data1 := RV.RandInt(Min => 0, Max => 15) ;
Data2 := RV.RandInt(0, 15, (5,11) ) ; -- except 5 & 11
Data3 := RV.RandInt( (1,2,3,5,7,11) ) ;
Data4 := RV.RandInt( (1,2,3,5,7,11), (5,11) ) ;
. . . -- ((val1, wt1), (val2, wt2), ...)
Data6 := RV.DistValInt( ((1,7), (3,2), (5, 1)) ) ;
Data5 := RV.DistInt ( (7, 2, 1) ) ;
SynthWorks
variable RV : RandomPType ;
. . .
StimGen: while TestActive loop
case RV.DistInt( (70, 10, 10, 5, 5) ) is
when 0 => -- Nominal case 70%
Operation := UARTTB_NO_ERROR ;
Data := RV.RandSlv(0, 255, Data'length) ;
when 1 => -- Parity Error 10%
Operation := UARTTB_PARITY_ERROR ;
Data := RV.RandSlv(0, 255, Data'length) ;
when . . . -- (2, 3, and 4)
end case ;
UartRxScoreboard.Push( (Data, Operation) ) ;
UartSend(UartTxRec, Data, Operation) ;
. . .

SynthWorks
SynthWorks
function GenBin ( . . . ) return CovBinType ;
type CovPType is protected
procedure AddBins ( CovBin : CovBinType ) ;
procedure AddCross( Bin1, Bin2, ... : CovBinType ) ;
procedure ICover ( val : integer ) ;
procedure ICover ( val : integer_vector ) ;
impure function IsCovered return boolean ;
procedure WriteBin ;
procedure WriteCovHoles ;
procedure ReadCovDb ( FileName : string ) ;
procedure WriteCovDb ( FileName : string; ... ) ;
. . .
end protected CovPType ;

SynthWorks
SynthWorks
architecture Test3 of tb is
shared variable ACov : CovPType ;
begin
CollectCov : process
variable RV : RandomPType ; -- randomization object
variable Src1, Src2 : integer ;
begin
ACov.SetName("TbAlu_ConstrainedRandom") ;
ACov.AddCross( GenBin(0,7), GenBin(0,7) );
loop
Src1 := RV.RandInt(0, 7) ;
Src2 := RV.RandInt(0, 7) ;
DoAluOp(TRec, Src1, Src2) ;
ACov.ICover( ( Src1, Src2 ) ) ;
exit when ACov.IsCovered ;
end loop ;
ACov.WriteBin ;
ReportAlerts ;
std.env.stop ;
end process ;

SynthWorks
SynthWorks
TestProc : process
begin
for i in 0 to 7 loop
for j in 0 to 7 loop
if i /= j then
-- non-diagonal
ACov.AddCross(2, GenBin(i), GenBin(j)) ;
else
-- diagonal
ACov.AddCross(4, GenBin(i), GenBin(j)) ;
end if ;
...

SynthWorks
architecture Test3 of tb is
shared variable ACov : CovPType ; -- Cov Object
begin
CollectCov : process
variable Src1, Src2 : integer ;
begin
SetAlertLogName("IntelligentCov1") ;
loop
(Src1, Src2) := ACov.RandCovPoint ;
ACov.ICover( (Src1, Src2) ) ;
exit when ACov.IsCovered ;
end loop ;
ACov.WriteBin ;
ReportAlerts ;
std.env.stop ;
end process ;
SynthWorks
while not ACov.IsCovered loop
(Src1, Src2) := ACov.RandCovPoint ;
if Src1 /= Src2 then
else
-- Do previous and following diagional
DoAluOp(TRec, (Src1-1) mod 8, (Src1-1) mod 8) ;
DoAluOp(TRec, Src1, Src1 ) ;
DoAluOp(TRec, (Src1+1) mod 8, (Src1+1) mod 8) ;
-- Can either record all or select items
end if ;
end loop ;

SynthWorks
StimCov.AddBins( 70, NORMAL ) ;
StimCov.AddBins( 10, PARITY ) ;
StimCov.AddBins( . . . ) ;
. . .
loop
iOperation := StimCov.RandCovPoint ;
case iOperation is
when 1 => . . . -- Nominal
when 3 => . . . -- Parity
. . .
end case ;
UartRxScoreboard.Push( (Data, Operation) ) ;
UartSend(UartTxRec, Data, Operation) ;
StimCov.Icover(iOperation) ;
exit when StimCov.IsCovered ;
SynthWorks

SynthWorks
SetAlertLogName("Test_Uart_Rx1") ;
signal CpuID : AlertLogIDType ;
signal DataErrID : AlertLogIDType ;
. . .
CpuID <= GetAlertLogID("Cpu_1") ;
DataErrID <= GetAlertLogID("Cpu_1 Data Error", CpuID);
SynthWorks
Alert (CpuID, "Illegal State") ;
AlertIfNot(CpuID, ReadValid, "Read Failed", FAILURE) ;
AlertIfDiff(CpuID, "./File1.txt", "./File2.txt") ;
%% Alert ERROR In Cpu_1, Illegal State at 5000 ns

SynthWorks
Log("Test 1 Starting") ;
Log(CpuID, "Entered Hold State", DEBUG) ;
%% Log ALWAYS Test 1 Starting at 1770 ns
%% Log DEBUG In Cpu_1, Entered Hold State at 31000 ns
SynthWorks
AffirmIf(CpuID, Data = Expect, "Data: " & to_string(Data),
" /= Expected: " & to_string(Expect)) ;
%% Alert ERROR In Cpu_1, Data: 5 /= Expected: 6 at ... ns
%% Log PASSED In Cpu_1, Data: 5 at 2150 ns

SynthWorks
ReportAlerts ;
%% DONE FAILED Test_UartRx_1 Total Error(s) = 10 Failures: 0
Errors: 10 Warnings: 0 at 100100100 ns
%% DONE FAILED Test_UartRx_1 Total Error(s) = 10 Failures: 0
Errors: 10 Warnings: 0 at 100100100 ns
%% Default Failures: 0 Errors: 2 Warnings: 0
%% OSVVM Failures: 0 Errors: 0 Warnings: 0
%% Cpu_1 Failures: 0 Errors: 5 Warnings: 0
%% Cpu_1 Data Error Failures: 0 Errors: 4 Warnings: 0
%% Cpu_1 Protocol Error Failures: 0 Errors: 1 Warnings: 0
%% UartTx_1 Failures: 0 Errors: 0 Warnings: 0
%% DONE PASSED Test_UartRx_1 at 100100100 ns
SynthWorks
SetAlertEnable(WARNING, FALSE) ; -- For all IDs
SetAlertEnable(CpuID, WARNING, FALSE) ; -- For CpuID
SetAlertStopCount(ERROR, 20) ; -- For all IDs
SetAlertStopCount(CpuID, ERROR, 20) ; -- CpuID
ClearAlerts ;
SetLogEnable(PASSED, TRUE) ; -- For all models
SetLogEnable(CpuID, DEBUG, TRUE) ; -- For CpuID

SynthWorks
TranscriptOpen("./results/test1.txt") ;
TranscriptClose ;
SetTranscriptMirror(TRUE) ; -- TRUE is the default
print("A String") ; -- Direct to file, newline added
print("") ; -- Print a blank line
writeline( WriteBuf ) ; -- Using textio
SynthWorks

SynthWorks
GenerateProc : process
begin
SB.Push(X"10") ;
UartSend(TRec, X"10") ;
SB.Push(X"11") ;
SB.Push(X"12") ;
. . .
Done <= TRUE ;
wait ;
end process GenerateProc ;
ReceiveProc : process
variable ExpectD, RcvD :
std_logic_vector(7 downto 0);
begin
SetAlertLogName("SB_UART");
while not Done loop
UartGet(RRec, RcvD) ;
SB.Check(RcvD) ;
end loop ;
ReportAlerts ;
end process ReceiveProc ;
shared variable SB : ScoreboardPType ;
SynthWorks
type MemoryPType is protected
procedure MemInit ( AddrWidth, DataWidth : in integer ) ;
procedure MemWrite ( Addr, Data : in std_logic_vector ) ;
impure function MemRead ( Addr : in std_logic_vector )
return std_logic_vector ;
procedure FileReadH (FileName : string) ;
procedure FileWriteH (FileName : string) ;
. . .
end protected MemoryPType ;

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