The document provides an overview of the Motorola DSP563xx family of processors. It describes the core architecture which includes a data ALU, MAC unit, address generation unit, program control unit, and on-chip memory. It also discusses the internal buses and on-chip peripherals. The DSP563xx family is used in applications such as wireless infrastructure and modem banks. Members of the family have different memory and peripheral configurations while sharing a standardized DSP56300 core.

1. An overview of Motorola
DSP563xx Processors
By.
Dr. Sudhir N. Shelke
Principal , Guru Nanak Institute of
Technology, Nagpur.
Dr.Sudhir N Shelke 1

2. Introduction
• The Motorola DSP56300 family programmable DSPs are
deployed in a number of applications such as wireless
infrastructure, internet telephony, base transceiver station,
network interface cards, base station controllers and high
speed modem banks.
• DSP 56300 family of processors has a number of processors
such as DSP56301, DSP56305, DSP56307, DSP56309 and
DSP56311 with different mix of on-chip memory, peripherals
and coprocessors.
• These processors are built around a standardized DSP56300
core. The DSP56300 core provides up to twice the
performance of Motorola’s popular DSP56000 core family,
while retaining code compatibility.
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3. Block Diagram of Motorola 563xx
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4. Architecture consists of following units:
o Data ALU
o MAC
o Address Generation Unit
o Program Control Unit
o On chip Memory
o Internal Buses
o On chip Peripherals
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5. Data ALU
o The Data ALU performs all the arithmetic and logical
operations on data operands in the DSP56300 core.
o It Consists of :
 Fully pipelined 24 X 24-bit parallel Multiplier-
Accumulator (MAC) unit.
 56-bit barrel shifter .
 four 24-bit general-purpose registers: X1, X0, Y1 and Y0,
these registers can be used either individually or combined
into two 48-bit registers called X and Y register
respectively.
 Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that
are concatenated into two general purpose 56-bit
accumulators (A and B)
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6. Data ALU cont..
o The CPU can be made to operate either in 24-bit or 16-bit
mode under software control .
o The Data ALU registers can be read or written over the X data
bus (XDB) and the Y data bus (YDB) as 16- or 32-bit operands.
o The source operands for the Data ALU, which can be 16, 32, or
40 bits, always originate from Data ALU registers .
o The results of all Data ALU operations are stored in an
accumulator.
o All the Data ALU operations are performed in two clock cycles
in pipeline fashion so that a new instruction can be initiated in
every clock .
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7. MAC unit
• The MAC unit comprises the main arithmetic processing unit
of the DSP56300 core and performs all of the calculations on
data operands.
• For arithmetic instructions, the unit accepts as many as three
input operands and outputs one 56-bit result of the following
form,
• Extension : Most Significant Product : Least Significant
Product (EXT:MSP:LSP).
• The multiplier executes 24-bit x 24-bit, parallel fractional
multiplies, between twos-complement signed, unsigned, or
mixed operands. The 48-bit product is right-justified into 56
bits and added to the 56-bit contents of either the A or B
accumulator.
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8. MAC unit Cont..
• The 56-bit sum is stored back in the same
accumulator.
• The input to the multiplier can come only from the X
and Y registers. The output of the multiplier can be
added or subtracted to either of the accumulators.
The outputs of the accumulators can be moved to
either X or Y areas.
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9. AGU
o The AGU performs the effective address calculations using
integer arithmetic necessary to address data operands in
memory and contains the registers that generate the
addresses.
o It has several features which are similar to that of the data
address generation logic (DAGEN) block of TI TMS320C54X. It
has two address arithmetic logic unit (Address ALU). This is
similar to ARAU0 and ARAU1 of 54X.
o The AGU operates in parallel with the main data ALU and all
effective address calculations are done without using the data
ALU. It has eight registers 24-bit R0-R7 which are used for
either specifying the indirect address or hold the operand for
instruction. Their operation is similar to the 16-bit ARs AR0-
AR7 of 54X.
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10. It implements four types of arithmetic:
o Linear
o Modulo
o Multiple wrap-around modulo
o Reverse-carry
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11. It implements four
types of arithmetic:
o Linear
o Modulo
o Multiple
wrap-around
modulo
o Reverse-carry
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12. AGU Cont..
• The AGU is divided into
halves, each with its own
Address Arithmetic Logic
Unit (Address ALU).
• Each Address ALU has four
sets of register triplets, and
each register triplet is
composed of an address
register Rn, an offset register
Nn and a modifier
register Mn .
The eight triplets are as
follows:
1.Low Address ALU register triplets
R0:N0:M0
R1:N1:M1
R2:N2:M2
R3:N3:M3
2.High Address ALU register triplets
R4:N4:M4
R5:N5:M5
R6:N6:M6
R7:N7:M7
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13. • The two address ALUs are identical. Each contains a 24-bit full
adder (called an offset adder) which can perform the
following additions/subtractions on an address register:
Plus one
Minus one
Plus the contents of the respective offset register N
Minus the contents of the respective offset register N
 A second full adder (called a modulo adder) adds the summed result of the
first full adder to a modulo value that is stored in its respective modifier
register.
 A third full adder (called a reverse-carry adder) is also provided. The offset
adder and the reverse-carry adder are in parallel and share common inputs.
 Each address ALU can update one address register from its respective address
register file during one instruction cycle.
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14. The two Address ALUs can generate up to two addresses
every instruction cycle:
o One for the PAB, or
o One for the XAB, or
o One for the YAB, or
o One for the XAB and one for the YAB
The AGU can directly address 16,777,216 locations on
each of the XAB, YAB, and PAB.
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15. Program Control Unit
• The Program Control Unit (PCU) of the DSP56300 family core coordinates
execution of program instructions and instructions for processing
interrupts and exceptions.
The PCU coordinates execution of instructions using three hardware blocks:
Program Address Generator (PAG)
Program Decode Controller (PDC)
Program Interrupt Controller (PIC)
These blocks perform the following functions:
o Fetch instructions
o Decode instructions
o Execute instructions
o Control hardware DO loops and REP
o Process interrupts and exceptions
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16.  The PCU implements a seven-stage pipeline and controls the
different processing states of the DSP56300 core.
 The PCU contains a number of registers such as program
counter register (PCN), status register (SRN), loop address
register (LAN), loop counter register (LCR), vector base
address register (VBAN), Stack pointer and so on. It also
contains a hardware stack.
 The PDC decodes the 24-bit instruction loaded into the
instruction latch and generates all signals necessary for
pipeline control.
 The PAG contains all the hardware needed for program
address generation, system stack, and loop control.
 The PIC arbitrates among all interrupt requests (internal
interrupts, as well as the five external requests IRQA, IRQB,
IRQC, IRQD, and NMI) and generates the appropriate interrupt
vector address.
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17. On Chip Memory
 The memory space of the DSP56300 core is partitioned into
o Program memory space
o X data memory space
o Y data memory space
 The data memory space is divided into X data memory and Y
data memory in order to work with the two address ALUs and
to feed two operands simultaneously to the data ALU.
 Memory space includes internal RAM and ROM and can be
expanded off-chip under software control.

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18. The DSP56301 has 8KX24-bit on-chip RAM which can be configured in a variety
of ways shown in Table below under software control.
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19. Internal Buses
 The following buses shown in architecture provide data exchange between
the functional blocks of the core:
o Peripheral I/O expansion bus (PIO_EB) to peripherals
o Program memory expansion bus (PM_EB) to program RAM
o X memory expansion bus (XM_EB) to X memory
o Y memory expansion bus (YM_EB) to Y memory
o Global data bus (GDB) between PCU and other core structures
o Program data bus (PDB) for carrying program data throughout the core
o X memory data bus (XDB) for carrying X data throughout the core
o Y memory data bus (YDB) for carrying Y data throughout the core
o Program address bus (PAB) for carrying program memory addresses
throughout the core
o X memory address bus (XAB) for carrying X memory addresses
throughout the core
 Y memory address bus (YAB) for carrying Y memory addresses
throughout the core. All internal buses on the DSP56300 family
members are 16-bit buses except the PDB, which is a 24-bit bus.
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20. On Chip Peripheral
Host Interface (HI32)
Enhanced Synchronous Serial Interface (ESSI)
Serial Communications Interface (SCI)
 Timer Module
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