The document describes the features and specifications of the DSP56824 16-bit digital signal processor, including its programmable peripherals, memory capabilities, and interface options. It is well-suited for cost-sensitive applications like digital wireless devices and cameras due to its low cost, configuration flexibility, and compact code. The evaluation module provides peripherals like memory, a codec, LEDs, and buttons to help develop and test applications for the DSP56824.

1. Session: 2015-2016 (Even Semester)
Semester/Branch/Section: –VI / ETC – C
Name of Subject: Digital Signal Processing
TAE-III:
Study of Data sheet of 56824 DSP processors
Name of Student
1.Akash J. Shahu (Roll No. 26)
2.Ashish M. Pandey (Roll No. 30)
Date of Submission: 02/03/2016
Signature of Faculty:

2. DSP56824 16-BIT DIGITAL SIGNAL PROCESSOR
The DSP56824 is a member of the DSP56800 core-based family of Digital Signal
Processors (DSPs). This general purpose DSP combines processing power with
configuration flexibility, making it an excellent cost-effective solution for signal
processing and control functions. Because of its low cost, configuration flexibility,
and compact program code, the DSP56824 is well-suited for cost-sensitive
applications, such as digital wireless messaging, digital answering
machines/feature phones, modems, and digital cameras.
The DSP56824 supports program execution from either internal or external
memories. Two data operands can be accessed from the on-chip data RAM per
instruction cycle. The rich set of programmable peripherals and ports provides
support for interfacing multiple external devices, such as codecs, microprocessors,
or other DSPs. The DSP56824 also provides two external dedicated interrupt lines
and sixteen to thirty-two General Purpose Input/ Output (GPIO) lines, depending
on peripheral configuration.
Features:
 DSP56824 16-bit Digital Signal Processor @ 70Mhz, and 3.3volts
 64Kx16-bit external Program Memory 0 wait state @70MHz
 64Kx16-bit external Data Memory 0 wait state @70MHz
 64K-bit SPI EEPROM memory for program and data storage
 Expansion connectors to allow the addition of external peripherals and
debug the DSP's signals
 JTAG interface connector for external Command Converter Interface
 On-board Parallel Command Converter Interface, with a connector for PC
printer port connections
 13-bit linear Codec for voice applications with line-in and line-out jack
connectors
 Low cost crystal oscillator for DSP frequency input
 SPIUART with RS-232 interface for easy connection to host processor
 On-board power regulation with external 7-12V AC/DC supplied power
input
 Three on-board real-time user debugging LEDs
 Two on-board switches to externally interrupt the DSP56824
 On-board power on reset with reset switch

3. Functional Block Diagram:
Block Diagram Description:
COP - Computer Operating Properly - A method for ensuring an embedded
program is
working properly. We won't worry about this.
GPIO - General Purpose Input/Output - We will use these to control physical
devices; particularly 3 LED's.
Interrupts - Used to force the processor to perform a particular routine.
Memory - Where data and program are stored.
PLL - Phase Locked Loop - Used to generate clock signals.
RTI - Real Time Interrupt - Hardware used to generate interrupts on a periodic
basis (e.g., for sampling)

4. SPI - Serial Peripheral Interface - We will use this to communicate with the PC
SSI - Serial Synchronous Interface - We will use this to communicate with the
CODEC (A/D and D/A converter)
Timer/Event Counters - We can use these to keep track of time (e.g., to set a
sampling
rate).
Pin Diagram:

5. Pin Diagram Description:
Power (VDD or VDDPLL):
VDD: These pins provide power to the internal structures of the chip, and
should all be attached to VDD.
VDDPLL: This pin supplies a quiet power source to the VCO to provide
greater frequency stability.
Ground (VSS or VSSPLL):
VSS: These pins provide grounding for the internal structures of the chip,
and should all be attached to VSS
VSSPLL: This pin supplies a quiet ground to the VCO to provide greater
frequency stability.
PLL and Clock Signals
EXTAL:
External Clock/Crystal Input—This input should be connected to an
external clock or oscillator. After being squared, the input clock can be
selected to provide the clock directly to the DSP core. The minimum
instruction time is two input clock periods, broken up into four phases
named T0, T1, T2, and T3. This input clock can also be selected as input
clock for the on-chip PLL.
XTAL:
Crystal Output—This output connects the internal crystal oscillator output to
an external crystal. If an external clock is used, XTAL should not be
connected.
CLKO
Chip- Clock Output—This pin outputs a buffered clock signal. By
programming CS[1:0] bits in the PLL Control Register(PCR1), the user can
selectbetween outputting a squared version of the signal applied to EXTAL
and a version of the DSP master clock at the output of the PLL. The clock
frequencyon this pin can also be disabled by programming the CS[1:0] bits
in PCR1

6. SXFC:
External Filter Capacitor—This pin is used to add an external filter circuit to
the Phase Lock Loop (PLL)
Address, Data, and Bus Control Signals:
A0–A15:
Address Bus—A0–A15 change in T0, and specify the address for external
program or data memory accesses.
D0–D15:
Data Bus—Read data is sampled in by the trailing edge of T2, while write
data output is enabled by the leading edge of T2 and tri-stated by the
leading edge of T0. D0–D15 are tri-stated when the external bus is inactive.

7. Specifications/ Characteristics with ratings:
The DSP56824 is fabricated in high-density CMOS with Transistor-Transistor
Logic (TTL)-compatible inputs, 5-volt tolerant Input/Output (I/O), and CMOS-
compatible outputs. Absolute maximum ratings given in Table 17 are stress ratings
only, and functional operation at the maximum is not guaranteed. Stress beyond
these ratings may affect device reliability or cause permanent damage to the
device.
The DSP56824 dc/ac electrical specifications are preliminary and are from design
simulations. These specifications may not be fully tested or guaranteed at this early
stage of the product life cycle. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
AC ElectricalCharacteristics
(VSS = 0 V, VDD = 2.7–3.6 V, TA = –40to +85C, CL = 50 pF)
ExternalClock Operation
(VSS = 0 V, VDD = 2.7–3.6 V, TA = –40to +85C, CL = 50 pF)

8. Applications:
EVM
The EVM has several peripherals attached will be useful. In particular it has:
 64k of program memory and 64k of data memory - more than we will need.
 A JTAG interface so we can do debugging.
 A 13 bit A/D and D/A converter (CODEC - Coder/Decoder)
 3 LED's (Light Emitting Diodes) that we can use for debugging.
 Two push-button switches (not shown) used for input.