1. Department of Electrical and Computer Engineering
ECE 311 - Final Project - Dr. Hossain
Building a Half Adder Circuit Using PMOS and NMOS Transistors
Jon Lepp
4/30/2015

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Table of Contents:
1. Objective 2
a. Brief Introduction to Project Assignment
b. Objectives to be Completed
2. Theory 2-3
a. Digital Theory of Project
b. Logic Gate Level Analysis
c. Logic Gate Schematics
i. Schematic 1
ii. Schematic 2
d. Explanation of Pull Up/Pull Down Networks
e. CMOS Transistor Half Adder Schematic 3
f. CMOS Transistor Half Adder Simulation 4
3. Circuit 5
a. Circuit explanation
b. Fig P.1 (Circuit built in Lab)
4. Data/Analysis 5-9
a. Collection of Data from Lab
b. Oscilloscope Captures
i. Fig P.2 Displays Inputs and Corresponding Outputs 6
ii. Fig P.3 Expanded View of Fig P.2 6
iii. Fig P.4 Rise and Fall Times of Outputs 7
iv. Fig P.5 Displays Logical Failure in Circuit 7
v. Fig P.6 Low to High Delay 8
vi. Fig P.7 High to Low Delay 9
c. Delays 7-9
i. Rise Time Explanation and Measurement Procedure
ii. Fall Time Explanation and Measurement Procedure
iii. Total Delay
iv. Total Delay Formula and Calculation Procedure
5. Conclusion 9

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Objective
The objective of the final project is to create a half adder circuit that adds two one bit binary
numbers and displays both the sum and the carry as outputs. This project is an extension of lab
eight, and is implemented using CMOS transistors as well as pull up and pull down networks to
implement different digital logic gates.
Theory
The half adder circuit has several configurations. It is generally created using two logic gates
consisting of the XOR gate and the AND gate (see Schematic 1). In order to implement an XOR
gate using transistors, the XOR gate can be broken down into several combinations of gates. The
design chosen for the XOR gate consists of the NAND, OR, and the AND gates. The half adder
circuit will consist of two AND gates, one NAND gate, and an OR gate (see Schematic 2).
Each of the gates from Schematic 2 can be implemented using one CD4007 chip that
contains six transistors consisting of three PMOS and three NMOS transistors. The final design
for the half adder circuit will consist of only four CD4007 chips with three inputs (𝑉𝑑𝑑 , 𝑉𝐴 , 𝑉𝐵)
and two outputs (sum and carry). Regardless of how efficiently the transistors are used within the
CD4007 chip (i.e. only 4 transistors used in a chip versus all 6 being used), the number of chips
still results in four chips being implemented in the final design. Thus, the final design will use
one CD4007 chip for each digital logic gate in Schematic 2.
Schematic 1 Schematic 2
To create the half adder circuit entirely of transistors, it is easiest to go gate by gate and
design each of the pull up and pull down networks for each gate (see lab 8). Because this is an
extension of lab eight, this step has already been completed. Using a hierarchical method, build
each of the gates separately on the breadboard and test each gate to see that each gate and their
functionality are correct individually and there are no problems with the CD4007 chip. Finally,
connect each of the gates together to see that the half adder is working.
The half adder will take two binary inputs and display the sum as a binary output. There
are two outputs for the half adder, one for the sum, and an additional output for the carry. There
are four situations expected to arise from the outputs when two binary numbers are entered at the
input terminals of the half adder circuit. The carry output will go logically high when the two
binary inputs add up to two. This situation arises when both inputs 𝑉𝐴 and 𝑉𝐵 are both logical
high (a 1 1 is entered as input). The sum will go logically high when the two binary inputs add
up to one. This situation arises when one input is logically high and the other is logically low for

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any combination of 𝑉𝑎 and 𝑉𝑏 (a 1 0 or a 0 1 is entered as input). Both outputs will display a
logical low when both inputs are logically low (0 0 is entered).
The CMOS Half Adder Schematic below is the same schematic as seen in schematic 2,
however, it is implemented using CMOS transistors. Each of the outputs to the transistor
networks is labeled to resemble an input or output to a gate. This makes the schematic easily
visible as transistors as well as digital logic gates.
There are three voltage inputs labeled on the lower left side of the schematic and two
outputs labeled sum and carry in the upper right of the schematic. 𝑉𝑑𝑑 in the schematic is a
supply voltage used to create the pull up and pull down networks for the transistors to operate
correctly. 𝑉𝑎 and 𝑉𝑏 are created using DC pulse trains. In order to test all situations for the circuit,
the pulse trains must be set up to test all binary inputs (i.e. 00 01 10 and 11).
CMOS Half Adder Schematic
The CMOS Half Adder Simulation below implements the circuit seen in the CMOS Half
Adder Schematic. The inputs in green and blue represent 𝑉𝑎 and 𝑉𝑏 respectively. The output
“sum” is displayed in red and the output “carry” is displayed in light blue. As expected, the sum
(red waveform) is logically high in the simulation when the two inputs add up to a binary one (10
or 01 entered). The sum (red waveform) is displayed as logically low when the binary sum adds

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up to two or zero (11 or 00 entered). The output carry (blue waveform) is high when two inputs
add up to a binary two (11 entered). In all other conditions carry (blue waveform) is zero.
CMOS Half Adder Simulation
The circuit in Fig P.1 was built using the simulated schematic. 𝑉𝐷𝐷 is the red jack on the
breadboard and runs through all the positive rails (red rails) on the breadboard with the exception
of the second rail running horizontally at the top of the breadboard and the furthest left rail on the
breadboard. These two rails consist of the inputs 𝑉𝑎 and 𝑉𝑏. These are the only rails used for
these inputs. In addition to these rails the wires are also color coordinated with these two inputs.
The longest yellow wires leading to the chip correspond to the yellow wire going to the yellow
jack (i.e. input 𝑉𝑏). The longest orange wires leading to the chip correspond to the orange wire
going to the green jack (i.e. input 𝑉𝑎). Ground is the black jack and runs through the same rails as
𝑉𝐷𝐷 on the negative side (all blue rails). Ground and 𝑉𝐷𝐷 are run through several different rails
for wire convenience.
The top three chips on the breadboard consist of the sum part of the half adder and the
bottom chip consists of the carry portion of the circuit. There are two outputs that appear to be
sticking out of the breadboard. The output wire sticking out of the breadboard that is blue in
color corresponds to the sum. The output wire sticking out of the breadboard that is yellow in
color corresponds to the carry output.

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Circuit
Fig P.1
Data and Analysis
The oscilloscope capture in Fig P.2 displays the inputs and the outputs. The period is in
milliseconds to show several cycles of the inputs and outputs. It also displays the frequencies and
the amplitudes of the inputs 𝑉𝑎 in yellow and 𝑉𝑏 in green. This waveform is used to see all
possible combinations of binary inputs to the half adder circuit to test all possible combinations
of sum and carry outputs.

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Fig P.2
The oscilloscope capture in Fig P.3 is similar to Fig P.2. The period is much smaller in
order to zoom in on the waveforms. Fig P.2 and Fig P.3 both display the inputs and outputs to the
half adder circuit. Both also display the frequencies and amplitudes to the circuit. Freq(1) should
be 500 Hz in Fig P.3. The oscilloscope capture in Fig P.3 is used to test a few of the
combinations of the sum and carry outputs to the half adder circuit.
Fig P.3
The oscilloscope capture in Fig P.4 displays the rise and fall times of the outputs
measured on the oscilloscope. The rise and fall times must be taken into account when finding
the delay of the circuit. Both rise and fall times for both the sum and the carry can be found as
measured values in nanoseconds on the right side of the oscilloscope capture found in Fig P.4.
Rise(3) and Fall(3) in blue correspond to the delay for the sum output and Rise(4) and Fall(4)
correspond to the delay for the carry output.

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Fig P.4
The oscilloscope capture in Fig P.5 displays what happens when the input voltage is too
low and the logic begins to fail in the circuit. For this circuit, the logic begins failing at 4.8 volts.
As shown in the oscilloscope capture, both of the outputs are being affected by the low voltage
level provided as input to the half adder circuit.
Fig P.5
The final measurements taken for the half adder circuit is the delay. This is measured
using the cursors on the oscilloscope. Find a region of the inputs and the blue output where the
output is affected by the combination of the inputs. Two of these regions need to be found. One
region where the logic goes from high to low and the other region is where the logic goes from

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low to high. These are the regions of high to low delay and low to high delay. Next, spread out
the waveform to the point where the output no longer looks like an ideal DC voltage waveform.
Use the cursors to find the high point of the high to low delay area. Place the first x cursor at the
point where the logic level begins to drop. Place the second x cursor where the y cursors indicate
the halfway point of the output wave. The delay measured in nanoseconds will be displayed on
the right side of the oscilloscope. Next, do the same procedure for the low to high delay. These
are the delays measured low to high and high to low. The actual delay of the circuit can be found
for the circuit by taking these two values, adding them together, and dividing by two to find the
average of the two delays. This procedure uses the formula below where 𝜏 𝑃𝐻𝐿 is the delay
measured high to low by the oscilloscope and 𝜏 𝑃𝐿𝐻 is the delay measured low to high by the
oscilloscope. Taking the average of the two delays gives the total delay of the circuit given by
𝜏 𝑃 .
The oscilloscope captures in Fig P.6 and Fig P.7 below consist of the process described
above. The capture below in Fig P.6 shows the low to high delay as 166 ns and the capture in Fig
P.7 displays the high to low delay as 66 ns. Thus, the total delay for the entire circuit after
finding the average of the two delays is 116 ns.
Fig P.6

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Fig P.7
Conclusion
In conclusion to the final project, several digital logic gates have been implemented into one
circuit to see a larger resulting half adder circuit that successfully takes two binary inputs, adds
them together, and displays the output as a sum and a carry. In addition, time delay
measurements have been taken to see the effects of different speeds with different logic gates.
Also, with a circuit such as this one where several parts are being implemented into one, some
troubleshooting skills are acquired along the way.