This document describes a project to design a sequential circuit to calculate the remainder (modulo-3) of an n-bit number A. The circuit uses a divide-and-conquer approach with multiple finite state machines (FSMs) running in parallel. A 128-bit shift register sequentially feeds bits to the FSMs. A 7-bit counter generates signals to stop the FSMs after processing all bits. The FSM outputs are combined using additional logic to produce the final remainder. The design aims to calculate the remainder in n/4 clock cycles, faster than the n cycles of a single FSM.

1. Sidharth Kumar: skumar37@uic.edu
Bahareh Pourshirazi: bpours2@uic.edu
UIC
ECE 465: PROJECT 2
CLOCK Period: 13.5ns

2. 1
Contents
Figure 1: Schematic of basic mod-3 FSM......................................................................................................2
Figure 2: Working of the FSM .......................................................................................................................4
Figure 3: Basic design for the System ...........................................................................................................6
Figure 4: 4-bit Shift Register .........................................................................................................................7
Figure 5: Connecting two 4-bit Shift registers ..............................................................................................8
Figure 6: MUXed Shift Register.....................................................................................................................9
Figure 7: 7-bit Counter and generation of Last signal.................................................................................11
Figure 8: Combinational Logic.....................................................................................................................13
Figure 9: Amod3 Calculator ........................................................................................................................14
Table 1: Connecting outputs of shift register to the MUX............................................................................9
Table 2: Truth table for output logic...........................................................................................................12
Table 3: K-map for the output function......................................................................................................12

3. 2
PROJECT-2 PART-1
Objective
Design a basic mod-3 FSM that gets its input bits of A sequentially. Besides the single current A bit, it will
receive 2 other bits in parallel with the A-bit, start and last.
Start=1, when the A-bit is the MSB, and is 0 otherwise.
Last= 1, when the A-bit is the LSB, and is 0 otherwise.
Design
The n-bit input, A can be given as MSB first or LSB first. We design it for the MSB first as it takes only 3
states as shown in the Figure 1. These states are the remainders obtained when input A is divided by 3,
hence - 0, 1 and 2. The design is a Moore’s machine hence the output is only dependent on the states.
Figure 1: Schematic of basic mod-3 FSM
0
1
Start
1
1
1 2
1
0
0
0
0
Reset

4. 3
Working
The FSM should start working as soon as it sees the START bit. So, we need to start from the state which
shows the remainder for the first bit. It can be 0 or 1, hence we need a logic for the START bit.
Also, the FSM should stop after the LSB of A has been fed. LAST = 1 at this moment and we would want
our FSM to stay in this state until we pass a RESET signal. We have put LAST as an input to a Flip-Flop as
we would want the FSM to stop only after the remainder for last bit has been calculated. We AND CLK
signal with the LAST’ (not LAST) so that the Flip-Flops do not see any further clocks and will not calculate
anything after that.
We need 4 1:2 De-MUX’s for the proper working of our FSM. One of them handles which state the START
should be fed into. The other 3 handle input to the next states depending on the input A. Every time the
FSM sees an input bit, it goes to the next state or stays in the same state depending upon the input bit.
Figure 2 depicts the schematic for the whole circuit.
Example:
Outputs have been taken out from states 1 and 2 as R1 and R0. This is because we have designed One-hot
design. Only one of the outputs can be 1 every clock cycle. In case output of state-0 is 1, R1R0=00. So we
don’t need to take the output from the state-0. Since the input A is being fed 1-bit at a time without a
register, we don’t need the S0, S1 bits. Hence they are absent in the circuit. RESET’ is needed to clear all
the Flip-Flops.
Delay Calculations
The critical path delay in the next state logic is from the output of a De-MUX to the input of a Flip-Flop
(shown in the Figure 2).
Delay = 2-input AND gate + 3-input OR gate = 5 units
Delay from Quartus = 6.538 ns
Critical path delay in the output logic for the Moore machine is delay from the output or the last sate FF.
In this case, outputs of state 1 and state 2 are the final outputs. (Output of state 0 is shown when outputs
of state 1 and 2 are 0). Hence the delay is 0.
Setup time for the FF’s = 1.697 ns
A A mod 3
10 2
100 1
1001 0
10011 0

5. 4
Critical path delay
for NS logic
Critical path delay
for output logic
Figure 2: Working of the FSM

6. 5
PROJECT-2 PART-2
Objective
Design a sequential circuit that can determine the remainder of an n-bit number A after division by 3 (i.e.,
determine A mod 3). Circuit should be composed of multiple interacting FSMs that are obtained using a
divide-and-conquer (D&C) approach. Using this approach, the outputs of the FSMs are “stitched-up” using
a purely combinational circuit to produce the desired output of the original problem. FSMs should use
One-hot-design style and the circuit is based on Moore Machine. The clock cycles needed to calculate the
result of n-bit number should be in range of n/4.
Design
In part-1, we have designed a FSM which can calculate the mod of an n-bit number in n ccs. But we want
it to be faster. In order to achieve the result in n/4 ccs, we will need 4 of the FSMs. A register is needed
which can feed all these FSMs at the same time and a combinational logic will be required to stitch up the
results from the FSMs to get the final result. Once the last bit of A is fed, we need to prevent the FSMs
from further calculations. Hence a counter is also required which can generate internal signals to
stop/reset/clear the register/FSM. A common clock signal will be fed to each and every component in the
system. A basic design will look like Figure3.

7. 6
Figure 3: Basic design for the System
Partitioning Logic
n/4 bits are fed into each FSM
Shift
128-bitShiftRegister
Q128Q96Q64Q48Q32Q24Q16Q12Q8Q4
Thebit
goesto
FSM1
Thebit
goesto
FSM2
Thebit
goesto
FSM3
Thebit
goesto
FSM4
S0
S1
Clock
Data[127..0]
FSM1
FSM2
FSM3
FSM3
AnadderaddsthenumbersthatcomesoutoftheFSMs
SinceeachFSM’soutputisanumberbetween0-2,theresult
ofsumwillbeanumberbetween0-8
Sowehavea
CombinationalLogicthatcalculatesthe
mod3ofanumberbetween0-8
Clock
Counter
Last
signals

8. 7
Shift Register
Since the maximum number of input bits can go up to 128, we need a 7-bit register. It is better to use a
shift register as we can feed the outputs of the register to the FSM’s one bit every clock cycle. So we need
to come up with a design which stores the first data input, lets the FSM calculate the remainder and starts
shifting the bits in the next cc. It means we should have a data input to the FSM at every cc.
Instead of using the registers from library, we decided to build our own shift register which doesn’t have
unnecessary input/output pins. The logic behind the shift register is the same. The only changes which
were made was to provide output pins for only those outputs which will be required for our design.
(Selection of the output pins has been discussed later in the MUXed Shift register section)
So we start with the 4-bit Shift register and grow it to 16-bit, 32-bit, 64-bit and finally 128-bit shift register.
A 4-bit shift register and the logic needed to connect two of them is been shown in Figure4 and 5.
The register starts feeding the FSMs as soon as Start signal goes low. This has been done in order to avoid
faulty inputs to the register if we have the Start signal high for a long time. We have connected Start’ to
Shift pin of the register. Hence the number of working ccs should be counted ‘only after Start goes low’.
As we will see later that it takes exactly n/4 ccs to feed the input to the FSMs after Start is 0.
This register allows us to feed n-bit input (up to 128 bits) sequentially to the FSMs. We can use the
necessary outputs (as shown in Figure) and feed them to all the FSM at the same time. This allows the
FSMs to work in parallel. According to the problem statement, we can have 4 values of n: 16, 32, 64 and
128. We have been provided select bits S0, S1. This calls for using a MUX which can break the register in
a way that we don’t have to wait for n ccs to get the nth bit and we can have a faster design.
Figure 4: 4-bit Shift Register

9. 8
Figure 5: Connecting two 4-bit Shift registers

10. 9
MUXed Shift Register
We have a 7-bit Shift Register but we don’t want all the bits every time. We can have 4 different number
of inputs – 16, 32, 64, 128. We can design a MUX which will provide us the output from the register based
on the number of input bits. Select lines S1S0 define how the register behaves. The design is as shown in
the Figure6. This serves as the partitioning logic.
Example: In case S1S0 = 01, number of input bits = 32. We want the 7-bit register to behave as 4-bit
register. So we can use Q8, Q16, Q24 and Q32 outputs from the register and feed it to every second input
of the MUX (Check the table). The outputs will give us 32 bits in 8 clock cycles. These will serve as inputs
to the 4 FSM’s. So each FSM gets 8 bits and hence takes 8 clock cycles to calculate the remainder. So
instead of taking n clock cycles, we go down to n/4 ccs.
S1S0 P1 P2 P3 P4
00(A) Q4 Q8 Q12 Q16
01(B) Q8 Q16 Q24 Q32
10(C) Q16 Q32 Q48 Q64
11(D) Q32 Q64 Q96 Q128
Table 1: Connecting outputs of shift register to the MUX
Figure 6: MUXed Shift Register
P1
P2
P3
P4

11. 10
Counter
It is evident from our design concept that we would like the FSMs to stop the calculations once the last
bit of A has been fed. This can be done using a counter. We have designed a counter which can count till
64 (6-bit counter). We can use this counter to generate the Last signal based on values of S0, S1.
The counter has only two necessary input pins: clock and Load. We will connect Load to delayed (by 1cc)
Start because we want it to generate the Last signals exactly after the FSMs have completed their
calculation. The other inputs to the counter are grounded to make the reset state as 0. So it counts from
0 once Start is 0. As we will notice in the simulation that the FSM’s calculate the result exactly after 1 cc
the inputs are fed to it. That means we would like to stop the calculations after (n/4+1) ccs (after Start
went low).
This gives the information that for a 16-bit A, we should stop the calculation when counter is at 4 (starting
from 0). Similarly for 32, 64 and 128-bit A, the calculation should be stopped at 8, 16 and 32 respectively.
Let’s call the outputs of the counter as Q5Q4Q3Q2Q1Q0. If we look at the pattern, we find that for a 16-bit
A, the Last signal (Last4) can be given as OR of Q5, Q4, Q3 and Q2, i.e. as soon any of these are high, Last4
will be triggered and the FSMs will stop. The expressions for all the Last signals is given below:
Last4 = Q5 + Q4 + Q3 + Q2
Last8 = Q5 + Q4 + Q3
Last16 = Q5 + Q4
Last32 = Q5
These signals will be chosen based on S1, S0 values. So we can feed these signals to a 4-1 MUX with S1,
S0 as the select lines. The output of the MUX is a high signal when the above expressions are true. Counter
and the Last signal generation logic is shown in Figure7.

12. 11
Figure 7: 7-bit Counter and generation of Last signal

13. 12
Combinational Logic
As we are using 4 FSM’s in parallel, each of them will be producing a 2-bit remainder value ranging from
0-2. But this is not the final result. We need to stitch them up using some function.
If we add all the remainders, we can see that the range of the sum value will be 0-8. Hence it is clear that
we need an adder to add the 4 2-bit remainders. The 2-bit numbers have been added using 4 FA’s and 3
HA’s by applying D&C approach. It results in a 4-bit value.
Using the property of Mod function, (a + b) mod k = [(a mod k) + (b mod k)] mod k, we can say that the
mod of the sum value will be the final result or mod(A). We can use a FSM to calculate the mod. But as
we have seen, it will take 4 clock cycles which we don’t want. Instead, we can design a simple
combinational logic for this part as well. The truth table below describes the logic.
S3 S2 S1 S0 R1 R0
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 0 0
0 1 1 1 0 1
1 0 0 0 1 0
Table 2: Truth table for output logic
S3S2S1S0 are the 4-bit sum values and R1R0 is the mod-3 value. For the sum values 9-15, we have R1R0
as don’t cares. We can write the expressions for R1 and R0 using a 4-bit K-map.
R1 R0
S1S0-> 00 01 11 10 S1S0->
S3S2
00 01 11 10
S3S2
00 1 00 1
01 1 01 1 1
11 X X X X 11 X X X X
10 1 X X X 10 X X X X
Table 3: K-map for the output function
R1 = S3 + S2’S1S0’ + S2S1’S0
R0 = S2S1’S0’ + S2’S1’S0 + S2S1S0
So all we need is 5 3-input AND gates and 2 3-input OR gates. Also, it gives us the result right away because
it is independent of the clock. The combinational logic is as shown in the Figure8.

14. 13
Figure 8: Combinational Logic

15. 14
Final design
Since we have all our components ready, it’s time to assemble them and build the whole system which
works as per the design defined in Figure3.
As we want the system to work only after Start is 0, we have connected Start to the Reset of the FSMs.
Hence the FSM is reset as long as Start = 1. We want the counter/register to work exactly after Start is 0.
So we provide the counter/register a delayed Start signal (1 cc). Hence a FF is added to the Start signal.
The output of MUXed register goes to the 4 FSMs and the output of FSMs are fed to the combinational
logic. The output of combinational logic is the final answer.
The final result is shown exactly after (n/4+2) ccs if we consider that the Start signal is high only for 1 cc.
At this point, based on S1, S0, the counter triggers the Last signal which is the output of the 4-1 MUX. We
invert the output of MUX and AND it with the clock which is being fed to the FSMs. The FSMs will not see
a clock until Start = 1. For the next input, Start = 1 and hence the counter will be in the clear mode and
the output of the MUX = 0. The FSM restart based on the new input. In the .vwf file, it can be observed
that the result stays at the same value until another number is fed, i.e. when Start = 1.
Figure 9: Amod3 Calculator
Counter
4-1 MUX
Counter
MUXed
Shift
Register
Combinational
Logic
FSM

16. 15
Analytical Delay Calculations
All numbers are based on unit of delay.
Partitioning Logic:
Critical path goes through one 41 Mux:
21-Mux: 5 (Max is for one NOT gate, one AND gates, one OR), 41-Mux: 2×5=10
 Partitioning logic: 10.
Next-State Logic:
Critical path is between the first and the second FF.
De-Mux21: 3 (one NOT, one AND), OR-3: 3  NS logic: 6.
Output Logic:
There are no gates: 0.
Stitch-Up Logic:
Critical path goes through two FAs and one NOT gate, one 3-input AND gate and one 3-
input OR gate.
FA: 6 (XOR-2, AND-2, OR-2) S-U logic: 2×6+7(NOT, AND-3, OR-3) = 19.
Total delay:
(n/4+1) × max (𝑻 𝑭𝑭 +𝑻 𝒔𝒖+ 6 (NS logic), 𝑻 𝑭𝑭 +𝑻 𝒔𝒖+ 10(Partitioning logic)) + 19
The partitioning is performed in the first cc when we are loading the data inside the register, then
during the next n/4+1 ccs, the FSM calculates the result. In the worst case, we have n/4 changes
among the states, one at each cc. It is worth noting that the delay of the FSM would be (n/4 +1)
cc because it takes one clock cycle for a Flip-Flop to show a change on its input on its output. As
we know that 𝑇𝐶𝑙𝑘=1.1 max (𝑇𝑃,𝐹𝐹+ 𝑇 𝑁𝑆,𝑃−𝑙𝑜𝑔𝑖𝑐 +𝑇𝑠𝑢, 𝑇𝑃,𝐹𝐹+𝑇𝑂𝑃,𝑃−𝑙𝑜𝑔𝑖𝑐) for a sequential logic. This
is because it has to be long enough to accommodate the delay of going through a Flip-Flop and
going to the next state or the output. Our design also has a partitioning combinational logic
between two sequential logics (shift-register and an FSM). The system clock should be long
enough to accommodate this combinational logic as well. Stitch-up logic on the other hand is not
between two flip flop, so it will not change the clock period. If the delay of this combinational
logic is less than clock period, we will get the result in a cc or else we would need multiple ccs to
have the stitch-up logic done.

17. 16
Hardware Cost Calculation
Partitioning Logic:
21-Mux: 7 (1 for the Not gate, 4 for the AND gates, 1 for the OR), 41-Mux: 21 units
 Partitioning logic: 4×21= 84.
Next-State Logic:
Four De-Mux21: 4×5= 20, OR gates: 9  20 + 9 = 29.
Output Logic:
There are no gates: 0.
Stitch-Up Logic:
Two OR-3: 3×2=6, Five AND-3: 3×5=15, Three NOT: 3, FA: 10×4=40, HA: 4×3=12
 Stitch-up logic = 6+15+3+40+12=76.
Counter:
Eleven 2-input gates: 11×2=22.
To calculate the last signal: 6×2=12.
Total Hardware Cost in terms of the number of inputs: 84 + 29 + 76 = 189 (next-state and output
logic units across all the FSMs, the partitioning logic, and the stitch-up logic).
Number of Flip Flops:
Shift Register:
128 D FFs.
The number of FFs which are used: “n” D Flip-Flops.
FSMs:
4(FSM) × 3 = 12.
Counter:
6 D-FF.
Total FFs = 128+12+6+1(for Start) = 147
FFs which will be used = n+19

18. 17
Quartus delay calculations
Maximum delay of each combinational unit in each FSM
Delay = 7.042ns
Delay of the Partitioning Logic
Delay between output register and input of the FSM.
Delay = 7.597ns
Clock period calculation
Clock period is 𝑇𝐶𝑙𝑘 which is calculated by the following formula:
𝑇𝐶𝑙𝑘=1.1 max (𝑇𝑃,𝐹𝐹+ 𝑇 𝑁𝑆,𝑃−𝑙𝑜𝑔𝑖𝑐 +𝑇𝑠𝑢, 𝑇𝑃,𝐹𝐹+𝑇𝑂𝑃,𝑃−𝑙𝑜𝑔𝑖𝑐)
Here, 𝑇𝑃,𝐹𝐹 is the Flip-Flop propagation delay, 𝑇 𝑁𝑆,𝑃−𝑙𝑜𝑔𝑖𝑐 is the propagation delay of the next
state (NS) logic portion of the entire combinational logic in the system and 𝑇𝑂𝑃,𝑃−𝑙𝑜𝑔𝑖𝑐is the
output logic portion of combinational logic.

19. 18
The clock to Output time given by Quartus is the addition of 𝑇𝑃,𝐹𝐹 and 𝑇𝑠𝑢.
TClk= 1.1*max(7.042+5.161,7.597) = 13.4233ns
Delay of stitch up logic
Delay = 9.794ns
Delay of the whole circuit
Delay starting after input A is stored = 10.734ns
Comparison between empirical and analytical delays
All the delays (except total delay) are constant as we would expect them to be. The number of bits doesn’t
affects these delays. The clock period can be anything larger than the safe value but we would like to keep
it at the safe value to make the system fast.
The total delay or the time taken to produce the output depends on n. As we can see from the simulation
outputs, the result is produced exactly after (n/4+1) ccs, once A is loaded in the register (or Start is low).
This agrees with the analytical delay we have calculated earlier. So we can affirm that the empirical and
analytical delays are of the same order.

20. 19
Conclusion
The system will give correct output for a clock period higher than 13.42ns. As it turns out, in the given vwf
file, for a few cases the clock changes more than 64 times. Hence our Last signal goes low after that point
and the FSM starts working again. So we might need a bigger counter which can keep the Last signal high
for a larger time period. But this doesn’t deviates us from getting the correct output after (n/4+1) ccs.
Still, to get a clear vision of the output, we can keep the clock period set at 16ns (count every 8ns in
Quartus).

21. 20
THANK YOU