This paper presents the research work on multicore microcontrollers using parallel, and time critical
programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work
on the application development phase on such architectures. The experimental results mentioned in the
paper are based on xCORE multicore microcontroller form XMOS®. The paper also imitates multi-tasking
and parallel programming for the same platform. The tasks assigned to multiple cores are executed
simultaneously, which saves the time and energy. The relative study for multicore processor and multicore
controller concludes that micro architecture based controller having multiple cores illustrates better
performance in time critical multi-tasking environment. The research work mentioned here not only
illustrates the functionality of multicore microcontroller, but also express the novel technique of
programming, profiling and optimization on such platforms in real time environments.
A Parallel Computing-a Paradigm to achieve High PerformanceAM Publications
Over last few years there has been rapid changes found in computing field.today, we are using the latest
upgrade system which provides the faster output and high performance. User view towards computing is only to
get the correct and fast result. There are many techniques which improves the system performance. Today’s
widely use computing method is parallel computing. Parallel computing, including foundational and theoretical
aspects, systems, languages, architectures, tools, and applications. It will address all classes of parallelprocessing
platforms including concurrent, multithreaded, multicore, accelerated, multiprocessor, clusters, and
supercomputers. This paper reviews the overview of parallel processing to show how parallel computing can
improve the system performance.
Solution to Operating system concepts ninth edition.
By Navid Daneshvaran, software engineering student at Kharazmi university.
I would be grateful if you would notify me of any errors to solutions.
E-Mail:
nd.naviddaneshvaran@gmail.com
A Parallel Computing-a Paradigm to achieve High PerformanceAM Publications
Over last few years there has been rapid changes found in computing field.today, we are using the latest
upgrade system which provides the faster output and high performance. User view towards computing is only to
get the correct and fast result. There are many techniques which improves the system performance. Today’s
widely use computing method is parallel computing. Parallel computing, including foundational and theoretical
aspects, systems, languages, architectures, tools, and applications. It will address all classes of parallelprocessing
platforms including concurrent, multithreaded, multicore, accelerated, multiprocessor, clusters, and
supercomputers. This paper reviews the overview of parallel processing to show how parallel computing can
improve the system performance.
Solution to Operating system concepts ninth edition.
By Navid Daneshvaran, software engineering student at Kharazmi university.
I would be grateful if you would notify me of any errors to solutions.
E-Mail:
nd.naviddaneshvaran@gmail.com
FellowBuddy.com is an innovative platform that brings students together to share notes, exam papers, study guides, project reports and presentation for upcoming exams.
We connect Students who have an understanding of course material with Students who need help.
Benefits:-
# Students can catch up on notes they missed because of an absence.
# Underachievers can find peer developed notes that break down lecture and study material in a way that they can understand
# Students can earn better grades, save time and study effectively
Our Vision & Mission – Simplifying Students Life
Our Belief – “The great breakthrough in your life comes when you realize it, that you can learn anything you need to learn; to accomplish any goal that you have set for yourself. This means there are no limits on what you can be, have or do.”
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MULTI-CORE PROCESSORS: CONCEPTS AND IMPLEMENTATIONSijcsit
This research paper aims at comparing two multi-core processors machines, the Intel core i7-4960X
processor (Ivy Bridge E) and the AMD Phenom II X6. It starts by introducing a single-core processor machine to motivate the need for multi-core processors. Then, it explains the multi-core processor machine and the issues that rises in implementing them. It also provides a real life example machines such as
TILEPro64 and Epiphany-IV 64-core 28nm Microprocessor (E64G401). The methodology that was used in comparing the Intel core i7 and AMD phenom II processors starts by explaining how processors' performance are measured, then by listing the most important and relevant technical specification to the
comparison. After that, running the comparison by using different metrics such as power, the use of HyperThreading
technology, the operating frequency, the use of AES encryption and decryption, and the different characteristics of cache memory such as the size, classification, and its memory controller. Finally, reaching to a roughly decision about which one of them has a better over all performance.
Advanced computer architecture lesson 1 and 2Ismail Mukiibi
An OS is a program that controls the execution of application programs and acts as an interface between the user of a computer and the computer hardware. .....................
Multicore processor technology advantages and challengeseSAT Journals
Abstract Until recent times, we have worked with processors having a single computing/processing unit (CPU), also called a core. The clock frequency of the processor, which determines the speed of it, cannot be exceeded beyond a certain limit as with the increasing frequency, the power dissipation increases and therefore the amount of heating. So manufacturers came up with a new design of processors, called Multicore processors. A multicore processor has two or more independent computing/processing units (cores) on the same chip. Multiple cores have advantage that they run on lower frequency as compared to the single processing unit, which reduces the power dissipation or temperature. These multiple cores work together to increase the multitasking capability or performance of the system by operating on multiple instructions simultaneously in an efficient manner. This also means that with multithreaded applications, the amount of parallel computing or parallelism is increased. The applications or algorithms must be designed in such a way that their subroutines take full advantage of the multicore technology. Each core or computing unit has its own independent interface with the system bus.. But along with all these advantages, there are certain issues or challenges that must be addressed carefully when we add more cores. In this paper, we discuss about multicore processor technology. In addition to this, we also discuss various challenges faced such as power and temperature (thermal issue), interconnect issue etc. when more cores are added. Key Words: CMP (Chip Multiprocessor), Clock, Core, ILP (Instructions Level parallelism), TLP (Thread level Parallelism).
COMPARATIVE ANALYSIS OF SINGLE-CORE AND MULTI-CORE SYSTEMSijcsit
Overall performance of computer systems are better investigated and evaluated when its various components are considered, components such as the hardware, software and firmware. The comparative analysis of single-core and multi-core systems was carried out using Intel Pentium G640T 2.4GHz dualcore,Intel Pentium IV 2.4GHz single-core and Intel Pentium IV 2.8GHz single-core systems. The approach
method was using hi-tech benchmarking and stress testing software(s) to examine systems’ CPU and RAM
for performance and stability. In all the tests, the components of dual-core had better rating when compared with single-core components; GFLOP result, and execution time for various processes rank G640T 2.4GHz dual-core above Pentium IV 2.4GHz and 2.8GHz single-core respectively.
FellowBuddy.com is an innovative platform that brings students together to share notes, exam papers, study guides, project reports and presentation for upcoming exams.
We connect Students who have an understanding of course material with Students who need help.
Benefits:-
# Students can catch up on notes they missed because of an absence.
# Underachievers can find peer developed notes that break down lecture and study material in a way that they can understand
# Students can earn better grades, save time and study effectively
Our Vision & Mission – Simplifying Students Life
Our Belief – “The great breakthrough in your life comes when you realize it, that you can learn anything you need to learn; to accomplish any goal that you have set for yourself. This means there are no limits on what you can be, have or do.”
Like Us - https://www.facebook.com/FellowBuddycom
MULTI-CORE PROCESSORS: CONCEPTS AND IMPLEMENTATIONSijcsit
This research paper aims at comparing two multi-core processors machines, the Intel core i7-4960X
processor (Ivy Bridge E) and the AMD Phenom II X6. It starts by introducing a single-core processor machine to motivate the need for multi-core processors. Then, it explains the multi-core processor machine and the issues that rises in implementing them. It also provides a real life example machines such as
TILEPro64 and Epiphany-IV 64-core 28nm Microprocessor (E64G401). The methodology that was used in comparing the Intel core i7 and AMD phenom II processors starts by explaining how processors' performance are measured, then by listing the most important and relevant technical specification to the
comparison. After that, running the comparison by using different metrics such as power, the use of HyperThreading
technology, the operating frequency, the use of AES encryption and decryption, and the different characteristics of cache memory such as the size, classification, and its memory controller. Finally, reaching to a roughly decision about which one of them has a better over all performance.
Advanced computer architecture lesson 1 and 2Ismail Mukiibi
An OS is a program that controls the execution of application programs and acts as an interface between the user of a computer and the computer hardware. .....................
Multicore processor technology advantages and challengeseSAT Journals
Abstract Until recent times, we have worked with processors having a single computing/processing unit (CPU), also called a core. The clock frequency of the processor, which determines the speed of it, cannot be exceeded beyond a certain limit as with the increasing frequency, the power dissipation increases and therefore the amount of heating. So manufacturers came up with a new design of processors, called Multicore processors. A multicore processor has two or more independent computing/processing units (cores) on the same chip. Multiple cores have advantage that they run on lower frequency as compared to the single processing unit, which reduces the power dissipation or temperature. These multiple cores work together to increase the multitasking capability or performance of the system by operating on multiple instructions simultaneously in an efficient manner. This also means that with multithreaded applications, the amount of parallel computing or parallelism is increased. The applications or algorithms must be designed in such a way that their subroutines take full advantage of the multicore technology. Each core or computing unit has its own independent interface with the system bus.. But along with all these advantages, there are certain issues or challenges that must be addressed carefully when we add more cores. In this paper, we discuss about multicore processor technology. In addition to this, we also discuss various challenges faced such as power and temperature (thermal issue), interconnect issue etc. when more cores are added. Key Words: CMP (Chip Multiprocessor), Clock, Core, ILP (Instructions Level parallelism), TLP (Thread level Parallelism).
COMPARATIVE ANALYSIS OF SINGLE-CORE AND MULTI-CORE SYSTEMSijcsit
Overall performance of computer systems are better investigated and evaluated when its various components are considered, components such as the hardware, software and firmware. The comparative analysis of single-core and multi-core systems was carried out using Intel Pentium G640T 2.4GHz dualcore,Intel Pentium IV 2.4GHz single-core and Intel Pentium IV 2.8GHz single-core systems. The approach
method was using hi-tech benchmarking and stress testing software(s) to examine systems’ CPU and RAM
for performance and stability. In all the tests, the components of dual-core had better rating when compared with single-core components; GFLOP result, and execution time for various processes rank G640T 2.4GHz dual-core above Pentium IV 2.4GHz and 2.8GHz single-core respectively.
This research paper aims at comparing two multi-core processors machines, the Intel core i7-4960X processor (Ivy Bridge E) and the AMD Phenom II X6. It starts by introducing a single-core processor machine to motivate the need for multi-core processors. Then, it explains the multi-core processor machine and the issues that rises in implementing them. It also provides a real life example machines such as TILEPro64 and Epiphany-IV 64-core 28nm Microprocessor (E64G401). The methodology that was used in comparing the Intel core i7 and AMD phenom II processors starts by explaining how processors' performance are measured, then by listing the most important and relevant technical specification to the comparison. After that, running the comparison by using different metrics such as power, the use of HyperThreading technology, the operating frequency, the use of AES encryption and decryption, and the different characteristics of cache memory such as the size, classification, and its memory controller. Finally, reaching to a roughly decision about which one of them has a better over all performance.
Hardback solution to accelerate multimedia computation through mgp in cmpeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
1. What important part of the process switch operation is not shown .pdffathimaoptical
1. What important part of the process switch operation is not shown in Figure 3.4?
2. What is the operational difference between single-threaded and multi-threaded processes? i.e.,
how does it change the usage of each?
3. What kinds of operations take advantage of threads? Think of depth and breadth.
1).consider task parallelism
2).consider data parallelism
4.What is the difference between Many to One, One to One, and Many to Many models?
1).What are the benefits and constraints of each of these?
2).Provide examples of each of these
3).How does the two-level model help thread operations? process Po operating system process P
interrupt or system call executing save state into PCBo idle reload state from PCB1 dle interrupt
or system call executing save state into PCB1 idle reload state from PCB0 executing Figure 3.4
Diagram showing CPU switch from process to process.
Solution
PCB daigaram.
1.The Program control Block diagram is important ,we have PCB in the diagram,but in detail.
For each process there is a Process Control Block, PCB,
which stores the following ( types of ) process-specific information, as illustrated in Figure 3.1. (
Specific details may vary from system to system. )
•Process State - Running, waiting, etc., as discussed above.
•Process ID, and parent process ID.
•CPU registers and Program Counter - These need to be saved and restored when swapping
processes in and out of the CPU.
•CPU-Scheduling information - Such as priority information and pointers to scheduling queues.
•Memory-Management information - E.g. page tables or segment tables.
•Accounting information - user and kernel CPU time consumed, account numbers, limits, etc.
•I/O Status information - Devices allocated, open file tables, etc.
2.With a single thread process, the process runs/executes on single path.With multiple thread
process is where a process runs/executes on two or more paths.
Applications with multithreading implementation increases its responsiveness to the
application’s users, for instance;
with traditional single-threaded process implementation within a web server can serve only one
client request at a time and can make the waiting period for other users requesting services a very
long time.
With more efficient multithreaded server implementation; separate threads can be created to
respond to different users’ requests.
Multithreading technique in the above example increased the application responsiveness to the
users’ requests.
3.
Multiple Processes ,example proxy server satisfying the requests for a number of computers on a
LAN would be benefited by a multi-threaded process.
Task parallelism is the simultaneous execution on multiple cores of many different functions
across the same or different datasets.
This form of parallelism covers the execution of computer programs across multiple processors
on same or multiple machines. It focuses on executing different operations in parallel to fully
utilize the available computing resources in form of proces.
DYNAMIC TASK SCHEDULING ON MULTICORE AUTOMOTIVE ECUSVLSICS Design
Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and
motivated towards adding more advanced features and sophisticated applications to the existing electronic
system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more
sophistication in vehicle electronics system. All these, directly make the vehicle software system more
complex and computationally more intensive. In turn, this demands very high computational capability of
the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have
already been implemented in some of the task rigorous ECUs like, power train, image processing and
infotainment. To achieve greater performance from these multicore processors, parallelized ECU software
needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the
computational cores to the maximum extent possible and meet the real time constraint. In this paper, we
propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU
utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their
real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems
Architecture (AUTOSAR).
Dynamic task scheduling on multicore automotive ec usVLSICS Design
Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and
motivated towards adding more advanced features and sophisticated applications to the existing electronic
system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more
sophistication in vehicle electronics system. All these, directly make the vehicle software system more
complex and computationally more intensive. In turn, this demands very high computational capability of
the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have
already been implemented in some of the task rigorous ECUs like, power train, image processing and
infotainment. To achieve greater performance from these multicore processors, parallelized ECU software
needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the
computational cores to the maximum extent possible and meet the real time constraint. In this paper, we
propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU
utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their
real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems
Architecture (AUTOSAR).
DYNAMIC TASK SCHEDULING ON MULTICORE AUTOMOTIVE ECUSVLSICS Design
Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and motivated towards adding more advanced features and sophisticated applications to the existing electronic system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more
sophistication in vehicle electronics system. All these, directly make the vehicle software system more complex and computationally more intensive. In turn, this demands very high computational capability of the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have already been implemented in some of the task rigorous ECUs like, power train, image processing and infotainment. To achieve greater performance from these multicore processors, parallelized ECU software needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the computational cores to the maximum extent possible and meet the real time constraint. In this paper, we propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU
utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems Architecture (AUTOSAR).
Concurrent Matrix Multiplication on Multi-core ProcessorsCSCJournals
With the advent of multi-cores every processor has built-in parallel computational power and that can only be fully utilized only if the program in execution is written accordingly. This study is a part of an on-going research for designing of a new parallel programming model for multi-core architectures. In this paper we have presented a simple, highly efficient and scalable implementation of a common matrix multiplication algorithm using a newly developed parallel programming model SPC3 PM for general purpose multi-core processors. From our study it is found that matrix multiplication done concurrently on multi-cores using SPC3 PM requires much less execution time than that required using the present standard parallel programming environments like OpenMP. Our approach also shows scalability, better and uniform speedup and better utilization of available cores than that the algorithm written using standard OpenMP or similar parallel programming tools. We have tested our approach for up to 24 cores with different matrices size varying from 100 x 100 to 10000 x 10000 elements. And for all these tests our proposed approach has shown much improved performance and scalability
AN EFFICIENT HYBRID SCHEDULER USING DYNAMIC SLACK FOR REAL-TIME CRITICAL TASK...ijesajournal
Task intensive electronic control units (ECUs) in automotive domain, equipped with multicore processors ,
real time operating systems (RTOSs) and various application software, should perform efficiently and time
deterministically. The parallel computational capability offered by this multicore hardware can only be
exploited and utilized if the ECU application software is parallelized. Having provided with such
parallelized software, the real time operating system scheduler component should schedule the time critical
tasks so that, all the computational cores are utilized to a greater extent and the safety critical deadlines
are met. As original equipment manufacturers (OEMs) are always motivated towards adding more
sophisticated features to the existing ECUs, a large number of task sets can be effectively scheduled for
execution within the bounded time limits. In this paper, a hybrid scheduling algorithm has been proposed,
that meticulously calculates the running slack of every task and estimates the probability of meeting
deadline either being in the same partitioned queue or by migrating to another. This algorithm was run and
tested using a scheduling simulator with different real time task models of periodic tasks . This algorithm
was also compared with the existing static priority scheduler, which is suggested by Automotive Open
Systems Architecture (AUTOSAR). The performance parameters considered here are, the % of core
utilization, average response time and task deadline missing rate. It has been verified that, this proposed
algorithm has considerable improvements over the existing partitioned static priority scheduler based on
each performance parameter mentioned above.
Theory related to OS :
It Includes:
1. Unit I (COMPONENTS OF COMPUTER SYSTEM)
2. Unit II (OPERATING SYSTEM STRUCTURE)
3. Unit III (PROCESS MANAGEMENT)
4. Unit IV (MEMORY MANAGEMENT)
5. Unit V (FILE SYSTEM)
6. Unit VI (INPUT OUTPUT SYSTEM)
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
PIP-MPU: FORMAL VERIFICATION OF AN MPUBASED SEPARATION KERNEL FOR CONSTRAINED...ijesajournal
Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources).
In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification.
Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit
(MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained
environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in
the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the
demonstration of the formal verification strategy on two representative kernel services. The publicly
released proofs have been implemented and checked using the Coq Proof Assistant for three kernel
services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of
an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.
International Journal of Embedded Systems and Applications (IJESA)ijesajournal
International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.
Pip-MPU: Formal Verification of an MPU-Based Separationkernel for Constrained...ijesajournal
Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources). In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification. Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit (MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the demonstration of the formal verification strategy on two representative kernel services. The publicly released proofs have been implemented and checked using the Coq Proof Assistant for three kernel services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.
International Journal of Embedded Systems and Applications (IJESA)ijesajournal
International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.
Call for papers -15th International Conference on Wireless & Mobile Network (...ijesajournal
15th International Conference on Wireless & Mobile Network (WiMo 2023) is dedicated to addressing the challenges in the areas of wireless & mobile networks. The Conference looks for significant contributions to the Wireless and Mobile computing in theoretical and practical aspects. The Wireless and Mobile computing domain emerges from the integration among personal computing, networks, communication technologies, cellular technology, and the Internet Technology. The modern applications are emerging in the area of mobile ad hoc networks and sensor networks. This Conference is intended to cover contributions in both the design and analysis in the context of mobile, wireless, ad-hoc, and sensor networks. The goal of this Conference is to bring together researchers and practitioners from academia and industry to focus on advanced wireless and Mobile computing concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to.
Call for Papers -International Conference on NLP & Signal (NLPSIG 2023)ijesajournal
Scope & Topics
International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP).
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:
Topics of interest include, but are not limited to, the following
Chunking/Shallow Parsing
Dialogue and Interactive Systems
Deep learning and NLP
Discourseand Pragmatics
Information Extraction, Retrieval, Text Mining
Interpretability and Analysis of Models for NLP
Language Grounding to Vision, Robotics and Beyond
Lexical Semantics
Linguistic Resources
Machine Learning for NLP
Machine Translation
NLP and Signal Processing
NLP Applications
Ontology
Paraphrasing/Entailment/Generation
Parsing/Grammatical Formalisms
Phonology, Morphology
POS tagging
Question Answering
Resources and Evaluation
Semantic Processing
Sentiment Analysis, Stylistic Analysis, and Argument Mining
Speech and Multimodality
Speech Recognition and Synthesis
Spoken Language Processing
Statistical and Knowledge based methods
Summarization
Theory and Formalism in NLP
Signal Processing & NLP
Computer Vision, Image Processing& NLP
NLP, AI & Signal
Paper Submission
Authors are invited to submit papers through the conference Submission System by May 06, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by International Journal on Cybernetics & Informatics (IJCI) (Confirmed).
Selected papers from NLPSIG 2023, after further revisions, will be published in the special issue of the following journals.
International Journal on Natural Language Computing (IJNLC)
International Journal of Ubiquitous Computing (IJU)
International Journal of Data Mining & Knowledge Management Process (IJDKP)
Signal & Image Processing : An International Journal (SIPIJ)
International Journal of Ambient Systems and Applications (IJASA)
International Journal of Grid Computing & Applications (IJGCA)
Important Dates
Submission Deadline : May 06, 2023
Authors Notification : May 25, 2023
Final Manuscript Due : June 08, 2023
International Conference on NLP & Signal (NLPSIG 2023)ijesajournal
International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP).
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:
11th International Conference on Software Engineering & Trends (SE 2023)ijesajournal
11th International Conference on Software Engineering & Trends (SE 2023)
May 27 ~ 28, 2023, Vancouver, Canada
https://acsit2023.org/se/index
Scope & Topics
11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.
Topics of interest include, but are not limited to, the following
The Software Process
Software Engineering Practice
Web Engineering
Quality Management
Managing Software Projects
Advanced Topics in Software Engineering
Multimedia and Visual Software Engineering
Software Maintenance and Testing
Languages and Formal Methods
Web-based Education Systems and Learning Applications
Software Engineering Decision Making
Knowledge-based Systems and Formal Methods
Search Engines and Information Retrieval
Paper Submission
Authors are invited to submit papers through the conference Submission System by April 08, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings (H index 35) in Computer Science & Information Technology (CS & IT) series (Confirmed).
Selected papers from SE 2023, after further revisions, will be published in the special issue of the following journals.
The International Journal of Software Engineering & Applications (IJSEA) -ERA indexed
International Journal of Computer Science, Engineering and Applications (IJCSEA)
Important Dates
Submission Deadline : April 08, 2023
Authors Notification : April 29, 2023
Final Manuscript Due : May 06, 2023
11th International Conference on Software Engineering & Trends (SE 2023)ijesajournal
11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.
PERFORMING AN EXPERIMENTAL PLATFORM TO OPTIMIZE DATA MULTIPLEXINGijesajournal
This article is based on preliminary work on the OSI model management layers to optimized industrial
wired data transfer on low data rate wireless technology. Our previous contribution deal with the
development of a demonstrator providing CAN bus transfer frames (1Mbps) on a low rate wireless channel
provided by Zigbee technology. In order to be compatible with all the other industrial protocols, we
describe in this paper our contribution to design an innovative Wireless Device (WD) and a software tool,
which will aim to determine the best architecture (hardware/software) and wireless technology to be used
taking in account of the wired protocol requirements. To validate the proper functioning of this WD, we
will develop an experimental platform to test different strategies provided by our software tool. We can
consequently prove which is the best configuration (hardware/software) compared to the others by the
inclusion (inputs) of the required parameters of the wired protocol (load, binary rate, acknowledge
timeout) and the analysis of the WD architecture characteristics proposed (outputs) as the delay introduced
by system, buffer size needed, CPU speed, power consumption, meeting the input requirement. It will be
important to know whether gain comes from a hardware strategy with hardware accelerator e.g or a
software strategy with a more perf
GENERIC SOPC PLATFORM FOR VIDEO INTERACTIVE SYSTEM WITH MPMC CONTROLLERijesajournal
Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. In this context,
a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC.
The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the
deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.
This paper presents an inverting buck-boost DCDC converter design. A negative supply voltage is needed
in a variety of applications, but only a few DCDC converters are available on the market. OLED, a new
display type especially suited for small digital camera or mobile phone displays. Design challenges that
came up when negative voltages have to be handled on chip will be discussed, such as
continuous/discontinuous mode transition problems, negative voltage feedback and negative over-voltage
protection. Both devices operate in a fixed frequency PWM mode or alternatively in PFM mode. The single
inductor topology is called inverting buck-boost converter or simply inverter. The proposed converter has
been implemented with a TSMC 0.13-um 2P4M CMOS process, and the chip area is 325 x 300 um2.
A Case Study: Task Scheduling Methodologies for High Speed Computing Systems ijesajournal
High Speed computing meets ever increasing real-time computational demands through the leveraging of
flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
Payment industry is largely aligned in their desire to create embedded payment systems ready for the
modern digital age. The trend to embed payments into a software platform is often regarded as first step
towards a broader trend of embedded finance based on digital representation of fiat currencies. Since it
became clear to our research team that there are no technologies and protocols that are protected against
attacks of quantum computing, and that enable automatic embedded payments, online or offline with no
fear of counterfeit, P2P or device-to-device to be made in real time without intermediaries, in any
denomination, even continuous payments per time or service, while preserving the privacy of all parties,
without enabling illicit activities, we decided to utilize the Generic Innovation Engine [1] that is based on
the Artificial Intelligence Assistance Innovation acceleration methodologies and tools in order to boost the
progress of innovation of the necessary solutions. These methodologies accelerate innovation across the
board. It proposes a framework for natural and artificial intelligence collaboration in pursuit of an
innovative (R&D) objective The outcome of deploying these Artificial Innovation Assistant (AIA)
methodologies was tens of patents that yield solutions, that a few of them are described in this paper. We
argue that a promising avenue for automated embedded payment systems to fulfil people’s desire for
privacy when conducting payments, and national security agencies demand for quantum-safe security,
could be based on DeFi and digital currencies platforms that does not suffer from flaws of DLT-based
solutions, while introducing real advantages, in all aspects, including being quantum-resilient, enabling
users to decide with whom, if at all, to share information, identity, transactions details, etc., all without
trade-offs, complying with AML measures, and accommodating the potential for high transaction volumes.
It is not legacy bank accounts, and it is not peer-dependent, nor a self-organizing network.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
2 nd International Conference on Computing and Information Technology ijesajournal
2
nd International Conference on Computing and Information Technology Trends
(CCITT 2023) will provide an excellent international forum for sharing knowledge and
results in theory, methodology and applications of Computing and Information Technology
Trends. The Conference looks for significant contributions to all major fields of the
Computer Science, Compute Engineering, Information Technology and Trends in theoretical
and practical aspects.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Vaccine management system project report documentation..pdfKamal Acharya
The Division of Vaccine and Immunization is facing increasing difficulty monitoring vaccines and other commodities distribution once they have been distributed from the national stores. With the introduction of new vaccines, more challenges have been anticipated with this additions posing serious threat to the already over strained vaccine supply chain system in Kenya.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
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Time critical multitasking for multicore
1. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
DOI : 10.5121/ijesa.2015.5101 1
TIME CRITICAL MULTITASKING FOR MULTICORE
MICROCONTROLLER USING XMOS®
KIT
Prerna Saini1,
Ankit Bansal2
and Abhishek Sharma3
1,3
Department of Electronics and Communication Engineering, LNM Institute of
Information Technology, Jaipur, India
2
Department of Electronics and Communication Engineering, GLA University, Mathura,
India
ABSTRACT
This paper presents the research work on multicore microcontrollers using parallel, and time critical
programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work
on the application development phase on such architectures. The experimental results mentioned in the
paper are based on xCORE multicore microcontroller form XMOS®
. The paper also imitates multi-tasking
and parallel programming for the same platform. The tasks assigned to multiple cores are executed
simultaneously, which saves the time and energy. The relative study for multicore processor and multicore
controller concludes that micro architecture based controller having multiple cores illustrates better
performance in time critical multi-tasking environment. The research work mentioned here not only
illustrates the functionality of multicore microcontroller, but also express the novel technique of
programming, profiling and optimization on such platforms in real time environments.
KEYWORDS
Multicore microcontroller, xCORE, xTIMEcomposer, Multitasking, Parallel programming, Time slicing,
Embedded System, Time critical programming.
1.INTRODUCTION
In the present era of technology, computational power [1] plays an important role. The multicore
microprocessor devices [2] are already available in CISC architecture which used to perform non
real time computing. Recently there has been a huge demand of high computing speed in time
critical system, mostly in real time embedded device. Technology is growing exponentially every
day with the demand of more power and processing handling capabilities. The basic need of a
multicore system is the distributed and parallel computing [3]. Time consumption is the drawback
of single core processors, so multicore [4] technology is used to achieve efficiency through
parallel processing. Parallel processing [5] is the simultaneous use of more than one CPU to
execute a program or multiple computational threads. The main goal of parallel processing is a
high performance [6] computing, which speedup the execution time of the program. Parallel [7]
processing makes programs run faster because there are more engines (CPUs or cores) workingon
it. It increases the efficiency, safe execution time, take less energy and retain the time. Multicore
has two or more CPUs while the single core has only one core inside it as illustrated in figure1.
To enhance the performance [8] of single core processor, it is mandatory to increase the
frequency as CPU load increases. It causes heat losses and leakage current so rather than increase
the clock frequency of single core, manufacture switched to multicore to avoid the power [9]
consumption problem and to increase speed and efficiency.
2. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
2
Figure 1. Block Diagram of Single-core and Multi-core Processor
As the number of the taskis rapidly increasingthe user wants to perform more than one task at a
time, but a computer with a single-core performs one operation at a time [10]. Although with
software threads, some amount of parallelization is possible, but it does not give satisfactory
results. In multicore scenario, it is possible to perform operations at comparatively high speed
[11] to perform paralleled task and save time. Table 1 represents the difference between single
core and multicore and shows that multicore has more advantage over single core with respect to
processing speed, power and operation handling ability etc.
Table 1. Comparison between single core and multi core system
Parameter Single-Core Multi-Core
No of cores One primary core Two or more separate core
Processing Sequential Parallel
SMT Not Possible Possible
Power Low High
Speed Slow Fast
Efficiency Low High
Operation One task at a time Multitasking
The multi-processing system has two types, namely homogeneous and heterogeneous. If all the
cores are identical and have the same features like message passing system, cache, threading,
share memory and resources then it is called homogeneous multi-core processors. In
heterogeneous [12] systems all the cores have different features; it can vary clock cycles
according to system requirements to achieve low power or ultra-low power mode.Flynn’s
taxonomy is a specific classification of parallel computer architectures that are based on the
number of concurrent instruction (single or multiple) and data streams (single or multiple)
available in the architecture [13]. Figure2 shows the evolution of multicore era thatevery single
processor replaced by a multicore processor to get high performance [14]. At the present time,
there is vast use of multicore [15] system. In future, no filed will be untouched with multicore
system.The first dual core microprocessor was Power-4 [16], [17] which was designed by the
IBM®
in 2001.
3. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
3
Figure 2. Evaluation Era of Multicore system
Amdahl’s law [18] is used to find out the speedup of a multicore system. Speedup is how much
time taken by a program to execute through the single core divide by the time taken by a program
when n number of processors execute in parallel manner as illustrated in equation 1 and 2 which
shows that as the number of cores in a processor is increased, the speed of a system is also
enhanced, but it is impossible to fully parallelize the program. Suppose a program takes 10 hours
using single core and a particular portion of that program which cannot be parallelized take at
least 1 hour, then by increasing the number of cores, execution time and speedup of the system
cannot be changed. By increasing the number of cores somehow speed up is increased, but it
depends upon how much a program can be parallelized.
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=
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ܶሺ1ሻ ቀܤ +
ଵ
ሺ1 − ܤሻቁ
=
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ܤ +
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… ሺ2ሻ
In parallel processing [19], every core executes the multiple set of instructions as an individual
processing unit. The CPU istreated as a single unitso the end user can divide the whole task into
subsection and send to various cores. Due to parallel processing all the core work simultaneously
so it enhances processing speed and save the time. Important of parallelism is increased because
complex problems can be split into smaller programs that can be executed at the same time to
reduce execution time. Basically parallelism is subdivided in two broad areas i.e. Instruction
level parallelism (ILP) and threads level parallelism. ILP tells, how many simultaneous
instructions can be executed, and thread level parallelism (TLP), is about how many simultaneous
threads can be executed. In a multicore system Parallelization is possible because it spilt threads
and assigns it to each core and all works simultaneously. Execution within a processor is very
quick and inexpensive for the time. Task parallelism is shown in figure 3.
0
50
100
150
1999 2001 2003 2005 2007 2009 2011 2013 2015
Numberofcores
Year
Evaluation of Multicore
4. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
4
Figure 3. Multithreading in multicore systems
The microprocessor has only CPU, it does not have RAM, ROM and other peripheral on the chip,
but the microcontroller contain all the basic components as shown in figure 4. A microcontroller
has two kinds of design mechanics, i.e. UMA (Unified Memory Architecture) and NUMA (Non
Unified Memory Architecture), although it can also be distinguished by Single Instruction
Multiple Data (SIMD) and Multiple Instruction Multiple Data(MIMD). Table 2 illustrated the
difference between microcontroller and microprocessor which show that the microcontroller has
more advantage over microprocessor.
Table 2. Difference between microcontroller and microprocessor
Parameter Microcontroller Microprocessor
Meaning Computer on chip CPU on chip
Inbuilt components CPU, Memory & Peripheral
Unit
CPU ONLY
Memory Architecture UMA UMA and NUMA
Purpose Specific General
Chips All components on chip Multiple chip for components
Circuit Simple Complex
No of Registers More Less
Operation Registers based Memory based
Clock Frequency Low High
Cost Low High
Speed Fast Fastest
.
There are vast applications of multicore microprocessors. The market trends show that in general
purpose computing processors are playing a key role. The entire major manufacturer is deploying
their Integrated Circuit(IC) with its functionality. Processors are designed for general purpose; it
can’t be used in embedded application for that user need multicore microcontroller. Multicore
microcontroller [20] is used in embedded application and Real Time Operating System(RTOS) in
which time is a major factor. In real time application multicore microcontroller play a major role.
In all major time critical operations, including defence, military, medical, industrial, etc. handled
by multicore microcontroller. Recently mangalyaan launched in Indiain Mars orbit in low cost is
5. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
5
managed by multicore microcontroller. Table 3 compares the multicore microcontroller and
multicore microprocessor and show that multicore microcontroller has a huge advantage over
multicore microprocessor.
Figure 4. Illustrating Multicore Microcontroller vs Multicore Microprocessor
Table 3. Distinction between multicore microcontroller and multicore microprocessor
Parameters Multicore Microcontroller Multicore Microprocessor
Architecture Harvard Von Neumann
Instruction Set RISC CISC
Power M Hz G Hz
Execution time In nano sec or micro sec In milisec or in sec
Cost Chip Expensive
Interrupt Given by the program Hardware and Software Interrupt
Priority Not define, All are executed
parallel
Masskable and Non Maskable
Cache Not used Used
Tile Define Not define
Time Critical Analysis Can be done Can not done
Power conception Low High
Power Saving Mode Available Not Available
Application Embedded system and RTOS General purpose
2. XMOS®
STARTKIT
startKIT [21] is a xCORE multicore microcontroller that has eight 32 bit logical processor cores
on two tiles as shown in figure5 which is taken from XMOS®
XS architecture [22]. The size of
startKIT is very small. The startKIT dimensions are 94 x 50mm. The startKIT require 5V which
are given by Micro-USB cable. The regulator is used to convert this 5V to 1V and 3V which is
used by external devices. Table 4 gives the overview of startKIT. It is very easy to use and simple
to program. User can easily design complex embedded system using high level language. Each
core acts as separately and able to run multiple real time tasks simultaneously. It provides 500
million instructions per second (MIPS) which make this more powerful than conventional
microcontroller. It provides a uniquely scalable, timing deterministic architecture that provides
extremely low latency and an I/O response that is 100 times faster than standard processors. If a
6. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
6
core is waiting for data, the xTIME hardware scheduler will pass the execution resource to the
next core making efficient use of the available processor resource and saving power.
XMOS®
provides xTIMEcomposer [23] IDE for designing applications. It supports high level
languages like C,C++, XC (extension of C). It has inbuilt debugger, compiler, simulator and
editor. xTIMEcomposer provide many functionalities to improve the performance and check
various parameters like time, delay. xTIMEcomposer provide XMOS®
Timing Analyser (XTA
[24]) tool which allow developers to identify worst case and best case execution time for code
blocks and functions. It also provides xSCOPE [25] which allow capturing the data from running
time. Figure 6 explains the architecture of XMOS®
startKIT. startKIT has two tiles. Tile 0 is
dedicated to the integrated debugger and Tile 1 is user-programmable. It has 8 cores with 500
MIPS. Micro-USB connector (B) is used as a debugger. It connects to the host PC and allows
running the program.
Dimension 94 x 50mm
No of Core 8
No of Tiles 2
Word Length 32 Bit
Architecture RISC
Cache Not Used
Clock Freq. 500 MHz
SRAM 64 KB
FLASH 256K Bytes
Voltage 5V, 3V3, GND
Programming
Language
High Level
Language
Table 4. XMOS®
startKIT overview Figure 5. XMOS®
architecture [22]
startKIT provide GPIO pins which allow developers to reconfigure the capabilities of devices to
support many different applications. PCle slot is used to extend the hardware capabilities, 1*5
PCIs connected (J6) and 1*12 GPIO header (J7) is used to connect external hardware or
peripheral. If PCIs slot is not used, then the user can use GPIO header [26]. The startKIT is
compatible with the Raspberry Pi connection. The developer can connect Raspberry Pi board with
startKIT using 2*13 Raspberry Pi headers. It is compatible with Raspberry Pi [26] connection. It
disables the LED and push button so the usercannot use LED and button in the Raspberry Pi
header. XMOS®
Links (E)1x13 pin GPIO header (J8) used for connecting multiple startKITs
together.The startKIT provides two and four-zone capacitive touch slider which is illustrated as
an F in figure 6.The startKIT has nine 3*3 green LED as shown in section G.ThestartKIT has two
additional green LED as a display in H.It has 256 KBytesof Serial Peripheral Interface (SPI)
FLASH memory (I), which can be configured by the program.startKIT has one push button (J)
which used as input and its status can be checked by software.startKIT provide 2*3 analogy input
header (K) which is used to give analogyinput.Tile 1 is clocked at 500 MHz, and the I/O ports are
100MHz. The startKIT board is clocked at 24MHz by a crystal oscillator as shown in L.
7. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
Figure
2.1. TASK PARALLELIZATION
XMOS®
[27] use ‘par’constructs
(a) [27]. The compiler automatically checks how m
one core whichever is free. The user can assign the task based on event occurs.
‘select’ keyword as illustrated in figure 7
occur and handle the event which
by the function of interrupt service routine
time stamping.Time stamping manages multiple events with a microcontroller that all require
different timing. For example, you might want to control a servomotor (which requires a 20
millisecond delay), blink an LED once a second, and read some sensors (which should be read as
frequently as possible. One way to handle this is to keep track of a time stamp for each event.
channel is used to communicate between the tasks.
memory. It creates a hang up situations
data at the same time. Channel [27
presenttask is finished now and so
as shown in figure 7 (c) [27]. Sometimes microcontroller can be in
has to wait for some time. XMOS
100 time units led will be high and after the wait for 100 time unit led
Figure 7. Time critical analysis and multitasking using XMOS
International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
Figure 6. Architecture [24] of XMOS®
startKIT
ARALLELIZATION IN XMOS®
STARTKITARCHITECTURE
constructs which allow several tasks to run parallel as illustrated in figure 7
]. The compiler automatically checks how many cores are used and allocatesthe one task to
is free. The user can assign the task based on event occurs. XMOS
yword as illustrated in figure 7 (b) [27] which pause the task and wait for the event to
occur and handle the event which isoccurring which is used as an interrupt. The event is assigned
by the function of interrupt service routine (ISR). Multicore system also allows channelling and
manages multiple events with a microcontroller that all require
different timing. For example, you might want to control a servomotor (which requires a 20
link an LED once a second, and read some sensors (which should be read as
frequently as possible. One way to handle this is to keep track of a time stamp for each event.
channel is used to communicate between the tasks. The user performs tasks parallel with sha
memory. It creates a hang up situations when both the process tries to change or use the same
annel [27] resolves this issue. It sends the signal to processor that
and so anothertask can be performed. XMOS®
used ‘chan
]. Sometimes microcontroller can be ina busy state,at that time user
wait for some time. XMOS®
time stamping explain in figure 7 (d) [27] in which after the
led will be high and after the wait for 100 time unit led will on low stage
Figure 7. Time critical analysis and multitasking using XMOS®
startKIT
International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
7
allel as illustrated in figure 7
any cores are used and allocatesthe one task to
XMOS®
used
] which pause the task and wait for the event to
is used as an interrupt. The event is assigned
(ISR). Multicore system also allows channelling and
manages multiple events with a microcontroller that all require
different timing. For example, you might want to control a servomotor (which requires a 20
link an LED once a second, and read some sensors (which should be read as
frequently as possible. One way to handle this is to keep track of a time stamp for each event. The
tasks parallel with shared
when both the process tries to change or use the same
signal to processor that
han’ keyword
at that time user
] in which after the
low stage.
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8
3. EXPERIMENTAL RESULTS
Experimental results mentioned in this section is based on time critical analysis of sequential and
parallel task on multi core microcontroller XMOS®
and the multicore microprocessor i3 and i5.
3.1. Time critical analysis of sequential and parallel tasks on multicore
microprocessor
Analysis of the sequential and parallel [28] behaviors are observed that there is a huge difference
in their execution time. Multithread program [29] in c executed using POSIX and the thread level
parallelism (TLP) is shown in figure 8. First, it is triedwith two threads then four and eight
threads are usedand shown in figure 8 which is just giving the status of the tread. The results are
checked with the help of profiling, which is obtainedatthe table5. The same process is applied to a
different machine.
Figure 8. Flow chart of thread level parallelism
Nothe same thingng is done by simple sequential c code as shown in figure 9 and obtain the
sequential table as illustrated in table 6 afteanalyzingng the each function execution time as well
aprogramme execution time. The same analysisis done with various otherarchitectures [30]
andthe difference in their execution time and the cache misses by the processor are examined
First program load in the cache then it will be executed. If any variable's value or any instruction
is not available in cache [31] then processor first fetches the instruction which takes some time
that is called cache misses.
Figure9. Flow chart of sequential program
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Table6. Sequential Profiling Table
Architecture Compiler No of
Functions
Compile time(sec) Exc. time of
each
function(sec)
Cache Misses (%)
Intel i3 Gcc 2 real =30.528
user =30.480
sys =0.044
First = 15.40
Second =15.41
I1 Misses =0.49
D1 Misses =1.1
LLi Misses =0.25
LLd Misses =0.6
LL Misses =0.3
Intel i5 Gcc 2 real =18.579
user =18.580
sys =0.008
First = 9.14
Second =9.13
I1 Misses =0.48
D1 Misses =1.1
LLi Misses =0.25
LLd Misses =0.6
LL Misses =0.3
Intel i3 Gcc 4 real =1m0.987
user =1m0.911
sys =0m0.068
First = 15.39
Second =15.41
Third =15.40
Fourth =15.30
I1 Misses =0.48
D1 Misses =1.1
LLi Misses =0.25
LLd Misses =0.6
LL Misses =0.3
Intel i5 Gcc 4 real =37.332
user =37.340
sys =0.016
First = 9.47
Second =9.28
Third =9.22
Fourth =9.22
I1 Misses =0.46
D1 Misses =1.1
LLi Misses =0.25
LLd Misses =0.6
LL Misses =0.3
Intel i3 Gcc 8 real =2m2.215
user =2m2.030
sys =0m0.160
First = 15.39
Second =15.34
Third =15.32
Fourth =15.31
Fifth=15.34
Sixth=15.32
Seventh=15.34
Eighth=15.32
I1 Misses =0.48
D1 Misses =1.1
LLi Misses =0.25
LLd Misses =0.6
LL Misses =0.3
Intel i5 Gcc 8 real =1m13.649
user =1m13.692
sys =0.024
First = 9.27
Second =9.27
Third =9.26
Fourth =9.26
Fifth=9.25
Sixth=9.24
Seventh=9.22
Eighth=9.13
I1 Misses =0.48
D1 Misses =1.1
LLi Misses =0.25
LLd Misses =0.6
LL Misses =0.3
Various architectures used different frequency which affects the execution time. The
experimental results mentioned in table 5 and table 6 explain how function execution time varies
with architecture which is illustrated in figure 10. Not only the architecture but also the number of
threads [32] is important the execution time of a machine. In parallelcomputation all the CPUs are
treated as individual entity which are connected to each other for better communication and it
executes all the threads at the same time, which could be proven with the help of figure 11, it
could also be observed with the same diagram that every function has a different time boundation
that is also known as time bounded computation.The execution speed of Intel®
i3 to Intel®
[33] i5
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11
reduces as the frequency of the device increases its results are illustrated in table
6.Aftercomparing the results mentioned in tables 5 and 9 the conclusion is that the good amount
of possibility that multicore arc. For controllers are very effective and efficient for time critical
execution.
Figure 10 shows the execution time depends upon the architecture also. As Intel®
i5 has higher
frequency [34] than Intel®
i3 and also Intel®
i3 has only 2 cores (dual core) and Intel®
i5 has four
courses. Intel®
i5 has less execution time in comparison to Intel®
i3. Execution time reduces as
the frequency and number of core increases. Even applying the same code for different-2
processors, then also we get different-2 time. As it is noticed that in every caseexecution time is
less in parallel of Intel®
i5 than Intel®
i3 (which has number of cores) as shown in figure 11 that's
proves requirement of multi-core and parallel processing is increasing rapidly.
Figure10. Function Execution time
Figure 11. Total execution time
Although same program is used for sequential as well as the parallel processing, but in the
parallel processing Intel®
i3 takes almost 5 sec and Intel®
i5 takes 2 sec and in case of sequential
program Intel®
i3 takes 15 sec and Intel®
i5 takes 9 sec which is shown in figure10. The total
execution time [35] depends upon the architecture and the number of threads or function used by
the program. As the number of threads and function increases, total execution time of the
processor increases as we used same threads and the same program. Using ®
i3 with 2 functions in
a parallel program is given worst execution time, whereas in Intel®
i5 with same 2 functions in
parallel processing [36] gives best result as illustrated in figure 11.
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3.2. Time Critical analysis of sequential and parallel task on Multi core
microcontroller
Results show that the development of parallel program by xtime composer for SK131552, the
task mentioned in the core has the special property of activating and setting a specific character
using 3x3 led matrix which is communicating through inbuilt com port i.e. 32 which is 20 bits
long. The 1st bit from first led & 2nd bit from second led & 3rd bit assign to third led. 8th bit,
9th, 10th, 11th, 12th, 13th bit assigns to fourth, fifth, sixth, seventh, eighth & ninth led
respectively, Others are don’t care. The words like ‘Y’ ‘O’ ‘U’ ‘K’ is as shown in figure 12(a)-
(d).
Figure 12(a). Display Y 3*3 LED Figure 12(b). Display O 3*3 LED
Figure 12(c). Display U 3*3 LED Figure 12(d). Display K 3*3 LED
The sequential flow chart of spinning ball is shown in Figure 13 in which 3x3 led glows and
rotate in a circle.Figure 14 shows the flow chart of a pattern shift in which LEDs of the first
column, then second, then third column, then first, second then third row glows and are repeated
again in the same manner.
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13
Figure 13. Sequential execution of spinning ball
program
Figure 14. Sequential execution of pattern
formation program
Parallelization is demonstrated using the servo motor. Flow chart of Servo motor control is shown
in figure 15 using xTOOLS [27] the obtained result is shown in figure 16. The platform summary
shows the how many cores, timer, memory and channel used by the program. It also displays the
value of timer and how much memory occupied by the program. startKIT [27] has 8 logical cores,
32 channels, 655036 bites memory space and 10 timer. Table 7 illustrates how many of them are
occupied by this program.
Figure 15. Flow chart of servo motor control Figure16. Analysis
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Table 7. Result of servo motor control
Name Used Free
Chanends 0% 100%
Logical Cores 1(12.5%) 7(97.5%)
Memory 336bit(0.51%) 65200bit(99.49%)
Timer 1(10%) 9(90%)
Multitasking [36] is also performed in this which 4 tasks perform simultaneously as shown in
figure 17, with the help of ‘par’ keyword. First two cores are assigned to blink the two additional
led and third core is assigned to display ‘+’ and fourth core is used to display ‘X’ in 3x3 led.
Third and fourth core work on same 3x3 led so it required channel by using ‘chan’ keyword to
assign the task so that both cannot overlap also profiling is done using gproof and noted that how
much time is taken by all the functions and result [37] is shown in table 8 and its profiling graph
is illustrated in figure 18. How much memory, channels, logical cores and timer used by this
program is illustrated in table 9. In this program stack is also used so memory is occupied by
stacking as well as program.
Figure17. Flow chart of multitasking
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15
Table 8. Execution time of each thread
Function Name Time
task1 125ns
task2 152ns
task3 2.548 micro sec
task4 3.45 micro sec
Table 9. Result of multitasking
Name Used Free
Chanends 3(9.38%) 29(90.63%)
Logical Cores 4(50%) 4(50%)
Memory(Stack) 604(0.92%) 60812(92.79%)
Memory(Program) 4120(6.29%)
Timers 4(40%) 6(60%)
From the experimental results we can illustrate that the time taken by the sequential programming
on multicore[38] microcontroller is in ‘micro seconds’ whereas time [39] taken by the multicore
microprocessor is in ‘seconds’ and ‘minutes’ which proves that the sequential task on
microcontroller can be done faster than the microprocessor. Similarly, the time taken for task
parallelization on multicore [40] microcontroller is in ‘nanoseconds’ whereas multicore
microprocessor takes ‘seconds’ which again proves that the parallel task on microcontroller can
be done faster than the microprocessor.
4. CONCLUSIONS
It can be seen that the time critical analysis on micro controller, task parallelization for complex
programming structures can be compiled in less time, although it has been observed that these
techniques of programming are easy for an advanced developer but tough for a new or the
beginners. Using above mentioned results user easily analyze the performance of multicore
microcontroller. The task Parallelization for multicore controller is still a challenge due to its
complex programming structure, but it gives high versatility and reliability to perform real-time
operations. The Future focus of the research is to implement it in automation control system using
SPI and I2C interfaces.In this research every thread is assigned by the controller to its different
cores by itself, future goal will concentrate by hand on assignment of threads on the cores. Also
in this paper time critical analysis results and examples are restricted only for basic
applications.Future work will be focused on expansion of present experimentations on time
critical analysis on real time applications and embedded system.
ACKNOWLEDGEMENTS
The authors would like to thank to Dr. Abhishek Sharma for their guidance and constant
supervision as well as for providing necessary information regarding the project & also for their
support in completing the project. The authors would like to express gratitude towards parents &
16. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
16
member of LNMIIT for their kind co-operation and encouragement which help in completion of
this project. Thanks and appreciations also go to the Texas instrumental Lab.
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AUTHORS
Prerna Saini is pursuing B. Tech in the branch Electronics and Communication
Engineering at the LNM Institute of Information Technology, Jaipur (Rajasthan), India. Her
area of interests is embedded System, Multicore Microcontroller and Microprocessor and
High Performance Computing.
Ankit Bansal is pursuing B. Tech in the branch Electronics and Communication
Engineering at GLA University, Mathura (U.P), India. His current interests are in
Embedded System, Multicore Microcontroller and Microprocessor and cloud computing.
18. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
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Abhishek Sharma obtained his B. Tech degree in ECE from Jiwaji University, Gwalior,
India. He worked with two Telecom Companies i.e. ZTE and Huawei. After he worked in
CNR, Milan as Research Engineer. He finished his Ph. D in multicore and many core
systems in 2010 from university of Genoa, Italy. He is currently working as Assistant
Professor in the Dept. of ECE in LNMIIT, Jaipur (Rajasthan), India. His current research
interest includes high performance embedded system, many cores and multicore
architecture.