The document discusses the transition from design for manufacturing (DFM) to physical design for debug (PDFD) to address challenges in debugging integrated circuits at advanced process nodes. PDFD provides design hooks like probe points, navigation features, and spare logic gates to enable silicon debugging techniques like focused ion beam probing and circuit editing. The document outlines PDFD capabilities, scope, and flow and provides examples of PDFD features for flip-chip navigation, bonus logic cells, and clock elements to enhance debug accessibility and productivity.
High Speed & RF Design and Layout: RFI/EMI Considerations (Design Conference ...Analog Devices, Inc.
At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. The design choices begin at the architecture level and extend down to submillimeter placement of traces. There are tried and proven techniques for managing this process. The practical issues of real system design is covered in this session, along with ways to minimize signal degradation in the RF environment.
This document describes PPI's quality standards and certifications for manufacturing printed circuit boards. It lists numerous certifications including ISO 9001, AS9100, FDA registration, and others. It then provides details on PPI's capabilities for various types of circuit board design and manufacturing, including multilayer boards, rigid-flex boards, HDI boards, and IC substrates. It also discusses prototype and quick turn services, as well as conformal coating capabilities.
With the ever changing environment in the medical device market, companies face continuous pressure to make their products smaller, lighter, more portable and of course, less costly.
Epec has over 60 years of experience in working with medical customers and the stringent requirements that go along with medical devices. We will be presenting a webinar that outlines some new technologies and techniques that can help companies achieve all of their product goals.
Please join us for our upcoming product webinar for more information on how Epec can help you with all your medical device needs.
The document provides an overview and summary of Nobuya Okada's educational background, work experience, achievements, skills, and personality. It includes 3 sections: 1) Education/career overview which lists his educational history and work experience. 2) Job details which summarizes his major achievements and roles developing various ASICs and IPs over 21 years of experience. 3) Other profile which outlines his patent/awards, language skills, personality traits, and commitments.
In this Webinar, Epec will review primary design requirements that are best served by the utilization of flex or rigid-flex circuit boards within a given design. Additionally we will address the primary cost drivers that impact the per part cost.
To learn more information on our flex & rigid-flex circuit board solutions visit http://www.epectec.com/flex/.
This webinar is an introduction to Flex and Rigid–Flex Gerber layout design methods and requirements that differ from standard rigid board technology.
Prepare to review some of the unique elements of Flex and Rigid–Flex Gerber layout to ensure functionality and mechanically reliability that meets or exceeds the design requirements.
This document provides a summary of Rashmi Palakkal's career profile including experience, skills, qualifications, projects and achievements. She has over 10 years of experience in FPGA/SOC design and verification. She is currently working as a Lead Engineer at UTC Aerospace Systems and has previously worked at Qualcomm, HCL Technologies and ISRO. Her skills include FPGA implementation, RTL design, verification, and experience with EDA tools and aerospace/automotive development processes. She has led teams and been responsible for pre-silicon and post-silicon validation for multiple chip tape outs.
High Speed & RF Design and Layout: RFI/EMI Considerations (Design Conference ...Analog Devices, Inc.
At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. The design choices begin at the architecture level and extend down to submillimeter placement of traces. There are tried and proven techniques for managing this process. The practical issues of real system design is covered in this session, along with ways to minimize signal degradation in the RF environment.
This document describes PPI's quality standards and certifications for manufacturing printed circuit boards. It lists numerous certifications including ISO 9001, AS9100, FDA registration, and others. It then provides details on PPI's capabilities for various types of circuit board design and manufacturing, including multilayer boards, rigid-flex boards, HDI boards, and IC substrates. It also discusses prototype and quick turn services, as well as conformal coating capabilities.
With the ever changing environment in the medical device market, companies face continuous pressure to make their products smaller, lighter, more portable and of course, less costly.
Epec has over 60 years of experience in working with medical customers and the stringent requirements that go along with medical devices. We will be presenting a webinar that outlines some new technologies and techniques that can help companies achieve all of their product goals.
Please join us for our upcoming product webinar for more information on how Epec can help you with all your medical device needs.
The document provides an overview and summary of Nobuya Okada's educational background, work experience, achievements, skills, and personality. It includes 3 sections: 1) Education/career overview which lists his educational history and work experience. 2) Job details which summarizes his major achievements and roles developing various ASICs and IPs over 21 years of experience. 3) Other profile which outlines his patent/awards, language skills, personality traits, and commitments.
In this Webinar, Epec will review primary design requirements that are best served by the utilization of flex or rigid-flex circuit boards within a given design. Additionally we will address the primary cost drivers that impact the per part cost.
To learn more information on our flex & rigid-flex circuit board solutions visit http://www.epectec.com/flex/.
This webinar is an introduction to Flex and Rigid–Flex Gerber layout design methods and requirements that differ from standard rigid board technology.
Prepare to review some of the unique elements of Flex and Rigid–Flex Gerber layout to ensure functionality and mechanically reliability that meets or exceeds the design requirements.
This document provides a summary of Rashmi Palakkal's career profile including experience, skills, qualifications, projects and achievements. She has over 10 years of experience in FPGA/SOC design and verification. She is currently working as a Lead Engineer at UTC Aerospace Systems and has previously worked at Qualcomm, HCL Technologies and ISRO. Her skills include FPGA implementation, RTL design, verification, and experience with EDA tools and aerospace/automotive development processes. She has led teams and been responsible for pre-silicon and post-silicon validation for multiple chip tape outs.
España tiene un relieve muy montañoso con numerosas cordilleras y sistemas montañosos como resultado de la tectónica de placas. La meseta central es la región más grande y está dividida en dos submesetas por el sistema central, con los ríos Duero y Tajo/Guadiana fluyendo a través de ellas. Las cordilleras Cantábrica, Ibérica, Pirineos y Bética rodean la meseta, y las Islas Baleares y Canarias también tienen relieve montañoso debido a su origen volcánico
El documento resume la Edad Media en Europa, comenzando con las invasiones germánicas que llevaron a la caída del Imperio Romano de Occidente en el siglo V. Los pueblos germánicos como los visigodos, francos y ostrogodos establecieron reinos en las antiguas provincias romanas. Los visigodos fundaron un reino en la península ibérica después de que los romanos les dieran tierras a cambio de defenderlos de otros pueblos. El documento también brinda una breve introducción al is
La Edad Media en la Península Ibérica comenzó con la caída del Imperio Romano y las invasiones de pueblos germánicos como los visigodos, que establecieron un reino en España. En el siglo VIII, los musulmanes conquistaron la Península y fundaron Al-Ándalus, que alcanzó su máximo esplendor bajo el califato de Córdoba. Mientras tanto, los reinos cristianos del norte, como Asturias y León, iniciaron la Reconquista para rec
Frank's Great Outdoors is a family-owned business established in 1945 that supplies customers with equipment and supplies for various outdoor recreational activities like fishing, hunting, kayaking, and camping. Located at 1212 N. Huron Rd. in Linwood, MI, the store offers fishing, ice fishing, waterfowl, kayaks, hunting, outdoor clothing, and marine equipment in addition to camping and cooking gear.
Este documento trata sobre la ética y la tecnología. Explica que la ética estudia el comportamiento humano y clasifica las acciones como correctas o incorrectas. Además, señala que la ética debe guiar el desarrollo y uso de la ciencia y la tecnología. También incluye listas de las principales redes sociales y los artículos relacionados con delitos informáticos.
Patricia Berlioz has over 20 years of experience in the pharmaceutical industry, working in marketing, sales, and product management roles in Australia, Venezuela, and New Zealand. She holds a postgraduate degree in marketing and business from Macquarie University and an undergraduate degree in pharmacology. Her resume lists leadership positions at several major pharmaceutical companies and a track record of exceeding sales targets.
This document discusses different forms of energy including light, sound, kinetic, electrical, and thermal energy. It also describes various renewable and non-renewable energy sources. Renewable sources include solar, wind, water, biomass, and geothermal energy. Non-renewable sources discussed are fossil fuels like coal and oil. The document also briefly touches on electricity, magnetism, and nuclear power.
Este documento resume las principales diferencias entre la didáctica tradicional, contemporánea y activa. Describe los roles del docente y el estudiante, así como los autores clave de cada enfoque. Además, clasifica las didácticas contemporáneas de acuerdo a qué y para qué enseñar, el rol del maestro, del estudiante y los recursos utilizados.
This document describes Dr. Jacob Habgood's research into evaluating game-based learning using a case study of his game Zombie Division. It discusses four designs of his classroom research studying the game, comparing intrinsic and extrinsic approaches. Design 4 found that an intrinsic group using teacher-led reflection had larger learning gains and gains that persisted longer according to delayed post-testing. The document also discusses the practical challenges of conducting educational game research in real classrooms.
La Unión Europea ha acordado un embargo petrolero contra Rusia en respuesta a la invasión de Ucrania. El embargo prohibirá la mayoría de las importaciones de petróleo ruso a la UE y se implementará de manera gradual durante los próximos seis meses. El embargo forma parte de un sexto paquete de sanciones de la UE contra Rusia destinado a aumentar la presión económica sobre el gobierno de Putin.
The document describes the differences between two pictures in each of two sections. In the first section, there are six differences between the pictures including the number of mushrooms, presence of a cat, visibility of the moon, number of birds, amount of grass, and a seam on a girl's shoulder. The second section lists six additional differences between the two pictures such as the presence of a monster in a lake, flowers on a tree, a drawing in the moon, decorations on a fairy's dress, number of branches on a tree, and presence of birds.
The 2012 transition from dfm to pdfd leor nevo-intelchiportal
The document discusses the transition from design for manufacturing (DFM) to physical design for debug (PDFD). PDFD aims to provide design hooks to enable improved debugging of very small integrated circuits. It covers various PDFD capabilities like bonus logic, probe points, and navigation features. PDFD allows bugs to be root caused and validated much faster than traditional mask set approaches. This helps reduce time-to-market and costs for developing integrated circuits.
AMD Chiplet Architecture for High-Performance Server and Desktop ProductsAMD
This document discusses AMD's chiplet architecture for high-performance server and desktop processors. Key points include:
- AMD partitions the system-on-a-chip design, using 7nm technology for CPU cores while leaving I/O interfaces in older process nodes. This improves performance and lowers costs.
- CPU dies ("chiplets") are connected using high-speed SerDes links both on-package and between dies. This allows for more chiplets and cores than traditional monolithic designs.
- Innovations in packaging, power distribution, and operating system scheduling were required to enable the multi-chiplet design and improve performance.
Anuradha is a senior specialist seeking a place and route engineer position. She has over 12 years of experience in physical design including floorplanning, placement, routing, and parasitic extraction. She is proficient with Cadence SOC Encounter for 90nm design and has worked on projects such as a DTMF core and RISC processor from RTL to GDSII. Anuradha is looking to leverage her skills and experience in physical design.
This document discusses surround gate MOSFETs as an approach to reduce short channel effects in transistors. It begins with an overview of MOSFET operation and Moore's Law. It then discusses the motivation to find alternatives to planar transistors as scaling limits are approached. Short channel effects in bulk MOSFETs are introduced as a major barrier to scaling. The document reviews SOI and multi-gate transistor technologies, such as double gate, tri-gate, and gate-all-around designs, as ways to better control the channel and reduce short channel effects. A new dual-material surround gate structure is proposed and its potential to further suppress short channel effects through gate material engineering is explained. Two-dimensional modeling of the new structure
DesignCon 2019 112-Gbps Electrical Interfaces: An OIF Update on CEI-112GLeah Wilkinson
DesignCon 2019
112-Gbps Electrical Interfaces: An OIF Update on CEI-112G
Brian Holden, Kandou Bus
Cathy Liu, Broadcom
Steve Sekel, Keysight
Nathan Tracy, TE Connectivity
A class to introduce students to designing Printed Circuit Boards (PCBs) using the Eagle software. Reflow soldering with stencil and solder paste will also be covered. This class was originally held by me at One Maker Group.
The lesson should take approximately 6 hours to complete.
The example designs used in this class can be found in the repo here. https://github.com/yeokm1/intro-to-pcb-design-eagle
España tiene un relieve muy montañoso con numerosas cordilleras y sistemas montañosos como resultado de la tectónica de placas. La meseta central es la región más grande y está dividida en dos submesetas por el sistema central, con los ríos Duero y Tajo/Guadiana fluyendo a través de ellas. Las cordilleras Cantábrica, Ibérica, Pirineos y Bética rodean la meseta, y las Islas Baleares y Canarias también tienen relieve montañoso debido a su origen volcánico
El documento resume la Edad Media en Europa, comenzando con las invasiones germánicas que llevaron a la caída del Imperio Romano de Occidente en el siglo V. Los pueblos germánicos como los visigodos, francos y ostrogodos establecieron reinos en las antiguas provincias romanas. Los visigodos fundaron un reino en la península ibérica después de que los romanos les dieran tierras a cambio de defenderlos de otros pueblos. El documento también brinda una breve introducción al is
La Edad Media en la Península Ibérica comenzó con la caída del Imperio Romano y las invasiones de pueblos germánicos como los visigodos, que establecieron un reino en España. En el siglo VIII, los musulmanes conquistaron la Península y fundaron Al-Ándalus, que alcanzó su máximo esplendor bajo el califato de Córdoba. Mientras tanto, los reinos cristianos del norte, como Asturias y León, iniciaron la Reconquista para rec
Frank's Great Outdoors is a family-owned business established in 1945 that supplies customers with equipment and supplies for various outdoor recreational activities like fishing, hunting, kayaking, and camping. Located at 1212 N. Huron Rd. in Linwood, MI, the store offers fishing, ice fishing, waterfowl, kayaks, hunting, outdoor clothing, and marine equipment in addition to camping and cooking gear.
Este documento trata sobre la ética y la tecnología. Explica que la ética estudia el comportamiento humano y clasifica las acciones como correctas o incorrectas. Además, señala que la ética debe guiar el desarrollo y uso de la ciencia y la tecnología. También incluye listas de las principales redes sociales y los artículos relacionados con delitos informáticos.
Patricia Berlioz has over 20 years of experience in the pharmaceutical industry, working in marketing, sales, and product management roles in Australia, Venezuela, and New Zealand. She holds a postgraduate degree in marketing and business from Macquarie University and an undergraduate degree in pharmacology. Her resume lists leadership positions at several major pharmaceutical companies and a track record of exceeding sales targets.
This document discusses different forms of energy including light, sound, kinetic, electrical, and thermal energy. It also describes various renewable and non-renewable energy sources. Renewable sources include solar, wind, water, biomass, and geothermal energy. Non-renewable sources discussed are fossil fuels like coal and oil. The document also briefly touches on electricity, magnetism, and nuclear power.
Este documento resume las principales diferencias entre la didáctica tradicional, contemporánea y activa. Describe los roles del docente y el estudiante, así como los autores clave de cada enfoque. Además, clasifica las didácticas contemporáneas de acuerdo a qué y para qué enseñar, el rol del maestro, del estudiante y los recursos utilizados.
This document describes Dr. Jacob Habgood's research into evaluating game-based learning using a case study of his game Zombie Division. It discusses four designs of his classroom research studying the game, comparing intrinsic and extrinsic approaches. Design 4 found that an intrinsic group using teacher-led reflection had larger learning gains and gains that persisted longer according to delayed post-testing. The document also discusses the practical challenges of conducting educational game research in real classrooms.
La Unión Europea ha acordado un embargo petrolero contra Rusia en respuesta a la invasión de Ucrania. El embargo prohibirá la mayoría de las importaciones de petróleo ruso a la UE y se implementará de manera gradual durante los próximos seis meses. El embargo forma parte de un sexto paquete de sanciones de la UE contra Rusia destinado a aumentar la presión económica sobre el gobierno de Putin.
The document describes the differences between two pictures in each of two sections. In the first section, there are six differences between the pictures including the number of mushrooms, presence of a cat, visibility of the moon, number of birds, amount of grass, and a seam on a girl's shoulder. The second section lists six additional differences between the two pictures such as the presence of a monster in a lake, flowers on a tree, a drawing in the moon, decorations on a fairy's dress, number of branches on a tree, and presence of birds.
The 2012 transition from dfm to pdfd leor nevo-intelchiportal
The document discusses the transition from design for manufacturing (DFM) to physical design for debug (PDFD). PDFD aims to provide design hooks to enable improved debugging of very small integrated circuits. It covers various PDFD capabilities like bonus logic, probe points, and navigation features. PDFD allows bugs to be root caused and validated much faster than traditional mask set approaches. This helps reduce time-to-market and costs for developing integrated circuits.
AMD Chiplet Architecture for High-Performance Server and Desktop ProductsAMD
This document discusses AMD's chiplet architecture for high-performance server and desktop processors. Key points include:
- AMD partitions the system-on-a-chip design, using 7nm technology for CPU cores while leaving I/O interfaces in older process nodes. This improves performance and lowers costs.
- CPU dies ("chiplets") are connected using high-speed SerDes links both on-package and between dies. This allows for more chiplets and cores than traditional monolithic designs.
- Innovations in packaging, power distribution, and operating system scheduling were required to enable the multi-chiplet design and improve performance.
Anuradha is a senior specialist seeking a place and route engineer position. She has over 12 years of experience in physical design including floorplanning, placement, routing, and parasitic extraction. She is proficient with Cadence SOC Encounter for 90nm design and has worked on projects such as a DTMF core and RISC processor from RTL to GDSII. Anuradha is looking to leverage her skills and experience in physical design.
This document discusses surround gate MOSFETs as an approach to reduce short channel effects in transistors. It begins with an overview of MOSFET operation and Moore's Law. It then discusses the motivation to find alternatives to planar transistors as scaling limits are approached. Short channel effects in bulk MOSFETs are introduced as a major barrier to scaling. The document reviews SOI and multi-gate transistor technologies, such as double gate, tri-gate, and gate-all-around designs, as ways to better control the channel and reduce short channel effects. A new dual-material surround gate structure is proposed and its potential to further suppress short channel effects through gate material engineering is explained. Two-dimensional modeling of the new structure
DesignCon 2019 112-Gbps Electrical Interfaces: An OIF Update on CEI-112GLeah Wilkinson
DesignCon 2019
112-Gbps Electrical Interfaces: An OIF Update on CEI-112G
Brian Holden, Kandou Bus
Cathy Liu, Broadcom
Steve Sekel, Keysight
Nathan Tracy, TE Connectivity
A class to introduce students to designing Printed Circuit Boards (PCBs) using the Eagle software. Reflow soldering with stencil and solder paste will also be covered. This class was originally held by me at One Maker Group.
The lesson should take approximately 6 hours to complete.
The example designs used in this class can be found in the repo here. https://github.com/yeokm1/intro-to-pcb-design-eagle
This document summarizes the development of high-speed cable technologies at ComLSI between 2005-2011. It describes early work on 30m HDMI cables including chip and cable modeling. Later work included developing silicon IP for cable transmitters and receivers, testing custom flat pair cables, and exploring opportunities in the growing HDMI cable market. Preliminary findings indicated active cable technologies could enable longer lengths and higher data rates to support emerging display standards.
The document provides tips for doing well in VLSI design such as attending classes regularly, working independently on assignments, studying effectively in groups, asking questions, and not cheating on exams. It also discusses various steps in the VLSI design flow including front-end design, back-end design, and considerations for power, timing, and area. Students are encouraged to study thoroughly from textbooks and notes to learn rather than just studying for exams.
Implementing the latest embedded component technology from concept-to-manufac...Zuken
This document discusses implementing embedded components in printed circuit boards from concept to manufacturing. It begins with an overview of embedded component technologies and their advantages like increased density and performance. Common challenges are then addressed such as meeting tolerance requirements for formed components and impact on thermal behavior. The document emphasizes the importance of considering manufacturability early in the design process and working closely with manufacturers to define dedicated design rules. It concludes that a true 3D design approach is necessary to effectively implement embedded component technologies.
SiFive SoC IP for HPC, AI and NetworkingAijaz Qaisar
SiFive offers several high-speed interface IP cores including:
- HBM IP up to 3.2Gbps for applications requiring high bandwidth and density like HPC and AI.
- Interlaken IP up to 1.2Tbps for chip-to-chip connectivity in applications such as networking and data centers.
- A new D2D PHY and controller IP for connecting dies through an interposer or organic substrate at speeds up to 6Gbps for applications such as AI and HPC.
- Ethernet MAC and PCS IP supporting speeds from 10G to 400G.
- USB controller and PHY IP from USB 1.1 to USB 3.2 for device and host connectivity.
This document discusses printed circuit boards (PCBs). It provides an introduction and overview of what a PCB is, the need for PCBs, types of PCBs including general, trace, single layer and double layer, and the design process for trace PCBs. It also outlines some advantages like lower costs for mass production and reduced wiring, and disadvantages such as difficulty repairing or redesigning a PCB. Finally, it provides some examples of PCB applications.
M-Solv is a company that designs and sells manufacturing equipment combining high-precision motion control with laser patterning, inkjet printing, and spray deposition technologies. They presented on using these technologies for large-area electronics manufacturing. Specifically, they discussed using inkjet printing and laser processing to digitally manufacture capacitive touch sensors and for a new "one step interconnect" process for thin-film photovoltaics that deposits all layers and connections in a single pass, reducing costs. Funding from Innovate UK and the EU is acknowledged.
This document provides an overview of VLSI design for a course. It discusses topics including CMOS transistors and logic gates, VLSI levels of abstraction, the VLSI design process, design styles like full custom and ASIC, and trends like Moore's Law. The roadmap outlines topics to be covered like CMOS processing, combinational and sequential circuit design, and a design project to complete a chip. Course objectives are listed relating to VLSI analysis, layout design, and system design skills.
This document provides an overview of PCB designing basics and tools. It defines a PCB as a printed circuit board that physically supports and wires surface-mounted and through-hole components using a FR-4 panel with copper foil laminated on one or both sides. The basic steps in PCB design are: 1) schematic capture, 2) component placement, and 3) routing and exporting output files in Gerber or ODB format. Popular PCB design tools mentioned include Cadence Allegro, Mentor Graphics PADS, Altium PCB Designer, and Eagle PCB Design.
The I2C (Inter-Integrated Circuit) Bus is a two-wire, low to medium speed, communication bus (a path for electronic signals) developed by Philips Semiconductors in the early 1980s. I2C was created to reduce the manufacturing costs of electronic products.
RECENT DEVELOPMENTS IN LED MANUFACTURING 2016 Presentation by Santosh KUMAR o...Yole Developpement
INTRODUCTION TO YOLE DÉVELOPPEMENT AND LED ACTIVITIES
•LED MARKET OVERVIEW
•RECENT DEVELOPMENTS IN LED MANUFACTURING
•2015 STATUs OF THE LED INDUSTRY (AND FUTURE TRENDS)
•CONCLUSION
•APPENDIX-DETAILLED PRESENTATION OF YOLE DEVELOPPEMENT AND LED ACTIVITIES
Roll-to-Roll ALD Coatings for Battery Cell Interfaces at Production ScaleBeneq
ALD/AVS 2022
Presented by D.Sc. Andrew Cook
ALD is an enabling technology for future batteries. ALD technology introduction has been hindered by lack of production scale equipment, but now Beneq R2R ALD technology offers a straightforward scale-up path to mass-production. Beneq has a long experience with R2R ALD on other application areas, and is now applying that know-how to offer R2R ALD solutions for battery manufacturing.
Designing, Fabricating, and Building an Electronic BadgeJim Apger
The process of building your first Printed Circuit Board (PCB) has never been easier, inexpensive, and faster than it is right now. We will walk through a recent project from concept to final product where I was tasked with building an electronic badge for a user conference. There are many choices for free and easy to use Integrated Development Environments (IDE) for programming microcontrollers. There are multiple CAD packages for designing your circuits and laying out the PCB. The cost and turnaround times for having beautiful PCBs and it's associated components show up at your door are hard to believe.
Anyone interested in cranking out your first PCB, programming microcontrollers, or even discussing high-level techniques (reflow/iron) for soldering surface mount devices (SMD) to your PCB will walk away well prepared to start or extend your journey as a maker.
Similar to The 2012 transition from DFM to PDFD ChipEx2012LeorNevoRev 08new (20)
Designing, Fabricating, and Building an Electronic Badge
The 2012 transition from DFM to PDFD ChipEx2012LeorNevoRev 08new
1. May 2, 2012 1
May 2, 2012
Leor Nevo – Intel PE
Courtesy of Intel mates: John Giacobbe
Rick Livengood, Donna Medeiros
Rev 08
The 2012 transition
from
DFM to PDFD
DESIGN FOR (PHYSICAL) DEBUG FOR SILICON MICROSURGERY
AND PROBING OF FLIP-CHIP PACKAGED INTEGRATED CIRCUITS
2. May 2, 2012 2
Outline
• ACRONYMS (alphabetically)
• From DFM to PDFD - Transition motivation
• PDFD capabilities overview
• PDFD scope & flow
• Flip-chip mechanical preparation and navigation
• Bonus combinational and sequential cells
• PDFD in Clock Elements
• Insertion, placement and automation
• Summary & Conclusions
PDFD - Leor Nevo, Intel
3. May 2, 2012 3
ACRONYMS (alphabetically(
Al Aluminums
Cu Copper
CAD Computer Aided Design
CNC Computer Numerical Control
DFD Design For Debug
DFM Design for Manufacture
DFT Design For Test
DRC Design Rule Checker
ECO’s Engineering Change Order
EDA Electronic Design Automation
FAB Fabrication Plant
FIB Focused Ion Beam
LVP Laser Voltage Probe
HVM High Volume Manufacturing
HW HardWare
IC Integrated Circuits
IR Infra Red.
PDFD Physical Design For Debug
PE Principal Engineer
TPT Throughput Time
RC Resistance & Capacitance
SW SoftWare
VLSI Very Large Scale Integrated
4. May 2, 2012 4
Transition Motivation
PDFD - Leor Nevo, Intel
• DFM – we all got used talking about DFM.. For years..
Taking care for high Yield, reduced variation by optimized density, etc.
• While DFM mostly moved to become a hard DRC (~> 1000)
–HVM Fabs can’t count on designers “good will” (High Volume manufacturing)
–They have moved most of the DFM guidelines into strict rules !!
• We assume that the VLSI design timeline is quite predictable
–But the silicon debug for sub-micron becomes a big challenge..
–The Micro-surgery HW has difficulty in following Moore’s law – The
relevant HW can not keep scaling every 2 years !
Conclusion:
PDFD provides hooks in the design enabling analysis of the
deep sub-micron IC beyond DFT & system debugging.
5. May 2, 2012 5
Overview
• What is PDFD?
Design hooks placed in layout to enable optimized access to nodes
during silicon debug: FIB probe access, backside circuit edit, probing.
PDFD Feature types include:
Bonus/happy devices,
probe points,
debug tool navigation features,
FIB cut / Connect cells.
• PDFD provides critical bug research during the debug
phase of a VLSI product for faster time-to-market.
Features designed to add capability or to improve productivity.
Bugs can be root caused and validated in a few days compared to weeks or
months required for a new mask set.
Reduces the number of steppings/masks required to certify for HVM.
M1
Poly
B C
6. May 2, 2012 6
PDFD Scope
• PDFD provides back side entries into the design to
enhance and enable analysis of Integrated Circuits in a
more reasonable time frame.
• This paper will cover design automation/cad SW
solutions and real life technical proposal to enable:
Smooth & accurate Backside Navigation (flip-chip)
Pre-placed Enhanced Probe-ability (cut/connect)
Enhanced Silicon Microsurgery (able to Trim, Cut, connect by-
pass using external low-res wires).
Fibable and Spare Logic Gate for FIB or design ECO’s to be
tested on silicon before reproducing on next design step/retrofit.
7. May 2, 2012 7
Flip-Chip Substrate
Chip A Chip BCaps Caps
Lands
Global thinning of Silicon Substrate:
8. May 2, 2012 8
Flip-Chip Substrate
Chip ACaps Caps
Lands
Chip B first thinned down from 720m to < 200m
using Mechanical Polishing or CNC Milling
Chip B
Global thinning of Silicon Substrate
Reminder : If we will go too
deep – we will start impact the
devices functionality too…
9. May 2, 2012 9
Trench (Top View(
Silicon
Substrate
Fine
Trench Etch Step
Trench Etch Step
Trenching Process
Silicon
Substrate
SiCl4
Cl2
Argon Ion
Laser
Scanning
Mirrors
Cl2
SiCl4
Physical Debug Overview: example only
Laser Chemical Etcher
10/05/15
10. May 2, 2012 10
The big Fiducials provide navigation
points for FIB (for circuit edits(
The more spreading- the more
accurate hit point.
Don't forget – we are drilling from the
back with eyes like blind folded.
High density of Fiducials improve beam placement accuracy < 100nm
Design For Debug (Flip-Chip Navigation Fiducial(
Die
11. May 2, 2012 11
Navigation Features
• The fiducial alignment points are the most utilized PDFD
features as they are used on every edit.
– The larger cell referred to as a global fiducial is placed with a 5-10mm
pitch and provides the 1st level of navigation..
– The smaller local fiducial has a much higher pitch typically around 70u
and is used to achieve sub 100nm accuracy.
• Both have an array of contacts and diffusion that are exposed
in the FIB and locked to CAD database of the chip
Global
Local
EDIT
AREA
12. May 2, 2012 12
Discover bug
through
production,
debug or
system level
test
Generate
or
customize
specific
pattern to
highlight
bug
Isolate bug
using DFT to
functional
area or clk
region
Navigate
Accurately &
Root cause bug
using probe
and design
data/tools
Confirm fix by
performing FIB
edit or rely on
re-simulation
Implement Fix
in layout and
generate new
mask set
PDFD flow overview
Silicon
arrived
13. May 2, 2012 13
Circuit Edit Geometry and RC Challenges
• The device scaling and layout efficiency improvements have
reduced the physical debug tools ability to access
transistors and metal signals:
– 65nm to 32nm and below= meaningful reduction in white space.
– This drives the FIB which has not been able to support the Nano.
– Probe tools have been able to scale but at reduced productivity.
– This limit in technology scaling has resulted in a greater need for
features to be placed in silicon to enable access (i.e., PDFD(.
130nm
Gate
FIB Box
90nm
65nm
45nm
32nm
M1
Poly
Diffusion
M1
S/D
130nmM1
S/D
14. May 2, 2012 14
FIB SiO2
Circuit Edit Geometry and RC Challenges
M1
M2
Gate
V1
Diff
Contacts
Si
FIB Line
STR
FIB Via
Demo
• PDFD features provide guaranteed access to critical
signals on the 2-3 lowest metals.
– Excellent correlation of FIB wire resistance: same ballpark.
– Shown here on the left is a metal 1 PDFD connection point and
on the right is an opportunistic metal 1.
15. May 2, 2012 15
PDFD Building Blocks
• Basic building block features
are designed to meet FIB
rules (Focused Iron Beam)
The features are created as cells
that can get auto spread by CAD.
• The Metal 1 connection pad
provides safe access to
signals
Optimized to keep the FIB via
resistance close to real via
resistance.
Cell area driven to min required –
mostly meet projects cells.
[A] - Metal 1 area maximized to
decrease contact resistance.
M1
Poly
B C
Probepoint
M1 Cut option Poly cut option
A
• Cut cells provide guaranteed
access to target signals.
[B] Metal 1 version typically used for
active signals (not impact timing(
[C] Poly cut cell introduced when metal
signals migrated from Al to Cu
16. May 2, 2012 1616
Design For Debug (Node Access Points(
Auto placement tool can
first place FIB (edit) node
access points. (Focused Iron Beam)
Consider auto route in
upper metal??
Auto placement tool follow
up with placement of LVP
access points.(Laser Voltage Probe)
Layout showing Metal lines
without PDFD coverage
17. May 2, 2012 17
Design For Debug (Spare Logic Gates)
o Designed in FIB Cut
Points
Diff
Diff
Spare Logic Gate
(3 input device)
o Designed in FIB
Connection Points
FIB-able Bonus Logic
18. May 2, 2012 18
Bonus Combinational and
Sequential Cells• Bonus logic and sequential
elements are added to a
design to validate functions
and speed path bugs.
– Typical cells include NAND,
NOR, Buffer, latch, and Flop.
– They can be used in dash.
• Chose cell from a standard
library that has the ability to
drive FIB metal ~100-200um.
– The cell is enlarged so that
building block cut & connect
cells can be inserted.
– Input tied to ground.
– output left floating.
19. May 2, 2012 19
Bonus Combinational and Sequential Cells
• In the below example Signal-B is driving a buffer but now should get the
NAND of Signal-A and Signal-B.
• The FIB connects Signal-A and Signal-B which are then routed using FIB
metal to the inputs of a bonus NAND.
– The output of the NAND is connected back to Signal-B before the input to the next stage.
• Once the routing and connecting are done the FIB will cut Signal-B as
shown by the “X” and the FIB CUT cells at the NAND’s input.
20. May 2, 2012 20
PDFD In Clock Elements
• The ability to alter the timing of clocks is one of the main
activities performed during speed path debug.
On current generation processes it has become essential to design PDFD
features and accessibility into the clock elements themselves.
• To provide FIB access in such small geometries clock
elements are designed with increased spacing's.
In this case a multi legged clock inverter can be trimmed successfully without
damaging the unrelated adjacent device (Trim= ability to reduce device/driver
size = modify the strength) ).
For optical probe accessing the separation helps minimize cross talk.
21. May 2, 2012 21
PDFD In Clock Elements
• A second type of PDFD feature designed into clocks are
mechanical probe points/FIB access cells.
o A building block with connect cells is placed in free space.
o The connection point allows for a FIB load capacitor to be
connected thus delaying the signal.
o It allows the output to be routed to another circuit using FIB.
o Since density rules might require fills in empty areas for DFM – why
not use it for PDFD?
M1
Poly
Diffusion
M1 FIB
Connect
Large Clock inverter with Offset Diffusion
22. May 2, 2012 22
Insertion and Placement Methodologies
• Historically each functional block owner has had to manually insert PDFD
features resulting in wasted effort and inconsistent implementation.
Some alternate options would be:
integrate features directly into cells from the common lib.
Another method : use of automated scripts and customized flows.
–Can be developed by central CAD team into design flows
–An insertion example is shown here where a script pre-placed bonus
combinational and sequential cells as well as navigation cells into a block prior
to the synthesis flow.
–Flow customized to meet individual product’s needs for cell types, strength
and pitches. For example: A product that utilizes proven design may decide to
have larger pitches then a design with untested logic and verified circuits.
• The bonus cell pitch is also determined by FIB
routing technology and RC impact.
• The pitch for the fiducial [+] is based on FIB labs
& navigation equipment accuracy.
23. May 2, 2012 23
PDFD Utilization for Product Stepping's
• The production of a VLSI DIE might require multiple validation loops..
– So while DFM helps long term and HVM yield – current business need is for
development and implementation of PDFD so that some of the below scenarios can
be avoided.
For e.g.
$ A full stepping requires a complete set of masks- IMPACTs TTM, TPT & Cost. (Time To Money)
$ Products use dash or sub stepping's which requires only few new backend masks = potential saving
month's / weeks of time – IMPACTs TTM, TPT & Cost. (Throughput Time)
$ This reduces time to market as product can be held in the FAB at a specific layer until the new backend
masks are generated – IMPACTS TTM.
$ DFM : For simplistic timing or electrical issues a dash stepping typically can be performed at metal
layers only since they do not require additional transistors. IMPACTS TTM, TPT & Cost.
• The implementation of strategically placed
PDFD cells allow these type of logic or
complex bugs to be fixed in a dash. Silicon READY for the coming
upper Metals
As Dash/Retrofit.
24. May 2, 2012 24
Wait.. Did we miss something?
• With future Deep sub-micron design < 32nm –
– How can one navigate to the exact location?
– Is the ability to navigate to +/- 1 u good enough?
– While metals width is less than 100nm: 1u means I will get to few
signals but not to the specific one … not good.
• So we: – innovated Global fiducials to get to the 1u Local
Fiducials so as to facilitate reaching the exact signal..
– Even if it is deep inside the silicon. We have lots of challenges to get
to the upper metals… across M1-M2 to M3-M4 .. Deeper?
– Assuming design will budget the area for the Global fiducials..
(~10*10u) and for the local fiducials 1-2x basic cells size, CAD/SW
automation will be needed to place the fiducials.
• After all – it require 3 notable spots to find a new location
PDFD - Leor Nevo, Intel Corporation
25. May 2, 2012 25
Flip-Chip Substrate
Chip ACaps CapsChip B
First Conclusion
The transition from DFM to PDFD is due:
While DFM ensures HVM a clean design is of equal importance.
PDFD implementation in next generations VLSI products is a critical part of
the overall DFD concept that must be employed by VLSI Product teams.
Placing design access hooks into the silicon and mainly on critical nodes
and cell types results in higher productivity and capability for physical
debug tools which further enables faster TPT from 1st silicon to product.
The utilization of PDFD results in fewer stepping's or partials layers
retrofits which translates to faster TTM. Having each new step already
validated on silicon has a big upside potential to save millions of $$$
26. May 2, 2012 26
Second Conclusion
Optimal coverage of PDFD will become even more critical as
the semiconductor industry moves into the 45nm,32nm and
below or else “no bug” guarantee is questionable.
It is clear that improvements are needed in scaling circuit
edit equipment's and material properties! Is that enough?
A comprehensive PDFD strategy is required on future
technologies if the industry is to continue to realize the benefits
of performing in-silicon validation of speed, yield & logic bugs.
SO while old traditional DFM guides have became strict
rules - a better usage of the white space would be to add
use DFM fillers for DFD – Right ?
This is true for front-side as the same as Flip-chips.
So we see here wide opportunities for:
SW solutions.
HW manufacturer or Start-Ups to leap-ahead into the future.
27. May 2, 2012 27
Q & A
Leor Nevo - Intel DFM-PDFD PE
Thanks.
Leor Nevo, Intel Corporation
28. May 2, 2012 28
References (Back-up(
• There is a very small set of literature outside and projects are
trying to do their best using DFT features to debug by the flip-
chip pins - but it requires more and more area.
• The Design Automation Conference, EDA, test and silicon debug
companies announced the creation of the Design-for-Debug
Consortium to address silicon debug challenges and
collaboratively define the tools needed.
PDFD - Leor Nevo, Intel Corporation
29. May 2, 2012 29
PDFD In Clock Elements
• The ability to alter the timing of clocks is one of the main
activities performed during speed path debug.
– On current generation processes it has become essential to design PDFD features
and accessibility into the clock elements themselves.
• To provide FIB access in such small geometries clk cells
must be designed with extra spacing between transistor’s.
– In this case a multi legged clock inverter can be trimmed successfully without
damaging the unrelated adjacent device.
• For optical probe access the separation helps minimize
cross talk.
Editor's Notes
The outline for my presentation is as follows:
Please fell free to stop me at any time to ask questions or for clarifications.
Your first slide must be the title slide. Your company or university logo may appear on this, and only this slide.
Next, have one slide that states the purpose of the work described in your paper. Describe the big picture of why you did the work, not the detailed technical objectives your work accomplished.
Outline the high points of the presentation you are giving. Don’t include the title, purpose or conclusion in your outline.
After the outline of your talk come the slides that detail your presentation. Most speakers will use between 11 and 21 slides.
Finally, have one or two slides that conclude your talk.
Your first slide must be the title slide. Your company or university logo may appear on this, and only this slide.
Next, have one slide that states the purpose of the work described in your paper. Describe the big picture of why you did the work, not the detailed technical objectives your work accomplished.
Outline the high points of the presentation you are giving. Don’t include the title, purpose or conclusion in your outline.
After the outline of your talk come the slides that detail your presentation. Most speakers will use between 11 and 21 slides.
Finally, have one or two slides that conclude your talk.
Your first slide must be the title slide. Your company or university logo may appear on this, and only this slide.
Next, have one slide that states the purpose of the work described in your paper. Describe the big picture of why you did the work, not the detailed technical objectives your work accomplished.
Outline the high points of the presentation you are giving. Don’t include the title, purpose or conclusion in your outline.
After the outline of your talk come the slides that detail your presentation. Most speakers will use between 11 and 21 slides.
Finally, have one or two slides that conclude your talk.