1. IEEE1149.1 Scan Chain Partitioning
for Test Time Enhancement
Goh Hoe Hin
Northumbria University
hh.goh.523@outlook.com
Abstract— Scan test is one of the major Design-for-Testability
features which provide testability, controllability and
observability of the internal circuitry of an integrated circuit
(IC). Long scan test time has become one of the problems faced
by designers. This paper mainly target on the scan test time
improvement by introducing multiple scan chain architecture as
well as parallel scan mode to relief the single-long scan chain
loading. By splitting the long scan chain into shorter one and
connect each short scan chain with de-multiplexers to provide
controllability to switch between serial and parallel mode. This
structure managed by a modified BILBO to provide flexibility of
scan test modes. DOE performed based on a small combinational
logic circuit sample with only 23 scan cells and test time captured
shows that the parallel in parallel out mode consumed the least
test time, in this DOE it consumed 17S.
Keywords— scan, scan cell, boundary scan, bilbo, test time,
design for test, dft, scan chain, parallel scan
I. INTRODUCTION
When manufacturer designs/produces Integrated Circuit
(IC), besides the main circuitry the manufacturer also
introduce Scan Chains into the circuitry. These scan chains
circuitries do not contribute any effort in the main circuitry
operation and towards customers, none of the application or
device that connected to this IC, will utilize these scan chains.
[1] Scan architecture simplifies the test of VLSI chips by
improving the testability, controllability and observability of
the internal circuitry in the design; by serially shifting in and
out the test pattern and the test response bits through the
Primary Input (PI)/Primary Output (PO). [2] Scan chain is
commonly used to connect shift registers that store the input
and output vectors during production phase testing. All shift
registers in the scan chain are connected as a single path with
both PI and PO.
In the semiconductor / integrated circuit (IC) manufacturing
process flow, Test area consumes most of the time. IC
produced by manufacturer needs to be tested in several
categories and among these categories, scan test has taken up
major part of the overall lead time. Nowadays scan test time
increases dramatically due to the increase of complexity of
integrated circuit design and the component density in most of
the digital VLSI design today. A long scan chain may impact
the test circuitry on chip performance, cost and increase the
test time. [2] It is important to minimize the wire length of
scan chain in order to reduce test time, wiring congestion and
chip area for cost saving in production phase testing.
The main aim for this paper is to shorten the scan chain
wire length to reduce wiring congestion, cost and test time. In
order to minimize the scan test time, several improvements
can be done:
• Multi Scan Chain Architecture
• Simplify scan cell structure
• Parallel Scan Chain Broadcasting Architecture
II. PROJECT SPECIFICATION
Several methods have been proposed to overcome the test
time and test data issue in scan testing. [3] A scan chain data
reduction by using scan chain reordering with combination of
scan chain reordering solution in optimization technique to
minimize the routing area overhead of scan chains and a
specific [3] window based grouping method to reduce
congestion by G. Seok et al. [3] This method does not require
additional DFT logic such as encoding method but can easily
applicable to any scan design. M. Azimipour et al [4]
proposed the basic concept of Circular-scan Architecture [5]
but using a [4] modified Scan Input Selection Unit instead of a
regular decoder in a parallel scan chains broadcasting
architecture, such as the [6] Illinois scan architecture (ILS).
The proposed architecture in this paper is to implement
multiple scan chain proposed in [5] Circularscan to combine
with a modified BILBO to handle the scan cells in order to
provide Parallel Scan modes.
III. CONCEPT
[7] Scan test is part of the DFT technique that used to
provide more testability, controllability and observability for
every component or flip-flop in the integrated circuit (IC).
The scan chains exist in design to ease the manufacturer’s
production, to be more specific, in Class Test. There are 2
types of Test in a normal IC producer factory, i.e. Sort Test
and Class Test. Sort Test happened when the IC is newly
fabricated from wafer to die, before wire bonding or die attach
process happened. This test basically tests the parametric
issues, such as basic I/O, Open/Short, Leakage and etc. After
the die been attached to the substrate (or package), the IC will
be sent for Class Test.
Class Test is more complicated process comparing with
Sort Test as it consists of almost all tests available for the IC,
from simple tests such as VCC Continuity, Thermal, Fuse, to
a more time consuming tests such as Voltage Input Low/High

2. (VIX) and Voltage Output Low/High (VOX), pin to pin
Leakage (Leak Low/High) with very tight lower and upper
limit. Among these tests, the most time consuming tests will
be Memory tests, Built-in Self Test (BIST) as well as Scan
Test.
For Scan Test, basically there are 2 major tests
compulsorily to be executed, the Stuck-at and the Scan Chain.
Apart from the components of the main circuitry (logic gates,
flip-flop and etc.) have stuck-at issue, the scan cell may also
encounter similar problems. Hence, the Scan Test will also
check the scan chain to ensure all scan cells are in good
condition before they can be used to test the components in
the main circuitry.
[7] There are two types of mode in scan test, the functional
and the test mode. [7] The concept is pretty simple, firstly set
the IC into test mode to load the scan chain with the input test
set (Test Pattern). [7] Then put the IC in to functional mode to
observe the primary output. Set the primary input and execute
with one clock cycle. [7] After that, put the IC in test mode
again to observe the scan chain output. By then, start to clock
the scan chain until the end of the test set and observe the scan
output result.
A. Basic Idea
This paper utilizes a basic scan chain circuitry that passes
through 3 combinational logic circuits as shown in Figure 1.
This is the initial design with Serial In / Serial Out scan path
concept. During Test Mode, all input test sets will be loaded
into scan chain. IC will be switched to Functional Mode to
allow output of combinational logic circuits to be loaded to
the scan cells. IC will then switch again to Test Mode to load
the output out from scan output.
Figure 1. Basic Idea of Scan Chain Circuitry
B. Scan Chain Split Method
This paper proposes to split the long scan chain shown in
Figure 1 into shorter scan chains to allow parallel input test
sets loading, as shown in Figure 2. In HDL, when Parallel
Scan mode is chosen, the scan chain will be split with
different length and for shorter scan chains, it will be offset
with 0 to ensure same length for same time loading at scan in.
Refer to Figure 3 for the code.
Figure 2. Proposed Scan Chain Split Method
Figure 3. HDL code for Scan Chain Split
IV. DESIGN METHODOLOGY
A. Modification of BILBO
This paper proposed a modification of standard 2-
mode_pin-BILBO to allow the scan chain works in both
Serial and Parallel modes. The [8] standard BILBO
structure comes with an Exclusive-OR (XOR) gate as
feedback for Linear Feedback Shift Register (LFSR) but
this shift register is not applicable in this project. Thus
minor modification has been done to suit to this project.
The standard BILBO with 2 mode pins carries 4 different
functions. Among these 4 functions, the LFSR has been
removed and replaced with a customized feature which
allows Parallel Scan mode. The change of functions of the
modified BILBO is shown in Table 1. There are 2 changes
made from the standard BILBO structure:
1) LFSR to Reset Mode (b2=1, b1=0)
The LFSR function is not applicable in this
project, thus the Feedback XOR has been removed
and replaced by Logic ‘0’. Note that the MUX2
shown in Figure 4 allow Serial Scan In (s_scan_in)
signal to enter the scan flip-flop (D0) via the
NAND1 and XOR gate, enabled by b2 mode pin.
For Reset Mode, b2 will be set to 1 and the MUX2
in Figure 3.3.4.c above will provide Logic ‘0’

3. signal into the NAND1 gate. The other input of
NAND1 gate is connected to a signal of B2X
(B2X = ~(~b2.b1)). With this, as long as b2 = 1,
B2X = 1. As a result, the output of NAND1 gate
will be fixed to 1. The reason to fix the out of
NAND1 gate to 1 is to ensure the output of the
XOR gate toggles the output from NAND2 gate.
The reason this mode will give a Reset to the scan
output is because mode pin b1 = 0 and hence
output of NAND2 gate is fixed to 1. By toggling
the output of NAND2 gate, the output of XOR
gate will be fixed to 0 (Reset).
2) MISR to Parallel Scan (b2=1, b1=1)
From the above explanation, when mode pin
b2 = 1, the output MUX2 will be the toggle of
output of NAND2 gate. In this mode b1 = 1, thus
the output of NAND2 gate will be the toggle of
input from MUX1. Note that MUX1 enabling
signal is controlled by b1b2, in this case the
MUX1 output will be Parallel Scan In (p_scan_in),
refer to Figure 5.
Table1. BILBO Modes Comparison
Figure 4. LFSR to Reset Mode
Figure 6. Modified Scan Cell Structure
Figure 5. Parallel Scan Configuration in BILBO
B. Scan Cell Structure
With the implementation of modified BILBO to the
scan chain, the scan cell used in this project will be
different from the Standard Scan, refer to the Figure 6.
C. Additional demux for Serial/Parallel Scan
There are 3 de-multiplexers have been added in to the
scan chain, enabled by b2 mode pin. These 3 de-
multiplexers play a role to fan out the scan result of each
combinational logic circuit during Parallel Scan mode,
shown in Figure 7. During Serial Scan Mode, these de-
multiplexers will close the loop of the serial scan chain to
allow input test set (test pattern) to load serially into the
entire scan chain as illustrated in Figure 8.
Figure 7. Demux Role during Parallel Scan
Figure 8. Demux Role during Serial Scan

4. V. EXPERIMENT AND RESULTS
Experiments are performed on the 3 combinational logic
circuits that formed up 23 scan-cell chain. There are 2 types of
DOE performed to ensure both scan result and scan test time
are covered.
A. Scan Result Comparison
Before the scan result can be compared, the expected
output from the combinational logic circuits has been
simulated by SPICE.
 Serial In / Serial Out
This experiment happened during Serial Scan
mode (BILBO b2=0, b1=0). Input test set was
loaded into scan chain serially in and out. Figure
9 showed the comparison of scan out results with
the expected output from SPICE.
 Serial In / Parallel Out
This experiment carried out by loading input test
set serially into scan chain but the scan result was
loaded out via de-multiplexer in parallel. Figure
10 showed the scan out result comparison.
 Parallel In / Serial Out
This experiment carried out with input test set
loaded into scan chain in parallel via de-
multiplexers but the scan output is loaded out
serially. Figure 11 showed the result matching
comparison.
 Parallel In / Parallel Out
This experiment had both scan in and out in
parallel mode. Figure 12 showed the result
matching comparison.
Figure 9. Serial In / Serial Out Scan Result
Figure 10. Serial In / Parallel Out Scan Result
Figure 11. Parallel In / Serial Out Scan Result
Figure 12. Parallel In / Parallel Out Scan Result
B. Scan Test Time Comparison
This experiment was carried out on the simple
combinational logic circuits with a total of 23 scan cells.
 Serial In / Serial Out
This mode consumed the longest time to
complete, a total of 38us for 23-bit input test set
to be loaded and output captured. Refer to Figure
13.
 Serial In / Parallel Out
This mode consumed lesser time because the
output was done in parallel via de-multiplexers.
Time taken 30us for 23-bit input test set to be
loaded and output captured. Refer to Figure 14.
 Parallel In / Serial Out
This mode consumed 24us for 23-bit input test set
to be loaded and output captured, refer to Figure
15.
 Parallel In / Parallel Out
This mode consumed the least time because both
input test set loading and output captured were
done in parallel mode, thus a total of 17us has
been taken to complete a 23-bit input test set.
Refer to Figure 16.
Figure 13. Serial In / Serial Out Test Time

5. Figure 14. Serial In / Parallel Out Test Time
Figure 15. Parallel In / Serial Out Test Time
Figure 16. Parallel In / Parallel Out Test Time
VI. CONCLUSION
This paper focus on scan chain with modified BILBO to
fulfill the Parallel scan test set loading and result capturing.
Based on the DOE results, Parallel In / Parallel Out scan mode
consumed the least test time. Further improvement projects
can be done for test pattern compacting and overlapping to
enhance the overall test cycle time.
ACKNOWLEDGMENT
This work was done under B.Eng E/E (Hons) of
Northumbria University.
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