An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of High-Speed SerDes
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RNM is finding prominence in functional verification signoff, However there is clear modeling gap when it comes to performance simulation of high-speed SerDes. Sometimes the pre-silicon simulation results show passing results with respect to Jitter tolerance (JTOL) specification which may not match the actual silicon validation results. These performance issues manifest due to inaccuracies of model where it may not comprehend the actual circuit behavior. There is no clear methodology to overcome these model gaps for performance simulation signoff. This paper discusses in detail the techniques used to accurately model and verify high-speed SerDes systems for performance simulation.
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An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of High-Speed SerDes
- 1. An Approach to Overcome Modeling Inaccuracies for Performance Simulation Signoff of High-Speed SerDes Aneesh K S, Principal Design Engineer Gaurav Ranjan, Principal Design Engineer Pankaj Singh, Design Engineering Director 1
- 2. Agenda • Introduction • Functionality vs Performance Simulations • Modeling Gaps in High-Speed SerDes • Performance Analysis Using “Capture and Playback” • Existing Methodology vs Proposed Methodology • Benefits of Overcoming Limitations of RNM • Implementation Details of Proposed Methodology – Modeling Frequency-Dependent Circuit Behavior • As a Digital Filter – Created from step response using MATLAB – Created from s-domain transfer function using bilinear transformation • As a Structural Model – Created using electrical-equivalent datatypes © Accellera Systems Initiative 2
- 3. Agenda – Modeling Signal Impairments • Modeling Noises • Modeling Gain Compression • Modeling Nonlinearities • Modeling Jitter • Simulation Results – Equalization and Adaptation Waves – Eye Diagrams and Jitter Tolerance (JTOL) Curves • Results and Conclusion • Next Steps • References • Acknowledgement • Glossary © Accellera Systems Initiative 3
- 4. Agenda • Introduction • Functionality vs Performance Simulations • Modeling Gaps in High-Speed SerDes • Performance Analysis Using “Capture and Playback” • Existing Methodology vs Proposed Methodology • Benefits of Overcoming Limitations of RNM • Implementation Details of Proposed Methodology – Modeling Frequency-Dependent Circuit Behavior • As a Digital Filter – Created from step response using MATLAB – Created from s-domain transfer function using bilinear transformation • As a Structural Model – Created using electrical-equivalent datatypes © Accellera Systems Initiative 4
- 5. Introduction: Modeling Tradeoffs © Accellera Systems Initiative 5 1. AMS simulations using analog and digital solver – SPICE Models • Benefit : Very high accuracy • Limitation : Very long runtime – Verilog A/AMS models • Benefit : High accuracy • Limitation : Long runtime 2. Digital simulations using digital solver – Pure digital or logic models • Benefit : Fastest approach • Limitation : Not capable of transferring real data across boundaries – RNM models (Ref [1] and Ref [2]) • Benefit : Relatively faster Capable of transferring real data across boundaries RNMs are the most effective way to abstract AMS functionality for full chip simulation AMS design Verilog A Verilog Verilog Verilog Verilog Spice D D D D D D Model
- 6. Functionality vs Performance Simulation © Accellera Systems Initiative 6 Focus on verifying digital algorithms Functional simulations Verifies integration of analog and digital Checks adaptation algorithm is functional Signoff : Results as test PASS/FAIL Focus on verifying analog specifications and its impact on system Performance simulations Verifies system performance for various attenuation channels, corners, noises etc. Checks the settled code after adaptation is as expected Signoff: Results as eye diagrams, JTOL curves Modeling Gap RNMs are good for functional verification, but have a clear modeling gap for performance simulations
- 7. Modeling Gaps in High-Speed SerDes © Accellera Systems Initiative 7 Improved RNM modeling techniques to overcome limitations for performance simulations is required • Methodology Gaps: – Modeling channel attenuation and equalizer gain (frequency-dependent) – Modeling signal impairments – Updating verification setup to add jitter in input data stream SerDes block diagram Transmitter Channel Receiver Equalization and DFE adaptation Phase Interpolator Sampler CDR (and de-serializer) Parallel data Serial data Recovered data Recovered clock Edge and data samples Edge and data clocks PLL Serializer EQ/ Driver UVM-e based Testbench SERDES
- 8. Performance Analysis Using “Capture and Playback” © Accellera Systems Initiative 8 Limitations of “capture and playback” forces us go back to pure RNM simulations for performance runs • Capture procedure needs to be repeated for each test pattern, channel, corner etc. (Ref [3]) • One capture run each for every VGA gain code • Difficulties in sampling, retiming and interpolating the captured data
- 9. Existing Methodology vs Proposed Methodology © Accellera Systems Initiative 9 RNM Limitations to model Frequency-dependent behavior and Signal impairments must be addressed No: Attributes Existing Methodology New/ Proposed Methodology Advantages / Disadvantages 1 Functionality checks Logic model runs - Inapt to test algorithms involving feedback paths with signal gain/attenuation etc. (like adaptation) AMS runs - Multiple runs impractical for devices with system frequencies above 5GHz because of high simulation time RNM methodology + Good to test feedback paths and algorithms + Better resemblance to schematics - Difficulties in modeling frequency-dependent circuit behaviors 2 Performance/ JTOL checks (for system frequencies > 5GHz) In-house capture and playback setup - Increased effort for setup creation and longer simulation time - Not suitable for random data stimulus runs RNM methodology + No extra effort for setup creation, RNM setup for functionality checks can be reused + Supports random data stimulus runs - Models need to be as accurate/close to the schematics as possible
- 10. Benefits of Overcoming Limitations of RNM © Accellera Systems Initiative 10 New methodology offers a holistic approach to overcome RNM limitations for functional and performance runs No: Limitations Details Benefits 1 Frequency-Dependent Schematic Behavior Digital filter – using MATLAB (from step response) • Useful to accurately model schematic behavior • Useful when transfer function is not known Digital filter – using bilinear transformation (from transfer function) • Useful for generic model development, especially when schematics is not available Electrical-equivalent nets (from schematics) • Useful to model smaller circuits like simple RC, RLC etc. 2 Signal Impairments Noise Modeling • Useful to model amplifier noises Nonlinearities Modeling • Useful to model nonlinearities of blocks like phase-interpolator Gain Compression Modeling • Useful to model large signal amplifier gain compression Jitter Modeling • Useful to model Input data jitter
- 11. Agenda • Introduction • Functionality vs Performance Simulations • Modeling Gaps in High-Speed SerDes • Performance Analysis Using “Capture and Playback” • Existing Methodology vs Proposed Methodology • Benefits of Overcoming Limitations of RNM • Implementation Details of Proposed Methodology – Modeling Frequency-Dependent Circuit Behavior • As a Digital Filter – Created from step response using MATLAB – Created from s-domain transfer function using Bilinear transformation • As a Structural Model – Created using electrical-equivalent datatypes © Accellera Systems Initiative 11
- 12. 1.1 Modeling Frequency-Dependent Circuit Behavior – Using Digital Filters © Accellera Systems Initiative 12 Key challenge in model development using digital filters is to obtain the filter coefficients • Frequency-dependent circuit behavior is modeled using a digital filter – FIR or IIR Implementing frequency-dependent behavior Wrapper model Instantiation of digital filter model Other functionalities / logic Outputs Inputs
- 13. 1.1.1 Filter Coefficient Generation Using MATLAB © Accellera Systems Initiative 13 Useful to accurately model schematic behavior, when the transfer function is not known, and the circuit size is big • Derives the filter coefficients from step response using MATLAB “stmcb” function • Required number of poles and zeroes can be provided as inputs to function Steps to generate IIR filter coefficients Steps to generate the step response Procedure for model development
- 14. Implementation Details © Accellera Systems Initiative 14 Instantiating the filter in wrapper model Implementing the direct form 1 structure Sample filter coefficients Direct form 1 structure (Ref [4])
- 15. Improved Accuracy of Simulation Results © Accellera Systems Initiative 15 Equalizer output waveforms Output of cascaded RLC channels Frequency response curves
- 16. 1.1.2 Filter Coefficient Generation Using Bilinear Transformation © Accellera Systems Initiative 16 Good for modeling generic channel/equalizer models without strict accuracy requirements, especially aimed at testing digital algorithms and fast bring-up • Filter coefficients are created from s- domain transfer function using bilinear transformation (Ref [5] and Ref 6]) Procedure for model development
- 17. Implementation Details and Simulation Results © Accellera Systems Initiative 17 RLC mode waveforms (Ts=4ps) Model code RLC circuit that was modeled
- 18. 1.2 Modeling Frequency-Dependent Circuit Behavior Using Electrical-Equivalent Datatypes © Accellera Systems Initiative 18 Used for develop structural models that accurately resemble circuits with minimal components like series RLC • Uses IEEE 1800-2012 SystemVerilog concepts of UDT and UDR (Ref [7]) • An electrical-equivalent data type along with a resolution function is used for modeling Model of a series RLC with o/p across R
- 19. Modeling Frequency-Dependent Circuit Behavior Using Electrical-Equivalent Datatypes © Accellera Systems Initiative 19 eestruct UDT - (electrical equivalent res_EE UDR for merging nodes Eenet UDN Using a UDN
- 20. Agenda – Modeling Signal Impairments • Modeling Noises • Modeling Gain Compression • Modeling Nonlinearities • Modeling Jitter • Simulation results – Equalization and Adaptation Waves – Eye Diagrams – Jitter Tolerance (JTOL) Curves • Results and Conclusion • Next Steps • References • Acknowledgement • Glossary © Accellera Systems Initiative 20
- 21. 2. Modeling Signal Impairments © Accellera Systems Initiative 21 No: Attribute Description Need for Modeling Implementation Details Results/Observation 1 Noise Unwanted random disturbances in an electrical signal To capture amplifier/equalizer noises Using $dist_normal (Gaussian) 2 Gain Compression Reduction in gain for large signal input To capture gain compression in equalizers when the digital filter coefficients are generated using AC analysis Using tanh function 3 Nonlinearities Deviation of the output phase curve from the ideal straight line To capture INL of phase-interpolators Nonlinearities are captured as a text file, which is instantiated in the wrapper model 4 Jitter Temporal deviations of a clock edge with respect to its ideal position To capture jitter in input data stream or in PLL clock ➔Sinusoidal DJ is modeled using the 1-cos(x) function ➔RJ is modeled using the $dist_normal
- 22. Automated Flow to Obtain JTOL Curve © Accellera Systems Initiative 22 Select suitable testcase for regression Run regression with the testcase varying jitter amplitude and frequency Post run script to probe regression results Output as CSV file capturing boundary between PASS and FAIL Plot JTOL curve from CSV file
- 23. Agenda – Modeling Signal Impairments • Modeling Noises • Modeling Gain Compression • Modeling Nonlinearities • Modeling Jitter • Simulation Results – Equalization and Adaptation Waves – Eye Diagrams – Jitter Tolerance (JTOL) Curves • Results and Conclusion • Next Steps • References • Acknowledgement • Glossary © Accellera Systems Initiative 23
- 24. Improved Simulation Accuracy with Frequency- Dependent Behavior Modeling © Accellera Systems Initiative 24 Adaptation procedure Equalized waves
- 25. Simulation Results – Accurate Eye Diagrams for High-Speed SerDes © Accellera Systems Initiative 25 Eye diagrams before and after equalization for PCIe 4.0 long channel Eye diagram at the input of sampler for PCIe 3.0 mode using long channel Eye diagram at the input of sampler for 10gkr mode using long channel
- 26. Simulation Results – JTOL Curves © Accellera Systems Initiative 26 • Silicon/simulation JTOL curve should fall above the specification JTOL curve for it to meet the JTOL specification • Not modeling jitter and noises is an optimistic approach and can give a false impression that the device has a better JTOL curve 0.1 1 10 1 10 100 SJ Amplitude (UI) SJ Frequency (MHz) JTOL curve - Silicon vs Simulation data (PCIe Gen4) Spec data Sim_Typ data Silicon FS_corner Silicon SS_corner Silicon Typ_corner
- 27. Results and Conclusion © Accellera Systems Initiative 27 • An issue with schematics, where the equalizer gain was less than expected, was caught in simulations – In this case, the settled gain code after adaption in simulation was far off from the expected one • Modeling signal impairments pushed the JTOL curve down, towards the specification curve, which helped in obtaining a realistic curve rather than an optimistic one • System simulation results using these techniques gave equal to or very close adapted gain codes as expected by analog engineers Proposed improved RNM methodology provides holistic approach to overcome limitations of traditional modeling approaches by modeling frequency- dependent circuit behavior and signal impairments
- 28. Next Steps © Accellera Systems Initiative 28 • Existing models are based on typical corner, models need to be updated to capture information from other corners also • Longer simulation time (around 12 to 48 hours for a single run) with the frequency-dependent circuit behavior modeled, alternate digital filter structures or modeling languages need to be tried to improve the simulation speed
- 29. Agenda – Modeling Signal Impairments • Modeling Noises • Modeling Gain Compression • Modeling Nonlinearities • Modeling Jitter • Simulation Results – Equalization and Adaptation Waves – Eye Diagrams – Jitter Tolerance (JTOL) Curves • Results and Conclusion • Next Steps • References • Acknowledgement • Glossary © Accellera Systems Initiative 29
- 30. References © Accellera Systems Initiative 30 [1] “Solutions for Mixed-Signal SoC Verification Using Real Number Models” https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/solutions/mixed-signal- verification-wp.pdf [2] DVCON 2015 paper “PHY IP Verification – Are Conventional Digital DV Techniques Sufficient?” Somasunder Sreenath [3] 16th International SOC Conference Paper “Overcoming Challenges of Verifying Complex High Speed Mixed Signal Designs” Vinayak Hegde, Pankaj Singh, Odom Serey [4] https://en.wikipedia.org/wiki/Infinite_impulse_response [5] Jess Chen, Michael Henrie, Monte F. Mar Ph.D. and Mladen Nizic, “Mixed Signal Methodology Guide” (Chapter 3, AMS behavioral Modeling, Ronald S. Vogelsong Ph.D.) [6] https://en.wikipedia.org/wiki/Bilinear_transform [7] Cadence Rapid Adoption Kit, “Using EEnet to Perform Electrical-Equivalent Modeling in SystemVerilog”, August 2017 [8] https://en.wikipedia.org/wiki/Gaussian_function [9] https://en.wikipedia.org/wiki/Normal_distribution
- 31. References © Accellera Systems Initiative 31 [10] Lecture 9: Intercept Point, Gain Compression and Blocking, Prof. Ali M. Niknejad, University of California, Berkley [11] Modeling and Verification of High-Speed Wired Links with Verilog-AMS; Ming-ta Hsieh, Gerald E. Sobelman [12] DVCON 2014 paper “SERDES Rx CDR Verification Using Jitter, Spread-Spectrum Clocking (SSC) Stimulus” Somasunder Sreenath, Raghuram Kolipaka, Chirag Shah, Parag Lonkar
- 32. Acknowledgement © Accellera Systems Initiative 32 • Chetan Kumar G • Potlapalli Santhosh • Arumugan A • Hardik Doshi
- 33. Glossary © Accellera Systems Initiative 33 No: Notation Description 1 AMS Analog Mixed Signal 2 CDR Clock and Data Recovery 3 CTLE Continuous Time Linear Equalizer 4 DFE Decision Feedback Equalizer 5 DJ Deterministic Jitter 6 DNL Differential Nonlinearity 7 EQ Equalizer 8 FE Front End 9 FIR Finite Impulse Response 10 IIR Infinite Impulse Response 11 INL Integral Nonlinearity 12 JTOL Jitter Tolerance 13 PI Phase Interpolator 14 PLL Phase-Locked Loop 15 RJ Random Jitter
- 34. Glossary © Accellera Systems Initiative 34 No: Notation Description 16 RMS Root Mean Square 17 RNM Real Number Modeling 18 RTL Register Transfer Level 19 SerDes Serializer/De-Serializer 20 SRIS Separate Reference clock with Independent Spread 21 SSC Spread Spectrum Clocking 22 SV SystemVerilog 23 TS Training Sequence 24 UDN User Defined Nettype 25 UDR User Defined Resolution 26 UDT User Defined Type 27 UI Unit Interval 28 UVM Universal Verification Methodology 29 VGA Variable Gain Amplifier 30 WREAL Wire Real
- 35. © Accellera Systems Initiative 35 Questions?