IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
PERFORMANCE FACTORS OF CLOUD COMPUTING DATA CENTERS USING [(M/G/1) : (∞/GDMOD...ijgca
The ever-increasing status of the cloud computing hypothesis and the budding concept of federated cloud computing have enthused research efforts towards intellectual cloud service selection aimed at developing techniques for enabling the cloud users to gain maximum benefit from cloud computing by selecting services which provide optimal performance at lowest possible cost. Cloud computing is a novel paradigm for the provision of computing infrastructure, which aims to shift the location of the computing infrastructure to the network in order to reduce the maintenance costs of hardware and software resources. Cloud computing systems vitally provide access to large pools of resources. Resources provided by cloud computing systems hide a great deal of services from the user through virtualization. In this paper, the cloud data center is modelled as queuing system with a single task arrivals and a task request buffer of infinite capacity.
Optimized Layout Design of Priority Encoder using 65nm TechnologyIJEEE
This paper provides comparative performance analysis of power and area of 4 bit priority encoder using 65nm technology.Two priority encoder approaches are presented, one with full automatic and the other with semicustom. The main objective is to compare full automatic and semicustomdesigned layout on the basis of two parameters which is power and area. The automatic design circuit simulation has been done on logic editor and layout created from Verilog file which is simulated. The semicustom layout is created manually and simulated. Creation of layout in both types of method is done at 65nm CMOS technology.The simulation results show that priority encoder using semicustom design has improved power efficiency and area by 29.61µWand 253.8µm2 respectively.
Analysis, verification and fpga implementation of low power multipliereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
PERFORMANCE FACTORS OF CLOUD COMPUTING DATA CENTERS USING [(M/G/1) : (∞/GDMOD...ijgca
The ever-increasing status of the cloud computing hypothesis and the budding concept of federated cloud computing have enthused research efforts towards intellectual cloud service selection aimed at developing techniques for enabling the cloud users to gain maximum benefit from cloud computing by selecting services which provide optimal performance at lowest possible cost. Cloud computing is a novel paradigm for the provision of computing infrastructure, which aims to shift the location of the computing infrastructure to the network in order to reduce the maintenance costs of hardware and software resources. Cloud computing systems vitally provide access to large pools of resources. Resources provided by cloud computing systems hide a great deal of services from the user through virtualization. In this paper, the cloud data center is modelled as queuing system with a single task arrivals and a task request buffer of infinite capacity.
Optimized Layout Design of Priority Encoder using 65nm TechnologyIJEEE
This paper provides comparative performance analysis of power and area of 4 bit priority encoder using 65nm technology.Two priority encoder approaches are presented, one with full automatic and the other with semicustom. The main objective is to compare full automatic and semicustomdesigned layout on the basis of two parameters which is power and area. The automatic design circuit simulation has been done on logic editor and layout created from Verilog file which is simulated. The semicustom layout is created manually and simulated. Creation of layout in both types of method is done at 65nm CMOS technology.The simulation results show that priority encoder using semicustom design has improved power efficiency and area by 29.61µWand 253.8µm2 respectively.
Analysis, verification and fpga implementation of low power multipliereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A High Performance Modified SPIHT for Scalable Image CompressionCSCJournals
In this paper, we present a novel extension technique to the Set Partitioning in Hierarchical Trees (SPIHT) based image compression with spatial scalability. The present modification and the preprocessing techniques provide significantly better quality (both subjectively and objectively) reconstruction at the decoder with little additional computational complexity. There are two proposals for this paper. Firstly, we propose a pre-processing scheme, called Zero-Shifting, that brings the spatial values in signed integer range without changing the dynamic ranges, so that the transformed coefficient calculation becomes more consistent. For that reason, we have to modify the initialization step of the SPIHT algorithms. The experiments demonstrate a significant improvement in visual quality and faster encoding and decoding than the original one. Secondly, we incorporate the idea to facilitate resolution scalable decoding (not incorporated in original SPIHT) by rearranging the order of the encoded output bit stream. During the sorting pass of the SPIHT algorithm, we model the transformed coefficient based on the probability of significance, at a fixed threshold of the offspring. Calling it a fixed context model and generating a Huffman code for each context, we achieve comparable compression efficiency to that of arithmetic coder, but with much less computational complexity and processing time. As far as objective quality assessment of the reconstructed image is concerned, we have compared our results with popular Peak Signal to Noise Ratio (PSNR) and with Structural Similarity Index (SSIM). Both these metrics show that our proposed work is an improvement over the original one.
Design and Implementation of a Programmable Truncated Multiplierijsrd.com
Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. However, this result in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction trade off against signal degradation which can be modified at run time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analysed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a fine-grain truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. Software compensation also shown to be effective when deploying truncated multipliers in a system.
Stochastic Computing Correlation Utilization in Convolutional Neural Network ...TELKOMNIKA JOURNAL
In recent years, many applications have been implemented in embedded systems and mobile Internet of Things (IoT) devices that typically have constrained resources, smaller power budget, and exhibit "smartness" or intelligence. To implement computation-intensive and resource-hungry Convolutional Neural Network (CNN) in this class of devices, many research groups have developed specialized parallel accelerators using Graphical Processing Units (GPU), Field-Programmable Gate Arrays (FPGA), or Application-Specific Integrated Circuits (ASIC). An alternative computing paradigm called Stochastic Computing (SC) can implement CNN with low hardware footprint and power consumption. To enable building more efficient SC CNN, this work incorporates the CNN basic functions in SC that exploit correlation, share Random Number Generators (RNG), and is more robust to rounding error. Experimental results show our proposed solution provides significant savings in hardware footprint and increased accuracy for the SC CNN basic functions circuits compared to previous work.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An fpga implementation of the lms adaptive filter eSAT Journals
Abstract This paper brings out implementation of Least Mean Square (LMS) algorithm using two different architectures. The implementations are made on Xilinx Virtex–4 FPGA as part of realization of an Active Vibration Control system. Both fixed point and floating point data representations are considered. A comparison between the two is brought out on the basis of a Finite State Machine (FSM) model suitable for both fixed & floating point implementations. The floating point LMS algorithm in VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language), uses the Intellectual Property (IP) cores available from Xilinx Inc. Results from the two architectures with respect to area as well as performance clearly shows floating point implementation to emerge as the better option in all respects. Index Terms: Least Mean Square Algorithm, Field programmable gate arrays (FPGA), floating point IP cores, Finite State Machine, Active Vibration Control.
Mixed approach for scheduling process in wimax for high qoseSAT Journals
Abstract
WiMAX(worldwide interoperability for Microwave Access) networks are the networks which are responsible for providing many services like video, data and voice. The WiMAX technology satisfies the modern need of broadband internet through wireless access. For managing all these services through WiMAX, IEEE802.16 gives QOS (Quality of Service) parameter. In WiMAX, a fundamental challenge is to achieve high QOS so that various parameters like waiting time, end to end delay can be minimized and other parameter like execution time and network utilization etc. To obtain high QOS there is scheduling algorithm which is implemented at the base station and subscriber stations. In this paper we discuss scheduling algorithms and also compare the parameters (waiting time, turnaround time, execution time, packet drop age and packet delivery). We purpose a scheduling algorithm which is combination of greedy latency, distance calculation of user from base station, calculate the burst time and apply SJF on that burst values.
Keywords: WiMAX, QOS, IEEE802.16, Scheduling, FCFS (first come first serve), SJF(Shortest job First), Latency.
A continuous time adc and digital signal processing system for smart dust and...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Motion compensation for hand held camera deviceseSAT Journals
Abstract
With handy camera image is not enough stable at that time stabilization method is used to recover that shaky effect. So, stabilization of image is concept to recover the scale and theta of shaky image. For that algorithm should be able to stabilize the image with maximum original information from that shaky input image. And from this image stabilization algorithm we can use this as a fundamental concept to stabilize the video. Here in this paper algorithm is applied for 2D image and measure the efficiency of that algorithm
Keywords: Motion estimation; Feature detection methods; FAST feature detection
Fpga implementation of optimal step size nlms algorithm and its performance a...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A High Performance Modified SPIHT for Scalable Image CompressionCSCJournals
In this paper, we present a novel extension technique to the Set Partitioning in Hierarchical Trees (SPIHT) based image compression with spatial scalability. The present modification and the preprocessing techniques provide significantly better quality (both subjectively and objectively) reconstruction at the decoder with little additional computational complexity. There are two proposals for this paper. Firstly, we propose a pre-processing scheme, called Zero-Shifting, that brings the spatial values in signed integer range without changing the dynamic ranges, so that the transformed coefficient calculation becomes more consistent. For that reason, we have to modify the initialization step of the SPIHT algorithms. The experiments demonstrate a significant improvement in visual quality and faster encoding and decoding than the original one. Secondly, we incorporate the idea to facilitate resolution scalable decoding (not incorporated in original SPIHT) by rearranging the order of the encoded output bit stream. During the sorting pass of the SPIHT algorithm, we model the transformed coefficient based on the probability of significance, at a fixed threshold of the offspring. Calling it a fixed context model and generating a Huffman code for each context, we achieve comparable compression efficiency to that of arithmetic coder, but with much less computational complexity and processing time. As far as objective quality assessment of the reconstructed image is concerned, we have compared our results with popular Peak Signal to Noise Ratio (PSNR) and with Structural Similarity Index (SSIM). Both these metrics show that our proposed work is an improvement over the original one.
Design and Implementation of a Programmable Truncated Multiplierijsrd.com
Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. However, this result in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction trade off against signal degradation which can be modified at run time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analysed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a fine-grain truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. Software compensation also shown to be effective when deploying truncated multipliers in a system.
Stochastic Computing Correlation Utilization in Convolutional Neural Network ...TELKOMNIKA JOURNAL
In recent years, many applications have been implemented in embedded systems and mobile Internet of Things (IoT) devices that typically have constrained resources, smaller power budget, and exhibit "smartness" or intelligence. To implement computation-intensive and resource-hungry Convolutional Neural Network (CNN) in this class of devices, many research groups have developed specialized parallel accelerators using Graphical Processing Units (GPU), Field-Programmable Gate Arrays (FPGA), or Application-Specific Integrated Circuits (ASIC). An alternative computing paradigm called Stochastic Computing (SC) can implement CNN with low hardware footprint and power consumption. To enable building more efficient SC CNN, this work incorporates the CNN basic functions in SC that exploit correlation, share Random Number Generators (RNG), and is more robust to rounding error. Experimental results show our proposed solution provides significant savings in hardware footprint and increased accuracy for the SC CNN basic functions circuits compared to previous work.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An fpga implementation of the lms adaptive filter eSAT Journals
Abstract This paper brings out implementation of Least Mean Square (LMS) algorithm using two different architectures. The implementations are made on Xilinx Virtex–4 FPGA as part of realization of an Active Vibration Control system. Both fixed point and floating point data representations are considered. A comparison between the two is brought out on the basis of a Finite State Machine (FSM) model suitable for both fixed & floating point implementations. The floating point LMS algorithm in VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language), uses the Intellectual Property (IP) cores available from Xilinx Inc. Results from the two architectures with respect to area as well as performance clearly shows floating point implementation to emerge as the better option in all respects. Index Terms: Least Mean Square Algorithm, Field programmable gate arrays (FPGA), floating point IP cores, Finite State Machine, Active Vibration Control.
Mixed approach for scheduling process in wimax for high qoseSAT Journals
Abstract
WiMAX(worldwide interoperability for Microwave Access) networks are the networks which are responsible for providing many services like video, data and voice. The WiMAX technology satisfies the modern need of broadband internet through wireless access. For managing all these services through WiMAX, IEEE802.16 gives QOS (Quality of Service) parameter. In WiMAX, a fundamental challenge is to achieve high QOS so that various parameters like waiting time, end to end delay can be minimized and other parameter like execution time and network utilization etc. To obtain high QOS there is scheduling algorithm which is implemented at the base station and subscriber stations. In this paper we discuss scheduling algorithms and also compare the parameters (waiting time, turnaround time, execution time, packet drop age and packet delivery). We purpose a scheduling algorithm which is combination of greedy latency, distance calculation of user from base station, calculate the burst time and apply SJF on that burst values.
Keywords: WiMAX, QOS, IEEE802.16, Scheduling, FCFS (first come first serve), SJF(Shortest job First), Latency.
A continuous time adc and digital signal processing system for smart dust and...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Motion compensation for hand held camera deviceseSAT Journals
Abstract
With handy camera image is not enough stable at that time stabilization method is used to recover that shaky effect. So, stabilization of image is concept to recover the scale and theta of shaky image. For that algorithm should be able to stabilize the image with maximum original information from that shaky input image. And from this image stabilization algorithm we can use this as a fundamental concept to stabilize the video. Here in this paper algorithm is applied for 2D image and measure the efficiency of that algorithm
Keywords: Motion estimation; Feature detection methods; FAST feature detection
Fpga implementation of optimal step size nlms algorithm and its performance a...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Conceptual design of laser assisted fixture for bending operationeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Transient voltage distribution in transformer winding (experimental investiga...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of area and power efficient half adder using transmission gateeSAT Journals
Abstract This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations .in this paper two bit addition has been done using conventional and transmission gate level and power, area and number of transistors are the scope of comparison. According to the simulation result, power and area are reduced by 55.35 % and 40.269% respectively when the circuit is implemented by transmission gate .thus transmission gate has become a very popular and useful technique to implement digital circuits which help to reduce power, surface area as well as number of transistors. Keywords: Transmission gate (TG), Half adder, CMOS logic gates, Surface area, Power.
High performance low leakage power full subtractor circuit design using rate ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Gsm or x10 based scada system for industrial automationeSAT Journals
Abstract Power systems are important and expensive components in the electric power system. The knowledge of the actual status of the system insulation behavior, load tap changer performance, temperature, and load condition is necessary in order to evaluate the service performance concerning reliability, availability and safety. Systems abnormalities, loading, switching and ambient condition normally contribute towards accelerated aging and sudden failure. The paper presents the causes which lead to the internal faults appearance in the power system. The production mechanisms of the faults and the on-line monitoring are also analyzed. A monitoring procedure is proposed for the diagnosis and forecasting strategy of the functioning state of the power system.
Keywords: GSM standard reference manual, Universal IC programmer
Design and implementation of 15 4 compressor using 1-bit semi domino full add...eSAT Journals
Abstract In this paper, we present 15-4 Compressor for Digital signal processing. A new Low power full adder and 5-3 compressor are used in this 15-4 compressor. Full Adder and 5:3 compressors are realized by Semi Domino logic which is faster and consumes less power than other conventional logics. Objective of this Work is to inspect the power, delay, power delay product of full adders in different logic styles and to inspect power, delay, and power delay product of Semi domino 5-3 compressor architecture with other architectures. Simulation results demonstrate the superiority of the proposed adder circuit against the pre-proposed adder circuits in terms of power, delay, PDP. The proposed style gets its benefit in terms of power, delay, PDP. The performance of the adder circuits and compressors is based on TSMC 28nm CMOS process models at the supply voltage of 1V, 500MHz frequency evaluated by the comparing of the simulation results obtained from Cadence spectre. Keywords: Semi Domino Logic, Full adder, 5-3 compressor, power, delay, PDP, TSMC 28nm.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
Abstract
Low complexity and power consumption are the key concerns while designing reconfigurable pulse shaping FIR filter for multistandard wireless communication system. In FIR filter, the single input to be multiplied by a set of coefficients known as multiple constant multiplications. This multiple constant multiplication becomes an obstruction in many applications. To overcome that, Digit Based Recoding, Canonic Sign Digit, Common Subexpression Elimination and Binary Common Subexpression Elimination algorithms are used to optimize the number of addition and subtraction operations. While designing these MCM algorithms in the architecture of RRC FIR filter, Binary Common Subexpression Elimination (BCSE) algorithm provides the better performance in terms of area and power.
Keywords: Multiple Constant Multiplication (MCM), Root Raised Cosine Filter (RRC), Canonic Sign Digit (CSD), Multiple Sign Digit (MSD), Common Subexpression Elimination (CSE)
Area and Power Efficient Up-Down counter Design by Using Full Adder ModuleIJEEE
In this paper an area and power efficient 98T Up- Down counter design has been presented by using Pass transistor logic designing technique. The proposed Up-Down counter design consist of 53 NMOS and 45 PMOS. Four PTL full adder modules has been used to design this Up-Down counter which consumes less area and power at 120 nm as compared to CMOS, TG and GDI full adder designs. The proposed Up-Down counter design is based on this area and power efficient 10 transistors PTL full adder module. The proposed Up-Down counter has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 using 120nm technology. Results show that Area of proposed PTL Up- Down counter design is 1288.4 µm2 on 120nm technology. At 1.2V input supply voltage the proposed Up-Down counter design consumes 111µW power at BSIM-4.
Design of power and delay efficient 32 bit x 32 bit multi precision multiplie...eSAT Journals
encountered arithmetic operations in DSP applications. The proposed multi precision(MP) multiplier that incorporates variable precision, parallel processing (PP), and dedicated MP operands scheduling to provide optimum performance for a various operating conditions. The building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or it also work parallel to form higher-precision multipliers. To reduce power consumption and delay, replaces the razor flip flop and voltage scaling unit .The Look up table (LUT) together with dynamic voltage and frequency management system configure the multiplier to work at low power consumption. The LUT stores the minimum voltages required for the multiplication of 8-bit, 16-bit and 32-bit multiplications. The multiplier consists of carry propagation adder which is replaced by carry select adder due to this a considerable delay reduction can be achieved. The MP multiplier is also consists of Frequency management unit makes the multiplier to operate at proper frequency. Finally, the proposed novel MP multiplier can further benefit from an operands scheduler that rearranges the input data, that determine the optimum voltage and frequency operating conditions for minimum power consumption. Experimental results show that the proposed MP Multiplier provides a 14.55% reduction in power consumption and 9.67% reduction in delay compared with conventional razor based DVS MP Multiplier. When combining this MP design with LUT, Parallel processing, and the operands scheduler, delay and power reduction can be achieved to a great extent. This paper successfully demonstrates that MP multiplier architecture can allow more aggressive frequency/supply voltage scaling for improved power and delay efficiency.
Keywords: Computer arithmetic, low power design, multi-precision multiplier, Input Operands Scheduler (IOS), Look Up Table.
Design of all digital phase locked loop (d pll) with fast acquisition timeeSAT Journals
Abstract
A Digital PLL is designed with improved acquisition time and power efficiency. The implemented D-PLL can operate
from 6.54MHz to 105MHz with a power dissipation of is 7.763μW (at 210MHz) with 1.2V supply voltage. The D-PLL is
synthesized using cadence RTL compiler in 45nm CMOS process technology.
Keywords: Digital PLL, Digital Phase/Frequency detector, NCO, Divide by N counter.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Protocol converter (uart, i2 c, manchester protocols to usb)eSAT Journals
Abstract
Abstract now a day’s many industries are using different types of protocols to show data on computer. For this purpose different modules are used which increases the hardware complexity and cost. This project (PROTOCOL CONVERTER) is helpful to overcome these problem different types of protocols such as Manchester, UART and I2Cconverted to the USB format which is compatible to the laptops which is the major application .By using different components such as PIC microcontroller 18F452, LCD, Personal computer, Max 232, DB9 connector.
Keywords::USB (universal serial bus)1, UART(universal asynchronous receiver/transmitter2), I2C (Inter-Integrated Circuit3), Manchester4.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An octo coding technique to reduce energy transition in low power vlsi circuitseSAT Journals
Abstract System on–chip design in deep submicron technology interconnects plays an important role in overall performance of the chip. Digital circuits consists of a number of interconnected logic gates which together perform a logic operation with more input signals. When an input signal changes the change will propagates via the gates to the circuit generating energy transition The signal transition causes to charge or discharge the capacitive load of CMOS circuits will induces the power dissipation. Recently power dissipation is becoming an important constrain in a deep submicron VLSI technology. There are several methods for the reduction of dynamic power dissipation through energy transition in data buses. Among them the Novel Octo-coding method is most effective and powerful method for enhancing the behavior of on-chip data buses. This coding method is implemented and analyzed using Xilinx and Modelsim tools Keywords: Switching activity, Hamming distance, Energy Transition, Active Power dissipation, Octo Coding .
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
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Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
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About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
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Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
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Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Td ams processing for vlsi implementation of ldpc decoder
1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 05 | May-2014, Available @ http://www.ijret.org 335
TD-AMS PROCESSING FOR VLSI IMPLEMENTATION OF LDPC
DECODER
Maramreddy Harish1
, Neelima Koppala2
1
P.G.Student scholar M.Tech (VLSI), ECE Department, Sree vidyanikethan engineering college (Autonomous)
2
Assistant professor, ECE Department, Sree vidyanikethan engineering college (Autonomous)
Abstract
An Efficient analog to digital interface (TDC/DTC) is presented. In particular, we explore time-based techniques for data conversion,
which can potentially achieve significant reductions in power consumption while keeping silicon chip area will be very small. On the
basis of a generic mixed-signal system the scaling difficulties of analog and mixed-signal circuits based on a signal representation in
the voltage domain are discussed for nanometer CMOS technologies. Easy to control and seamlessly embedded, were also low latency
occur. Mainly applicant for LDPC implementation which is used for error correcting and image processing will be done. In gate level
verilog hardware description language used for coding digital circuits using tool Xilinx ISE 10.1i and target family Spartan
3E,Device XC3S500, speed -5,package:FG320.The synthesized for the proposed digital circuits.
Keywords—low density parity-check (LDPC), time-to-digital converter (TDC), Binary-search time-to digital converter
(BS-TDC), low power
----------------------------------------------------------------------***--------------------------------------------------------------------
1. INTRODUCTION
The rationale behind digitally-assisted analog design is to
move the accuracy burden from the realm of analog design to
the digital domain. Relaxing the precision of the analog
circuitry reduces power consumption significantly, while the
correction of analog imperfections is implemented in the
digital domain, allowing lower power and faster designs[1]. At
this point the motivating question shall be discussed why
TDCs suddenly become popular in mainstream micro-
electronics: Modern VLSI technology is mainly driven by
digital circuits. The reasons for this are the many advantages
of digital compared to analog circuits: Atomic digital
functions can be realized by very small and simple circuits.
This results in a compact and cheap implementation of
elementary logic functions and enables complex and flexible
signal processing systems[2]. A comparable complexity was
not feasible with an analog implementation due to area and
power consumption but also due to variability and signal
integrity.
Flexible means reconfigurable, adjustable or even
programmable. Data can be stored easily in digital systems
without any loss of information. The design of digital circuits
is highly automated resulting in high design efficiency and
productivity. However, the main advantage of digital signal
processing is the inherent robustness of digital signals against
any disturbances, i.e. noise and coupling, as well as the
inherent robustness of digital circuits against process
variations[4].
Fig. 1 Generic digital signal processing system
The reduction in supply voltage accompanying technology
scaling, which is dramatically Improves the energy and area
efficiencies of a digital circuits, makes the realization of
voltage domain analog computation circuits, problematic. In
order to maintain a dynamic range under such a low supply
voltage ,it is necessary to reduce the mismatches and thermal
noise ,and that results in large chip area and low power
consumption[1] .
2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 05 | May-2014, Available @ http://www.ijret.org 336
Fig. 2 Basic TD-AMS
2. DIGITAL TO TIME CONVERTER
The circuit diagram of a single-bit DTC and its operation
principle are shown in Fig.3 Digital-to-time conversion is
realized by selecting a signal from delayed or non-delayed
time-domain Signals originated from clk according to a digital
input signal. The DTC is composed of unit delay cells with
Tdel delay (DELs), NORs, and inverters [1]. When Din is low,
node B stays low and a rising edge of passes through two
NORs. On the other hand, when is high, the rising edge passes
through DEL as well as two NORs. As a result, according to
whether is high or low, the timing of the rising edge of varies
Dout by Tdel.
Fig 3 Digital to time converter circuit diagram
Fig 4 Timing waveform for 1bit DTC
Fig 5 Proposed 3bit DTC circuit diagram
Fig 6 Timing waveform for 3bit DTC diagram
A multi-bit DTC is composed of cascaded single bit DTCs
with binary weighted numbers of DELs. For example 3bit
3. CONVENTIONAL TDC AND ITS OPERATION
The operating principle of a TDC based on a digital delay line.
The reference clock which is in a more general sense an
arbitrary start signal is delayed along the delay-line. On the
arrival of the stop signal the delayed versions of the input
signal are sampled in parallel. Either latches or flip-flops can
be used as sampling elements. The sampling process freezes
the state of the delay-line at the instance where the clock
signal occurs [7].These results in a thermometer code because
all delay stages which have been already passed by the start
signal give a HIGH value at the outputs of the sampling
elements, all delay stages which have not been passed by the
input signal yet give a LOW value. The position of the HIGH-
LOW transition in this thermometer code indicates how far the
input signal could propagate during the time interval spanned
by the input and the clock signal. Hence this transition is a
measure for the time interval .An excellent style manual for
science writers is [7].
3. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 05 | May-2014, Available @ http://www.ijret.org 337
An implementation of the basic delay-line TDC is shown in
Fig. 7. The input signal ripples along a buffer chain that
produces the delayed signals input[7]. Flip-flops are connected
to the outputs of the delay elements and sample the state of the
delay line on the rising edge of the clk signal. The clk signal
drives a high number of flip-flops so a buffer-tree (not shown)
is required. Any skew in this buffer-tree directly contributes to
the non-linearity of the TDC characteristics.
Fig 7 Delay based conventional TDC circuit diagram
Fig. 8 Timing diagram for delay based conventional TDC
4. BINARY SEARCH TDC
TDCs are extensively researched now days for use in all
digital PLLs in wireless Transceivers so on, because a TDC
can gain the full benefits of deep submicron CMOS process.
Before explanation of binary search TDC (BS-TDC) proposed
circuit just briefly describe a conventional TDC, which is
composed in the form delay chain and flip-flops. In other
words, the required number of flip-flops increases extremely
based n bits, which is a lead to more area and delay.
In order to reduce those parameters, we proposed BS-TDC
based on binary search algorithm. As shown below fig.11.the
n-bit BS-TDC is composed only of n FFs, where as there are
2^n-1 FFs in a conventional TDC. Because the area and power
for FFs are dominant in TDCs, reducing FFs directly results in
area and power reduction. Although a binary-search approach
is commonly used in voltage-domain ADCs, some tricks are
required in order to apply it to a TDC because time can neither
be stored nor subtracted[1].
Fig. 9 Circuit diagram of the Binary search TDC
Fig. 10 Timing waveform for binary search TDC
Fig. 11 Circuit diagram of the new proposed Binary search
TDC
Fig 12 Timing waveform for new proposed binary search
TDC
But in fig.9 binary search TDC has logic error is there .when
an input is high then one output will become doesn‟t exist
because the clk will become low[7] .so that the logical error
applied in proposed binary search TDC .so, that a modification
of changing the inverted input at DTC to normal input is done
in the above fig.9
4. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 05 | May-2014, Available @ http://www.ijret.org 338
Fig. 13 Comparison area based on LUTs conventional TDC
and binary search TDC
Fig. 14 Comparison combinational delay between
conventional TDC and Binary TDC
Table 1: Performance summary comparison conventional
TDC and BS-TDC
Types of
TDC
/parameter
Conventional TDC Binary search
TDC
Number of
bits
(n)
3b 4b 5b 3b 4b 5b
Number of
LUTs
7 15 31 3 4 5
Delay(ns) 4.32 7.11 12.23 4.2 5.9 9.7
5. ACCURACY OF DTC AND TDC
The accuracy of DTC and TDC with simulation of the circuit
show in fig.15 A 1b digital input of DTC is converted into
time domain signal and TDC converted digital output Dout .In
order based on clock signal DTC and another input 011 taken
input to full range of the DTC [4] .Then output of TDC Dout
will be high .But the digital logic should not mismatches, if it
so error occurrence will be appear. The simulation result in
hardware implementation is given below fig16.
6. MINIMUM CALCULATION
A minimum calculation, which is most frequently, appears in
min-sum algorithm for LDPC code decoding, is executable by
a single 1bit Comparator gate as shown in Fig. 17. The output
of OR becomes high when any one of the input signals
becomes high. Then, among the input signals with various
rising edge timings, the OR can find the fastest one, which
corresponds to the minimal value[7]. A simulation result is
shown in Fig. 18. These calculations are obviously more
efficient than the digital counterparts.
Fig. 15 Circuit diagram of accuracy of DTC and TDC
Fig. 16 Timing waveform for Accuracy
5. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 05 | May-2014, Available @ http://www.ijret.org 339
Fig. 16 Circuit diagram of Minimum calculation
Fig. 17 Timing waveform for minimum calculation
Fig. 18 simulation results for minimum calculation
7. LOW DENSITY PARITY CHECK CODES
Low-density parity-check codes are a class of linear block
code defined by a sparse M x N parity-check matrix, H
[5],where N > M and M = N − K. Although LDPC codes can
be generalized to non-binary symbols, we consider only binary
codes. The parity-check matrix has a small number of „1‟
entries compared to „0‟ entries, making it sparse. The number
of „1‟s in a parity-check matrix row is called the row-weight,
k, and the number of „1‟s in a column is the column-weight, j.
A regular LDPC code is one in which both row and column
weights are constant, otherwise, the parity check matrix is
irregular. Although a LDPC code is defined by a sparse
matrix, a bipartite graph, also known as a Tanner graph, can
be used to represent the code. A bipartite graph is a graph
whose nodes can be divided into two sets such that each node
is connected to a node in the other set. The two sets of nodes
in a Tanner graph are called check nodes and variable nodes
representing rows and columns respectively[6].
Fig.19 (a)parity check matrix (b) Tanner graph Representation
Fig. 20 Architecture of LDPC decoder
6. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 05 | May-2014, Available @ http://www.ijret.org 340
Tanner graph representation will be reduced to minimum
routing congestion and also reduced power consumption[6].
Fig20.illustrates the overall architecture of the implementation
(8,4) LDPC decoder leveraging TD-AMS .It is mainly of
variable node function units(VNUs) corresponding to (1) and
check node function units(CNUs) corresponding to (2). The
calculations in the VNUs and CNUs are partitioned into the
time domain and digital domain, considering efficiency. The
minimum function in the CNU and the summation function in
the VNU are executed in the time domain, whereas absolute
value (ABS) and XOR function in the CNU are executed in
the digital domain.
Fig. 21 Timing waveform for parity check matrix
Fig. 22 Timing waveform for check node unit
Fig. 23 Timing waveform for variable node unit
Fig. 24 BER measurement results
8. EXPERIMENTAL RESULTS
All the circuits in TD-AMS including TDC and DTC are
developed verilog hardware description language in the same
way digital .These modules can be incorporated in the verilog
simulations of the system including general digital modules.
LDPC decoder with proposed time –domain analog and digital
mixed signal processing .LDPC is implemented in 90 nm
technology and Bit error rate (BER) measurement results is
calculated in MATLAB tool
9. CONCLUSIONS
The analog circuitry is reduced to two simple building blocks,
leading to less design complexity and lower power
consumption. But this trade-off is quite favorable given recent
technological advancements in nanometer CMOS
technologies. The proposed technique is binary search TDC
can enhance the delay and area efficiencies of computing
especially in applications where high calculation accuracy and
complete answers are not required, such as error correction
and Image processing. Bit error rate is reduced also power
consumption will be reduced.
REFERENCES
[1] Hiroyuki.Kobayashi,Kazurori Hashiyoshi,”An LDPC
Decoder with Time-Domain Analog and Digital
Mixed processing”.IEEE J of Solid
circuits,Vol.49,No.1 January 2014.
[2] B.K Swann et al.,”A 100-ps Time Resolution CMOS
Time to converter for positron Emission Tomography
Imaging Applications,”IEEE Journal of Solid-State
circuits,Vol.39,No.11,pp1839-1852.Nov,2004.
7. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 05 | May-2014, Available @ http://www.ijret.org 341
[3] H.Lee and C.G.Sodini.”Anaolg to Digital
converters.Digitizing the Analog World ,”Proceeding
of the IEEE,pp.323-33.Feb 2008.
[4] J.P.Jansson,A.mantyniemi and J.Kostamovaana”A
CMOS Time to Digital converter with Better than
10ps single-shot precision,”IEEE Journal of Solid-
State Circuits,Vol.41,No.6,pp,1286-1296,June 2006.
[5] C.L Juscin et al,”An Integrated 16-channel CMOS
Time to Digital converter ,”IEEE Transactions on
Nuclear Science ,Vol.41,August 1994.
[6] R.G.Gallager,”Low Density Parity Check
Codes,”Ph.D.dissertation, Massachusetts
Inst.technol.,Cambridge,MA,USA.1963.
[7] D.Miyashita,R.Yamaki,K.HashiYoshi,H.Kobayashi,S
.Kousai,Y.Oowaki and Y.Unekawa,”A 10.4
pJ/b(32,8) LDPC Decoder with Time-domain Analog
and digital mixed signal processing ,” in IEEE
int.Solid-State Circuit conf .Dig.Tech papers ,2013
.pp 420-421.
[8] S. Hemati, A. Banihashemi, and C. Plett, “A 0.18- m
CMOS analog min-sum iterative decoder for a (32, 8)
low-density parity-check (LDPC) code,” IEEE J.
Solid-State Circuits, vol. 41, no. 11, pp. 2531– 2540,
Nov. 2006.