Subroutines are blocks of code that perform specific tasks and are stored separately from the main program to avoid duplicating code segments. When called, a subroutine will execute its instructions and then return control to the point from which it was called in the main program. Interrupts temporarily halt the main program to allow interrupt service routines (ISRs) to handle priority events, with the processor saving return addresses to resume the main program after interrupts are serviced. PIC microcontrollers have multiple sources of interrupts, each with associated flags to enable interrupts and indicate interrupt requests.

2. SUB ROUTINESSUB ROUTINES
Instead of repeating same program
segments at all locations, they are written
and stored separately;
Each such block of instructions which
carries out a specific and well defined task
is called a ‘Subroutine’.

3. SUB ROUTINESSUB ROUTINES
Halt the main program
Provide returning to the same point.
Transfer control to the subroutine.
Execute the subroutine.
Revert to the main routine.

4. MOVWF
CALL bb
aa-2
aa-1
aa
aa+1
aa+2
bb-1
bb
bb+1
cc-1
cc
cc+1
RETURN
MainRoutineSubRoutine
2
3
aa+1
1
4
Program Memory
PC Content
Subrouti
ne
operation
s

5. Stack contents should remain undisturbed
during the execution of the subroutine.
Registers used in the main pgm and those in
the subroutine are not to be mixed up.
While using Goto statement, ensure that
program control is brought back to the
subroutine (using RETURN)
CALL statement has to specify the
subroutine address;13 bits PC is generated with
11 bits of address and PCLATH<4:3> as MS

6. SUB ROUTINE NESTINGSUB ROUTINE NESTING
Calling of one subroutine inside another
aa-1
aa
aa+1
bb
dd
dd+1
cc-1
cc
aa+1
dd+1
ee
ff
1 2
4
5
3
7
6
9
7
8
9
CALL bb
CALL ee
RETURN
RETURN
stack
PC content
Program
memory
Mainprogram
segment
Subroutine1
segment
Subroutine2
segment

7. CALL bb
[Subroutine 1]
aa CALL bb
PC
aa+1
stack
bb aa+1
CALL ee
[Subroutine 2]
Return from
Subroutine 2
Return from
Subroutine 1
dd CALL ee
aa+1
PC
dd+1
ee
stack
dd+1
RETURN
aa+1
PC
dd+1
stack
RETURN
PC
stack
aa+1
Sequence of operation during Subroutine nesting….

8. Regular operation of the processor is
interrupted
and a priority activity is carried out;
once the same is completed,
the regular operation is resumed

9. Increment PC
Fetch & execute next instruction
Interrupt
Flag
Save return address in stack
Attend to Interrupt (Carry out ISR)
Retrieve return address from Stack
reset
set
Processor Operation while
interrupted

10. Call occurs at specific
and predetermined
locations in the main
routine.
Can ask for service
without any prior notice.
Hardware initiated.Software initiated.
Request can come
expectedly.
Request can come
unexpectedly; may have
to carry out some
emergency activities-like
saving the status of
scratch pad registers.

11. Any of the peripherals associated with PIC can interrupt the
microcontroller.
External Peripherals can also interrupt the processor.
Each interrupt has an associated Interrupt Flag.
Interrupt can be masked by resetting its Interrupt Enable Flag.
Three conditions are to be satisfied for a source to interrupt
The interrupt flag has to be set by the Interrupt
Request(IRQ) going high.
The interrupt has to be enabled by the microcontroller by
setting the concerned Interrupt Enable Flag.
The GIE flag has to be set-again by the controller.

12. PIC 16F877A has 10 sources of interrupt:
External Interrupt
TMR0 Over Flow Interrupt
PORT B Change Interrupt
Comparator Interrupt
USART Interrupt TX
USART Interrupt RX
CCP Interrupt
TMR1 Over Flow Interrupt
TMR2 Match Interrupt
Data EEPROM Interrupt

13. INTE RBIE T0IF INTFT0IEGIE PEIE RBIF
B4 B3 B2 B1B5B7 B6 B0
INTCON REGISTER
GIE GLOBAL INTERRUPT ENABLE BIT
PIE PERIPHERAL INTERRUPT ENABLE BIT
T0IE TMER 0 OVERFLOW INT ENABLE BIT
INTE RB0/INT EXT INT ENABLE BIT
RBIE RB PORT CHANGE INT ENABLE BIT
T0IF TMR0 OVERFLOW INT FLAG BIT
INTF RB0/INT EXT INT FLAG BIT
RBIF RB PORT CHANGE INT FLAG BIT

14. TMR1IE
TMR1IF
TMR2IE
TMR2IF
CCPIE
CCPIF
CMIE
CMIF
TXIE
TXIF
RXIE
RXIF
EEIE
EEIF
TMR0IE
TMR0IF
INTF
INTE
RBIF
RBIE
PEIE
GIE
INT

15. I n t e r r u p t
T X I F
1
2
3
T M R 2 I F
E E I F
R C I F
1
2
3
I N T F
T X I E
I N T E
1
2
3
1
2
3
1
2
3
R B I FE E I E
R B I E
T M R 1 I E
1
2
3
1
2
3
T M R 1 I F
T M R 2 I E
R C I E
1
2
3
1
2
3
P E I E
1
2
3
1
2
3
1
2
3
C C P I F
T 0 I E
G I E
T 0 I F
C M I E
1
2
3
C C P I E
C M I F
1
2
3
INTERRUPT LOGIC

16. Interrupt Request and Response – Sequence of Activities

17. Positioning of ISR in Program Memory
The PIC has the provision to start the
ISR at location 0X004H
The location 0X04H can have a simple
GOTO ISR instruction.

18. 0x04h
Interrupt
from
source A
Service routine
A
Service routine B
yes
no
004h BTFSS PIR,A
GOTO SRB
---------------
--[ISR A]----
----------------
RETFIE
SRB : ---[ISR B]---
-------------
RETFIE
004h BTFSS PIR,A
GOTO SRB
---------------
--[ISR A]----
----------------
RETFIE
SRB : ---[ISR B]---
-------------
RETFIE

19. Stores the W register
Stores the Status register
Executes the ISR code
Restores the Status
Restores the W register
The common memory area with addresses 70h to 7Fh can be used
to store such data.
It eliminates the need to switch banks back and forth to access data
during interrupt service.

20. Scratchpad register assignment and status saving for each
service routine have to be done with care to avoid any mix up.
While using Goto statement, ensure that program control is
brought back to the subroutine (using RETFIE)
The return addresses of subroutines as well as those of
interrupt services are saved in the same stack.
The service routine can complete the more prioritized task of
one source, enable GIE(to allow IRQ from source B) and then
take up the second (non priority)task.
If more interrupts which exceeds the 8 level stack, are
involved; assign a different processor.

21. THANK YOU