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The evolution of TMS, family of DSP\'s

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An academic presentation explaining the evolution of TMS series of digital signal processors by Texas Instruments.

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The evolution of TMS, family of DSP\'s

  1. 1. The Evolution of TMS, Family of DSP’s Presentation By:- Ritul Sonania 2005H124416 BITS-Pilani 23 rd Nov 2006 Instructor in charge:- Prof. Sanjay Roy
  2. 2. Outline <ul><li>DSP Introduction </li></ul><ul><li>DSP Tasks </li></ul><ul><li>DSP Applications </li></ul><ul><li>DSP vs. General Purpose MPU </li></ul><ul><li>TMS DSP IC </li></ul><ul><li>TMS DSP Types </li></ul><ul><li>TMS Generations </li></ul><ul><li>Conclusion </li></ul>
  3. 3. DSP Introduction <ul><li>Digital Signal Processing : application of mathematical operations to digitally represented signals </li></ul><ul><li>Signals represented digitally as sequences of samples . </li></ul><ul><li>Digital Signal Processor (DSP) : electronic system that processes digital signals </li></ul>
  4. 4. DSP tasks- <ul><li>Most DSP tasks require: </li></ul><ul><ul><li>Repetitive numeric computations </li></ul></ul><ul><ul><li>Real-time processing </li></ul></ul><ul><ul><li>High memory </li></ul></ul><ul><ul><li>System Flexibility </li></ul></ul><ul><li>DSPs must perform these tasks efficiently while minimizing: </li></ul><ul><ul><li>Cost </li></ul></ul><ul><ul><li>Power </li></ul></ul><ul><ul><li>Memory use </li></ul></ul><ul><ul><li>Development time </li></ul></ul>
  5. 5. DSP Applications <ul><li>Digital cellular phones </li></ul><ul><li>Digital cameras </li></ul><ul><li>Satellite communication </li></ul><ul><li>Voice mail </li></ul><ul><li>Music synthesis </li></ul><ul><li>Modems </li></ul><ul><li>RADAR </li></ul>
  6. 6. DSP vs. General Purpose MPU <ul><li>DSPs tend to be written for 1 program, not many programs. </li></ul><ul><ul><li>Hence OSes are much simpler, there is no virtual memory </li></ul></ul><ul><li>DSPs run real-time apps </li></ul><ul><ul><li>You must account for anything that could happen in a time slot </li></ul></ul><ul><ul><li>All possible interrupts or exceptions must be noticed. </li></ul></ul><ul><li>DSPs have an infinite continuous data stream </li></ul>
  7. 7. TMS DSP IC.. <ul><li>TMS 320 C5X </li></ul><ul><li>TMX : Experimental device </li></ul><ul><li>TMP : Prototype </li></ul><ul><li>TMS : Qualified device </li></ul><ul><li>C: CMOS Tech with on – chip non- volatile memory as ROM </li></ul><ul><li>E: CMOS tech with on-chip non – volatile memory as EPROM </li></ul><ul><li>nothing : NMOS tech with on-chip non – volatile mem as ROM </li></ul><ul><li>5 : Generation </li></ul><ul><li>X : Version number- 0,1,2,3,4x,5,6,7 </li></ul>
  8. 8. TMS DSP Types… <ul><li>Fixed Point DSPs </li></ul><ul><ul><li>TMS320C5x & 54x </li></ul></ul><ul><ul><li>16-bit DSPs </li></ul></ul><ul><li>Floating Point DSPs </li></ul><ul><ul><li>TMS320C3x, 4x & 6x </li></ul></ul><ul><ul><li>16 & 32-bit DSPs </li></ul></ul><ul><li>Multiprocessor DSPs </li></ul><ul><ul><li>TMS320C8x </li></ul></ul>
  9. 9. TMS Product Generation
  10. 10. BASIC TMS320 ARCHITECTURE <ul><li>A DSP has to perform fast arithmetic operations and should handle mathematical intensive algorithms in real time. This was achieved by these basic concepts- </li></ul><ul><ul><li>Harvard architecture ( increased memory access/cycle) </li></ul></ul><ul><ul><li>extensive pipelining, </li></ul></ul><ul><ul><li>dedicated hardware multiplier, </li></ul></ul><ul><ul><li>special DSP instructions( DMOV – delay) </li></ul></ul><ul><ul><li>fast instruction cycle </li></ul></ul>
  11. 11. 1 st Generation TMS320C1x <ul><li>Instruction cycle timing: -160 ns -200 ns -280 ns. </li></ul><ul><li>5 MIPS </li></ul><ul><li>20 MHz </li></ul><ul><li>On chip data RAM: -144 words -256 words </li></ul><ul><li>(TMS320C17). </li></ul><ul><li>On chip program ROM: -1.5K words 4 K words (TMS320C17). </li></ul><ul><li>4K words of on chip program EPROM( TMS320E17). </li></ul><ul><li>16 x I6 bit multiplier with 32-bit result. </li></ul><ul><li>16-bit barrel shifter for shifting data memory words into the ALU. </li></ul><ul><li>4 x 12-bit stack. </li></ul><ul><li>Two auxiliary registers for indirect addressing. </li></ul><ul><li>Eight 16 bit I/O port </li></ul><ul><li>Operating Temperature . . . 0°C to 70°C </li></ul>
  12. 12. 2 nd Generation TMS320C2x <ul><li>Reduced Instruction cycle timing: -100 ns (TMS320C25) </li></ul><ul><li>10 MIPS, 40 MHz </li></ul><ul><li>4K words of onchip masked ROM (TMS320C25). </li></ul><ul><li>544 words of onchip data RAM. </li></ul><ul><li>128K words of total program data memory space. </li></ul><ul><li>Eight auxiliary registers with a dedicated arithmetic unit. </li></ul><ul><li>Serial port for multiprocessing or interfacing to codecs. </li></ul><ul><li>Bit-reversed addressing modes for fast Fourier trans-forms (TMS320C25). </li></ul><ul><li>Extended-precision arithmetic and adaptive filtering support (TMS320C25). </li></ul>
  13. 13. 3 rd Generation TMS320C3x <ul><li>60-ns single cycle execution time </li></ul><ul><li>20 -30 MIPS </li></ul><ul><li>Two 1K x 32-bit single cycle dual-access RAM blocks. </li></ul><ul><li>One 4K x 32-bit single cycle dual-access ROM block. </li></ul><ul><li>64 X 32-bit instruction cache. </li></ul><ul><li>32-bit instruction and data words, 24-bit addresses. </li></ul><ul><li>32*32 bit floating-point and integer multiplier ( 40 bit product ). </li></ul><ul><li>32-bit floating-point, integer, and logical ALU. </li></ul><ul><li>32-bit barrel shifter. </li></ul><ul><li>Eight extended-precision registers. </li></ul><ul><li>Two address-generators with eight auxiliary registers. </li></ul><ul><li>On chip Direct Memory Access (DMA) controller. </li></ul><ul><li>High-level language support. </li></ul>
  14. 14. 4 th Generation TMS320C4x <ul><li>The TMS320C4x devices are 32-bit floating-point digital signal processors optimized for parallel processing. </li></ul><ul><li>33-/40-ns instruction cycle times </li></ul><ul><li>40 MIPS </li></ul><ul><li>ANSI C compiler </li></ul><ul><li>The ’C4x family accepts source code from the TMS320C3x family of floating-point DSPs. </li></ul><ul><li>Key applications of the ’C4x family include 3-dimensional graphics, image processing, networking, and telecommunications base stations. </li></ul>
  15. 15. 5 th Generation TMS320C5x <ul><li>Fixed Point DSP </li></ul><ul><li>Power Efficient (1.15mA/MIPS) </li></ul><ul><li>20-50 MIPS </li></ul><ul><li>20-35ns single cycle execution time </li></ul><ul><li>Bit reversed /index addressing mode for FFT </li></ul><ul><li>Power Down modes </li></ul><ul><li>8 Auxiliary registers </li></ul><ul><li>Single Cycle 16*16 bit parallel multiplier (32 bit product) </li></ul><ul><li>32 bit accumulator ,32 bit ALU </li></ul>
  16. 16. TMS320C54x <ul><li>16-bit fixed point </li></ul><ul><li>Power < 40 mW </li></ul><ul><li>300 to 532 MIPS </li></ul><ul><li>3 Power down modes </li></ul><ul><li>RAM 16 Kb to 1280Kb(TMS320C5441-175) </li></ul><ul><li>ROM max 256KB </li></ul><ul><li>Applications – </li></ul><ul><ul><ul><li>Digital Cellular Base stations </li></ul></ul></ul><ul><ul><ul><li>PDA’s </li></ul></ul></ul><ul><ul><ul><li>Digital Cordless Phones </li></ul></ul></ul><ul><ul><ul><li>Modems </li></ul></ul></ul>
  17. 17. TMS320C55x <ul><li>16 & 32 bit fixed point </li></ul><ul><li>Most power efficient in the industry with 0.12mW (stand by) </li></ul><ul><li>600 MIPS </li></ul><ul><li>Dual Processor </li></ul><ul><li>RAM 320Kb </li></ul><ul><li>ROM 32 to 64Kb </li></ul><ul><li>Newest in series TMSC5506-108 </li></ul><ul><li>Applications – </li></ul><ul><ul><li>2G,2.5G,3G cellular phones and base stations </li></ul></ul><ul><ul><li>Digital audio players </li></ul></ul><ul><ul><li>Digital still cameras </li></ul></ul><ul><ul><li>GPS receivers </li></ul></ul><ul><ul><li>Wireless modems </li></ul></ul>
  18. 18. 5 th Generation … TMS320C2xx <ul><li>The TMS320C2xx was introduced in 1995. Manufactured with triple-level metal and full complementary CMOS static logic, the ’C2xx provides 20-40 MIPS performance. </li></ul><ul><li>The ’C2xx, also available as a core for TI’s customizable DSPs, is the low-cost, fixed-point DSP of the future. </li></ul><ul><li>The TMS320C24x generation high-speed central processing unit (CPU) allows the use of advanced algorithms, yielding better performance and reducing system component count. </li></ul>
  19. 19. 5 th Generation .... TMS320C8x (1995) <ul><li>1 Master Processor and up to 4 parallel processors </li></ul><ul><li>More than 2 billion operations per second (BOPS) </li></ul><ul><li>50K bytes of on-chip RAM </li></ul><ul><li>Video controller supports any display or capture resolution </li></ul><ul><li>32 bit RISC master processor with 120-MFLOPS </li></ul><ul><li>Applications – </li></ul><ul><ul><li>Desktop video conferencing, </li></ul></ul><ul><ul><li>high-speed telecom, </li></ul></ul><ul><ul><li>3-dimensional and virtual reality graphics, </li></ul></ul><ul><ul><li>digital audio and video compression . </li></ul></ul>
  20. 20. 6 th Generation TMS320C6x <ul><li>First to feature VelociTI architecture . </li></ul><ul><li>TMS320C62X </li></ul><ul><ul><li>multi-channel, multi-function applications </li></ul></ul><ul><ul><li>Advanced VLIW architecture </li></ul></ul><ul><ul><li>Medical, industrial applications, digital imaging, 3D graphics, speech recognition and voice-over packet. </li></ul></ul><ul><ul><li>Frequency 150 to 300 MHz </li></ul></ul><ul><ul><li>RAM up to 1 MB (min 128Kb) </li></ul></ul><ul><ul><li>Greater than 1600 MIPS </li></ul></ul>
  21. 21. 6 th Generation ... TMS320C6x <ul><li>TMS320C64x (highest level of performance ) </li></ul><ul><ul><li>Speeds up to 1GHz </li></ul></ul><ul><ul><li>Up to 8000 MIPS </li></ul></ul><ul><ul><li>digital communications infrastructure </li></ul></ul><ul><ul><li>video and image processing </li></ul></ul><ul><li>TMS320C67x (high-precision applications ) </li></ul><ul><ul><li>First floating point processor in 6x series </li></ul></ul><ul><ul><li>6 ns cycle timing </li></ul></ul><ul><ul><li>1billion floating point operations per second (Flops) </li></ul></ul><ul><ul><li>audio, medical imaging, instrumentation and automotive. </li></ul></ul>
  22. 22. Comparison of various generations
  23. 23. Compariso n on the basis of clock frequency
  24. 24. Conclusion <ul><li>DSP performance has increased according to the applications involved. </li></ul><ul><li>DSP friendly ness is an important factor because the applications complexity is increasing. </li></ul>
  25. 25. References <ul><li>http://www.ti.com </li></ul><ul><li>http://www.bdti.com </li></ul><ul><li>“ DSP Architectures: Past, Present and Future”, Edwin J. Tan, Wendi B. Heinzelman </li></ul><ul><li>“ The TMS320 Family of Digital Signal Processors”, KUN SHAN LIN, GENE A. FRANTZ and RAY KUMAR,IEEE-1987 </li></ul>

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