Space Codesign's presentation from ARM Technology Symposium Japan 2014 (Tokyo-Shinagawa) with Avant Technology

1. Space Codesign Systems Inc.
ESL and HW/SW Co-design for Rapid Development of
ARM-based SoC Embedded Systems
ARM Technology Symposium Japan
October 30, 2014

2. Value Proposition
ARM Technology Symposium Japan - October 30, 2014 2
Design Optimization, Increase Productivity, Improve/Maintain Quality
 Electronics design is dealing with
larger, more complex systems of
Hardware and Software
 Development approaching/exceeds
Product life
 Design Changes/Errors are Costly
 TI: Silicon Re-spin Costs up to $3
Million (ref. Synopsys Newsletter)
 Costly in Time  Late to Market!

3. Space Codesign’s SpaceStudio
ARM Technology Symposium Japan - October 30, 2014 3
Next Generation ESL Design Technology
 Algorithm / Functional Specification
- Requirements for System Architecture
 Architectural Design Exploration
- Hardware/Software Co-design
- Automation supports HW/SW
Partitioning
- Development of System Architecture
 Implementation
 Focus on System Architects

4. Traditional HW-Centric Workflow
ARM Technology Symposium Japan - October 30, 2014 4
Methodology Impacts Product Development Cycle Time
• Hardware and Software developed on separate paths
• Long design exploration cycles  late problem discovery
• Long HW Prototype debug (FPGA, Emulation, etc.)
• Virtual Prototyping has improved speed but not approach
• Risks in Integration  Problems prolong time-to-market
Mapped
architecture
Analysis
&
diagnostics
time
HW
architecture
C/C++
application
Weeks!
Integration
SW Devel.
HW Design

5. Henry Ford on Customers’ Needs
ARM Technology Symposium Japan - October 30, 2014 5
Process Improvement Also Needed
 If I had asked people what they wanted,
they would have said faster horses.

6. SpaceStudio Agile Workflow
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Methodology Improvement Enabled By Next Generation ESL Technology
• Automated transformation of functions between HW and SW
• Reuse the Same Model … Without Recoding
• Fast High Level Simulation  Rapid Virtual Prototyping & Analysis
• Agile Work Flow  Immediate Integration and Problem Detection
• Rapid Design Exploration Enabled!
time
Mapped
architecture
Analysis
&
diagnostics
HW architecture
with
SystemC TLM
layer
Multi-threaded
C/C++
application Minutes/Hours!
SW, HW,
Firmware
Generation
Integration

7. Modeling Levels and Performance
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Abstraction Impact
TimingDetail
Execution
(Simulation) Time
FAST
Untimed
RTL
Loosely
Timed
Approx.
Timed
Slow
FPGA
(Prototype)
Functional
Specification
(Algorithm)
Architecture
Exploration (HW/SW)
Implementation
Cycle
Accurate
Less
More

8. Processor ISS: ARM
ARM Technology Symposium Japan - October 30, 2014 8
ARM Fast Models and QEMU options supported
 SpaceStudio supports ARM Cortex-A9 dual core
• Popular wireless core (Apple, Samsung, Nvidia, etc.)
• Choice for new generation of powerful Programmable
Devices (Xilinx Zynq All Programmable SoC, Altera SoC
FPGA)
 ARM Fast Models selected for ARM ISS source by Space
Codesign
• Functionally Accurate, High Performance
• Validated by ARM
• Configured with SystemC TLM-2.0 interface
 QEMU recently added (ARM, etc.)

9. SpaceStudio Advantages and Benefits
ARM Technology Symposium Japan - October 30, 2014 9
Enabling Reduced Cycle Time
 Rapid System Design
• Faster Design Technology (ESL)
• Faster Design Methodology (HW/SW Co-design)
Enabled by Retargeting same model to HW or SW
 Performance Analysis
• Faster Feedback on Performance QoR
 Power and Silicon Estimation
• Interfaces Industry Standard Tech (e.g., Xilinx 14.4)
 FPGA Implementation
• Down to Chip
• Physical Prototype or Final Release
• ASIC development: guided by Virtual Prototype

10. Automation supports HW/SW Partitioning
ARM Technology Symposium Japan - October 30, 2014 10
Same Functions are Retargeted for HW or SW
Drag + Drop
Configuration 1: All SW Configuration 2:
All SW minus IDCT
 Drag and Drop Mechanism Eases Design Iteration
Iteration
Task
Coprocessor

11. Hardware/Software Co-Debugging
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Simultaneous Debugging without Restart of Hardware Simulation
 Software Debuggers + Hardware Debugger
• Communication via Sockets
• Single Environment, Simultaneous Debugging

12. Space Codesign Implementation Flow
ARM Technology Symposium Japan - October 30, 2014 12
Design Creation from Algorithm to Architecture to Implementation
Elix GenX
Functional
(algorithm)
Implementation
SpaceStudio
Architectural
(design exploration,
hw/sw co-design)
….
C/C++
Specifica
tion
Simtek
SoC Virtual
Platform
CPU Core Models (ISS)
IP Reuse
(Mapping)
High Level
Synthesis
Silicon SoC
SoftwareGeneration

13. Space Codesign in Xilinx Vivado Flow
ARM Technology Symposium Japan - October 30, 2014 13
Design Creation Front-End for Xilinx Vivado (including Vivado HLS)
Elix GenX
IP
(EDK/ISE)
Synthesis
(Vivado HLS)
Xilinx FPGA
Functional
(algorithm)
Implementation
SpaceStudio
Architectural
(design exploration,
hw/sw co-design)
SoftwareGeneration
….
C/C++
Specifica
tion
Simtek
Xilinx Virtual
Platform
CPU Core Models (ISS)

14. Space Codesign Ecosystem
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Making use of Industry Standards and Leading Technologies
 Processor Models
• QEMU (Intel, ARM, PPC, etc.)
• ARM Fast Models (Cortex-A9 dual core)
 OS
 Standards
 HLS Tools
 FPGA
SystemC, TLM-2.0 (IEEE 1666)
IP-XACT (IEEE 1685)