This document proposes an error tolerant adder (ETA) that can provide approximate results at a higher speed than conventional adders. The ETA consists of an accurate part built with a ripple carry adder and an inaccurate part containing a carry-free addition block and control block. The inaccurate part determines the speed, power, and accuracy of the ETA. The ETA was designed, simulated, and synthesized, showing improvements in delay, power, and area at the cost of accuracy. Potential applications of the ETA include signal and image processing where exact results are not required.

1. Simulation and synthesis of error
tolerance adder
Submitted by:
13635A0402-V.Komalasri project guide:
13635A0401-B.Anil Kumar T.Srinivas
13635A0406-D.Venkatesh asst. professor
11631A0437-B.Madhavi

2. contents
• Introduction
• Abstract
• Existing system
• Need for error tolerant adder
• Block diagram
• Accurate part
• Inaccurate part
• Applications
• Advantages
• conclusion

3. Introduction
• In modern VLSI technology, the occurrence of all kinds of
errors has become inevitable. By adopting an emerging
concept in VLSI design and test, error tolerance (ET), a novel
error-tolerant adder (ETA) is proposed. .
• The ETA is able to ease the strict restriction on accuracy, and
at the same time achieve tremendous improvements in both the
power consumption and speed performance.

4. Abstract
• Error Tolerant Adder (ETA) is proposed which provide
approximate result at very high speed than the convention
adder.
• The proposed adder provides improvement in delay, power and
area at the same time at the cost of accuracy.

5. Existing system
• In many applications, such as a communication system, the
analog signal coming from the outside world must first be
sampled before being converted to digital data.
• The digital data are then processed and transmitted in a noisy
channel before converting back to an analog signal.
• During this process, errors may occur anywhere.

6. PROPOSED SYSTEM
• According to the definition, a circuit is error tolerant if:
1. It contains defects that cause internal and may cause external
errors.
2. The system that incorporates this circuit produces acceptable
results.

7. Need for error tolerant adder
• Increasingly huge data sets and the need for instant response
require the adder to be large and fast.
• ETA can attain great improvement in both the power
consumption and speed performance.

8. Proposed addition arithmetic
Fig.3 Proposed Addition Arithmetic.

9. Block diagram of Error tolerant adder
Fig.4 Hardware implementation of proposed ETA.
Accurate Inaccurate

10. ETA consist of two types
• Accurate part:
The accurate part is constructed using a conventional
adder such as the RCA, CSK, CSL, or CLA.
• Inaccurate part:
The inaccurate part constitutes two blocks: a carry-free
addition block and a control block.

11. Design of the Accurate Part
• The overall delay is determined by the inaccurate part, and so
the accurate part need not be a fast adder.
• The ripple-carry adder, which is the most power-saving
conventional adder, has been chosen for the accurate part of
the circuit.

12. Ripple carry adder
Fig.5 Implementation of accurate part modified ripple carry adder.

13. Design of the Inaccurate Part
• The inaccurate part is the most critical section in the
proposed ETA as it determines the accuracy, speed
performance, and power consumption of the adder.
• The inaccurate part consists of two blocks: the carry
free addition block and the control block.

14. Control block
Fig.6 Control block. (a) Overall architecture and (b) schematic
implementations of CSGC.

15. Carry-free addition block
Fig.7 Carry-free addition block. (a) Overall architecture and
(b) schematic diagram of a modified XOR gate.

16. Fig.8 simulation wave from for Error Tolerant adder

17. Fig.9 Synthesis block for Error Tolerant Adder Top Module.

18. Fig.10 Synthesis block for Error Tolerant Adder Sub Module.

19. OUTPUT SHOWING DELAY
Fig .11 Output showing delay of ETA-32 bit

20. Example
• A=“1011001110011010” (45978) .
• B=“0110100100010011” (26899).
• The final result =“10001110010011111” (72863).
• The actual result= “10001110010101101” (72877).
• OE=72877-72863=14.
• ACC=(1-(14/72877))*100%=99.98%.

21. TOOLS USED
• Verilog for design
• Verilog test bench for verification
• Modelsim for simulation
• Xilinx for synthesis

22. Applications of ETA
SIGNAL PROCESSING APPLICATIONS
• The potential applications of the ETA fall mainly in areas
where there is no strict requirement on accuracy or where
super low power consumption.
IMAGE PROCESSING APPLICATIONS
• To compare the quality of images processed by both the
conventional FFT and the inaccurate FFT.
FAST FOURIER TRANSFORMATIONS
• The computational process of FFT involves a large number of
additions and multiplications. It is therefore a good platform
for embedding our proposed ETA.

23. Fig.12 Images after FFT and inverse FFT. (a) Image processed with
conventional adder and (b) image processed with the proposed ETA.
APPLICATION OF ERROR-TOLERANT
ADDER IN DIGITAL SIGNAL PROCESSING

24. Advantages
• Low power consumption
• High speed computation

25. CONCLUSION
• The potential applications of the ETA fall mainly in
areas where there is no strict requirement on
accuracy.
• One example of such applications is in the DSP
application for portable devices such as cell phones
and laptops.

26. Thank you