The document summarizes a study on thermal management strategies for semiconductor chips that generate 2W and 10W of heat. Researchers tested different heat sinks and air velocities. Their predictive thermal model matched experimental data within 5%. For a 2W chip, a 16-pin aligned heat sink kept temperature below 60°C at air velocities of 1-4 m/s. However, scaling to 10W with the tested strategies would not maintain the temperature below 60°C, requiring alternative strategies.

1. Thermal Management Solutions for Darlington
Semiconductors’ Microprocessors
Scott Hulbert, Robert Kim, Nicholas Montes, Swetha Viswanatha
Introduction
Procedure
Results
Conclusions
References
• The purpose of our study was to identify thermal
management strategies for a semiconductor chip
• In particular we sought strategies to keep the
temperature rise in a chip below 35 °C as it
generates 2W of heat.
• We tested the thermal behavior of the chip and
obtained a thermal coefficient of resistance, α.
• We obtained contact resistance for each heat sink
• We developed a predictive heat transfer model and
analyzed the effects of heat sinks and air flow
velocity on chip temperature for 2W of heat.
• Finally, we used our model to determine the
feasibility of dissipating 10W of heat while meeting
the same temperature requirements.
• Thermal circuit model reasonably reproduces
experimental data within ±5% accuracy.
• The recommended heat sinks can be used to
manage a 2W power dissipation will maintaining
device temperature < 60 °C.
• Scaling the power dissipation to 10W with tested
strategy is not feasible; alternative strategies should
be investigated.
Figure 1: Aluminum heat sinks used in lab,
three 5 pin staggered and one 16 pin aligned
[1] ME 495, 2013, ME 495 Lab 2_Lec3,
https://ctools.umich.edu/portal/site/b88d1bc5-2a10-455b-
8c6c-02618cfa137c/ page/c1ffb53e- 7828-4cee-b406-
c6f54e55f2f2 accessed on October 28th, 2013
[2] University of Waterloo Microelectronics Heat Transfer
Laboratory, 1997, Fluid Properties Calculator,
http://www.mhtl.uwaterloo.ca/old/onlinetools/airprop/airprop.ht
ml accessed on October 26th, 2013
[3] Simons, R., 2003, Estimating Parallel Plate-Fin Heat Sink
Thermal Resistance, Electronics Cooling,
http://www.electronics-cooling.com/2003/02/estimating-
parallel-plate-fin-heat-sink-thermal-resistance/ accessed on
Oct 17th, 2013
Recommendations
Predictive Thermal Model
Thermal Management Solutions
for 2W Power Dissipation
Figure 2: Test bench setup for evaluating chip
with heat sinks
Figure 3: The maximum allowable QH to keep Tchip below
60 °C is shown for each heat sink at the tested air velocities.
Data points that are above QH = 2W meet the thermal
management criteria. Error in QH,Max is too small too be seen
on the graph.
• We characterized the chip thermal coefficient of
resistance.
• We mounted a heat sink on the chip and found the
chip temperature using α at various fan speeds.
• We tested three 5 pin (staggered pattern) heat
sinks and one 16 pin (aligned pattern) heat sink
(shown in Fig. 1), we tested four different air flow
velocities for each heat sink in a small wind tunnel
and measured the fin base temperature with the
thermocouple.
• Total thermal resistance would have to be less
than 3.5 °C/W.
• Current heat sink designs incapable of keeping
the chip temperature below 60°C if the power
dissipation were to increase to 10W.
Tchip
Rconvective, fin
T∞
Rconvective, base
Rcontact
qb
Nqf
Complete thermal circuit model for a heat sink
with heat transfer over the base and the fins.
1. Use 16 pin aligned heat sink
QHMax= 2.50 ± 0.02 W
2. Increase the 5 pin heat sink fin
lengths to 27mm
QHMax= 2.00 ± 0.11 W
3. Use heat sink with 6 parallel
plates
QHMax= 2.35 ± 0.12 W
27mm
8
13
18
23
28
33
0 0.5 1 1.5 2 2.5 3
(Tchip-T∞)/QH(°C/W)
V∞ (m/s)
1
2
3
4
Red – Model
Blue – Experimental
Horizontal error =±0.21
Vertical error =±0.75
Figure 4: Relationship between the chip-to-ambient thermal resistance and air flow velocity for each
heat sink, from experimental and from model outputs. We found our model is accurate within ±5%.
Feasibility of 10W
Power Dissipation
Silicon chip with
heat sink
Cooling fan run
at 6-12V
1 2 3 4
Base Thickness: 2.7mm
0
0.5
1
1.5
2
2.5
3
3.5
1 1.5 2 2.5
QH,Max(W)
V∞ (m/s)
5 Pin Short
5 Pin Med
5 Pin Long
16 Pin
4 Plate
(theoretical)
Horizontal error bars removed for clarity
Horizontal error = ±0.21
Vertical error = ±0.12
1
2
3
4
7.34mm
10.77mm
14.15mm
17.98mm
9.21mm
Heat Sink Average Rcontact (°C/W)
1 2 3 4
6.07±0.62 6.07±0.62 6.70±0.30 4.05±0.51