Greg Mokler is a senior-level verification engineer with over 20 years of experience developing verification environments using hardware verification languages for ASIC/FPGA development. He has extensive experience architecting and coding verification environments, generating coverage metrics, and releasing designs with few bugs. At his current role at Trend Micro, he developed an agent-based traffic generator to improve test case generation. Previously, he introduced methodologies that reduced bug escapes by over 93% and created automated regression and random testing flows.

1. GREG MOKLER SENIOR-LEVELVERIFICATIONENGINEER
469-688-6651  gmokler@gmail.com 13003B South Madrone Trail.  Austin, TX  78737
Top-performing verification engineer with over 20 years of experience in ASIC/FPGA development. Involved in
verification using HVLs for networking, wireless baseband, video, and telephony applications. Over two years of UVM
experience and five years of experience writing RTL code. Served as lead verification engineer within project teams in
various organizations. Proven track record in the architecting and coding of verification environments, generating
coverage metrics, and releasing solid designs with very few bug escapes.
Areas of Expertise include:
 Verilog  System Verilog (VMM/UVM)  Strategic Planning
 Functional Coverage Driven  Specman E (HVL)  Team Leadership
 Constrained Random Verification  PERL Script Development  Problem Resolution
RELEVANT PROFESSIONAL EXPERIENCE
TREND MICRO  Austin, TX  2016 - Present
LEAD VERIFICATION ENGINEER
 Architected and implemented Layered Agent-based Traffic Generator for newly ported UVM testbench to
replace existing one providing improved ability to quickly generate new packet topologies and/or add new
layers to existing ones.
ENTERPRISE SECURITY PRODUCTS/HEWLETT-PACKARD  Austin, TX  2007 - 2016
LEAD VERIFICATION ENGINEER
 Developed system level verification infra-structure using VMM from scratch including class library for
generation of network traffic for IPv4 and IPv6 over Ethernet, carrying TCP, UDP, ICMP, IP tunneling, GRE, GTP,
VLAN tunneling protocols, and MPLS for verification of FPGA devices for state-of-the-art intrusion prevention
systems supporting 40 Gbps of traffic.
 Introduced constrained random test methodologies, SVA, and functional coverage resulting in over 93%
reduction in bug escapes over 6 projects.
 Created automated triage tool for assisting in root-causing failures during random testing.
 Designed automated regression flow for nightly regressions and continuous random seed testing.
 Implemented plan for VMM-to-UVM testbench port
LIFESIZE COMMUNICATIONS  Austin, TX  2003 - 2007
LEAD VERIFICATION ENGINEER
 Member of initial startup team providing guidance on appropriate approach to hardware development. Built
small team for verification of FPGAs.
 Debugged and fully verified RTL for deinterlacing video sources with advanced algorithms.
 Developed and maintained System C testbench for verifying FPGAs for processing of multiple video sources
including hi-def camera for IP-based conferencing system.
D2 AUDIO CORPORATION  Austin, TX  2002 - 2003
VERIFICATION CONSULTANT
 Responsible for development and implementation of verification environment for Class D audio PWM amplifier.
 Developed directed tests for DSP core instruction pipe control, DMA controller, and various peripherals
including SSI, I2C. Verified full code coverage using Surecov.
EDUCATION & TRAINING
Bachelor of Science in Electrical Engineering
SAN DIEGO STATE UNIVERSITY | San Diego, CA
UVM Adopter Class by Doulos