Automated Design Space Exploration and Roofline Analysis for FPGA-based HLS Applications
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The document proposes a framework to optimize FPGA-based high-level synthesis (HLS) applications through automated design space exploration and roofline analysis. It applies the framework to optimize an N-body physics simulation case study. The framework generates a roofline model to analyze memory transfer constraints. It then performs automated design space exploration to identify computational bottlenecks and optimize the operational intensity. Estimations from the design space exploration and roofline analysis are validated through AWS testing of the optimized N-body simulation, demonstrating improved performance over the baseline version.
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Automated Design Space Exploration and Roofline Analysis for FPGA-based HLS Applications
- 1. 1 DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA Automated Design Space Exploration and Roofline Analysis for FPGA-based HLS Applications Marco Siracusa: marco.siracusa@mail.polimi.it Marco Rabozzi: marco.rabozzi@polimi.it Lorenzo Di Tucci: lorenzo.ditucci@polimi.it Marco Santambrogio: marco.santambrogio@polimi.it May 17-30th, 2019 NGCX, San Francisco (CA)
- 2. 2 Context definition Field-Programmable Gate Arrays (FPGAs) are an appealing solution to overcome in a power efficient way the ever increasing computing demand of HPC applications by several fields. Bioinformatics Deep learningFinance
- 3. 3 Problem definition Field-Programmable Gate Arrays (FPGAs) are an appealing solution to overcome in a power efficient way the ever increasing computing demand of HPC applications by several fields. Bioinformatics Deep learningFinance However, the complex FPGA design flow and programmability limit the widespread adoption of FPGAs as hardware accelerator.
- 4. 4 Problem definition HLS (High-Level Synthesis): Code translation from C/C++ to an HDL Hardware Synthesis: Bitstream generation for target device Test on FPGA: Results validation on the target device Source code HLS HW Synthesis Test on FPGA Performance met? Functions optimization flow Design Space Exploration HLS estimations Optimization directives insertion O direc Roofline model generation HW description C / C++ function Manual code restructuring C/C++ source Functions optimization flow Design Space Exploration HLS estimations Optimization directives insertion Op directi Roofline model generation HW description C / C++ function Manual code restructuring Functions optimization flow Design Space Explorat Optimization directives insertio Roofline model generation HW description C / C++ function Manual co FPGA bitstream HDL code
- 5. 5 Problem definition HLS (High-Level Synthesis): Code translation from C/C++ to an HDL Hardware Synthesis: Bitstream generation for target device Test on FPGA: Results validation on the target device From minutes to hours From hours to a few days Few hours Source code HLS HW Synthesis Test on FPGA Performance met? Functions optimization flow Design Space Exploration HLS estimations Optimization directives insertion O direc Roofline model generation HW description C / C++ function Manual code restructuring C/C++ source Functions optimization flow Design Space Exploration HLS estimations Optimization directives insertion Op directi Roofline model generation HW description C / C++ function Manual code restructuring Functions optimization flow Design Space Explorat Optimization directives insertio Roofline model generation HW description C / C++ function Manual co FPGA bitstream HDL code
- 6. 6 Proposed approach We propose a framework iteratively leading the user toward the optimal HLS code while considering • Memory transfer constraints by means of roofline model analysis • Computational bottlenecks through automated DSE Source code HLS HW Synthesis Test on FPGAAutomatic roofline analysis & automatic DSE Functions optimization flow Design Space Exploration HLS estimations Optimization directives insertion Optimizatio directives selec Roofline model generation HW description C / C++ function Manual code restructuring C/C++ source Functions optimization flow Design Space Exploration HLS estim Optimization directives insertion Roofline model generation HW description C / C++ function Manual code restructuring optimized HLS code
- 7. 7 The N-Body test case N-Body physics simulation: • Compute intensive application applied in several scientific domains (astrophysics, molecular dynamics) • Simulate the evolution of a system of N physical bodies (such as astrophysical object) under the presence of a pairwise force between such bodies (e.g. gravity) F1,2 F1,3 F2, 1 F3,1 F2,3 F3,2
- 8. 8 Roofline model generation attainable performance ceiling 2 DDR ports ceiling 1 DDR port Performance[pairs/s] 106 107 108 109 1010 Operational intensity [pairs/B] 10−2 10−1 1 101 102 103
- 9. 9 Baseline operational intensity attainable performance ceiling 2 DDR ports ceiling 1 DDR port baseline operational intensity Performance[pairs/s] 106 107 108 109 1010 Operational intensity [pairs/B] 10−2 10−1 1 101 102 103
- 10. 10 Baseline performance estimation attainable performance ceiling 2 DDR ports ceiling 1 DDR port baseline operational intensity baseline performance (estimation) Performance[pairs/s] 106 107 108 109 1010 Operational intensity [pairs/B] 10−2 10−1 1 101 102 103
- 11. 11 Cached version operational intensity attainable performance ceiling 2 DDR ports ceiling 1 DDR port baseline operational intensity baseline performance (estimation) optimized operational intensity Performance[pairs/s] 106 107 108 109 1010 Operational intensity [pairs/B] 10−2 10−1 1 101 102 103
- 12. 12 Cached version DSE output attainable performance ceiling 2 DDR ports ceiling 1 DDR port baseline operational intensity baseline performance (estimation) optimized operational intensity optimized performance (estimation) Performance[pairs/s] 106 107 108 109 1010 Operational intensity [pairs/B] 10−2 10−1 1 101 102 103
- 13. 13 Cached version AWS testing attainable performance ceiling 2 DDR ports ceiling 1 DDR port baseline operational intensity baseline performance (estimation) optimized operational intensity optimized performance (estimation) optimized performance (real) Performance[pairs/s] 106 107 108 109 1010 Operational intensity [pairs/B] 10−2 10−1 1 101 102 103
- 14. 14 Conclusions We presented a framework leading the designer toward the optimal solution relying on • roofline model analysis • automated design space exploration • fast yet accurate HLS estimations
- 15. 15 DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA Thank you! Marco Siracusa: marco.siracusa@mail.polimi.it Marco Rabozzi: marco.rabozzi@polimi.it Lorenzo Di Tucci: lorenzo.ditucci@polimi.it Marco Santambrogio: marco.santambrogio@polimi.it May 17-30th, 2019 NGCX, San Francisco (CA)