The functions of fixed-point arithmetic were verified by simulations with the single instruction test as the first point. And then implemented fixed-point arithmetic with FPGA. To handle more challenges nowadays and The demand for complex tasks is increasing day by day to increase the efficiency of a processor resulting in more number of components manufactured on a single chip according to Moore's law.

1. Department of Electronics & Communication
SESSION:2019-2021
Presented by:
Sateesh kourav
M.TECH IIIth sem
Guided by:
Prof. Sunil Shah
Head, Deptt. Of EC
GGITS,Jabalpur
Gyan Ganga Institute of Technology and Sciences Jabalpur
DESIGN AND IMPLEMENTATION OF
64-BIT ARITHMETIC LOGIC UNIT
ON FPGA USING VHDL

2. ABSTRACT
 A 64-bit ALU is designed and implemented using VHDL
and simulated on a Xilinx simulator..
 Arithmetic Logic Unit part of the Central Processing Unit
which performs arithmetical operations such as addition,
subtraction, division, multiplication, etc. arithmetic logic
unit (ALU) architecture Perfect dynamic on the fly
supports the precise operation. Same as Operation ALU
Becomes more complex, becomes more complex,
becomes more expensive, and takes up more space in
the CPU so power Consumption is a major problem.
VHDL synthesized coded RTL code of fixed point is an
arithmetic core.
2

3.  The functions of fixed-point arithmetic were verified
by simulations with the single instruction test as the
first point. And then implemented fixed-point
arithmetic with FPGA. To handle more challenges
nowadays and The demand for complex tasks is
increasing day by day to increase the efficiency of a
processor resulting in more number of components
manufactured on a single chip according to Moore's
law.
3

4. INTRODUCTION
 A basic FPGA is an integrated circuit with logic
blocks which are arranged in a matrix. In addition
to logic blocks, modern FPGAs have multiplier
blocks and memory blocks inside the arithmetic
logic unit (ALU) a combination digital electronic
circuit.
 This is in contrast to FPU that operates
Decimal numbers. ALU is a fundamental
building block of CPU. Even one of the simplest
microprocessors has an ALU for purposes Such
as maintaining a timer.
4

5.  Data input is ALU The operation is called the operand is
called, and a code that represents the operation and
optionally,
 Information from the previous operation; The output of
the ALU is the result of the performed operation. ALU In
addition, additional information is exchanged with a
status register, which relates to the result of AL.
 Because ALU can be built in many ways, with detailed
specifications, the main purpose of the project is a
working ALU that performs different arithmetic and logic
functions for all.
 The output of the computation perform the following
operations:- Arithmetical operations - addition,
subtraction, increment, decrement, transfer.
 • Logical operations - AND, NOT, OR, NAND, NOR, EX-
OR, EX-NOR.
5

6. MIPS INSTRUCTION SET ARCHITECTURE
 The instruction set can be categorized under three
classifications in the MIPS ISA, these are 1 Register
Instructions 2 Immediate Instructions and 3 Jump
Instructions.
6

7. MIPS ARCHITECTURE
The accompanying framework reflects the basic
architecture of the MIPS-based frame-work: Million
Instructions Per Second It is a method of measuring the
raw speed of a computer processor.
A microprocessor without interlocked pipeline stages
(MIPS) is a RISC (Computing Reduced Instruction Set)
Architecture.
Pipelining means several operations in a single data path
at the same instant. A multi-cycle CPU comprises
countless tasks. So if something happens instead of
waiting for the process to finish at the same time Any other
task is initiated in the same data path without interfering
with the previous data. Thus processes are divided into
separate pipelines. 7

8. 8
a new operation begins The pipeline stage for which
the process is being fed. Triggers are made without
interruption For the previous process. This thusly can
increment the throughput of MIPS. the instruction set
architecture microprocessor without interlocked
pipeline stages instructions an assembler and simulator
of MIPS integer instructions and the design of an
arithmetic logic unit (ALU) which calculates the
operation results of some MIPS integer instructions. ISA
is an important issue in hardware or software co-
design.

9. 9

10. SIMULATIONS AND RESULTS
Execution of The instruction in the EX stage is according to
the prescribed op-code. Op-code storage Memory and
fetching it from memory is the primary function of the
memory unit. In this paper, we are looking at ASIP
performance results, Xilinx ISE, and XST synthesis tools.
register The transfer level (RTL) description of the ASIP
micro-architecture is designed and simulated in VHDL
using Xilinx The ISE design suite and basic functionality
are verified using assembly code and the results are
verified
10

11. Operations and Select Lines
11

12. RTL Schema of 64 Bit Arithmetic Unit
12

13. MIPS ARCHITECTURE
The accompanying framework reflects the basic
architecture of the MIPS-based frame-work: Million
Instructions Per Second It is a method of measuring
the raw speed of a computer processor.
A microprocessor without interlocked pipeline stages
(MIPS) is a RISC (Computing Reduced Instruction
Set) Architecture.
Pipelining means several operations in a single data
path at the same instant. A multi-cycle CPU
comprises countless tasks. So if something happens
instead of waiting for the process to finish at the same
time Any other task is initiated in the same data path
without interfering with the previous data. Thus
processes are divided into separate pipelines. 13

14. Simulation Results of the 64 Bit Arithmetic Unit
14

15. 15
64 Bit Arithmetic Logic Unit’s compilation report

16. CONCLUSION AND FUTURE WORK
This research paper outlines a 64-bit microprocessor
without RISC based on interlocked pipeline stages
(MIPS). The processor is executed effectively with
pipelining. Execution of each in a five-stage pipeline
system The direction occurs in a single clock cycle.
This design demonstrates the use of MIPS-based
CPUs Different register types, jump types, and quick
type instructions and take care of each of them The
classification has a diverse configuration.
16
Improved
&
Modified
Distributed
Energy
Efficient
Clustering
(M-DEEC)

17. The basic structure and design process of VHDL is
studied. Design ideas of an ALU are also studied.
Log operations from bit operations to logical
operations are implemented using simple gates that
operate independently of each other. All mathematical
verbs in ALU are performed by repeated addition. The
ALU is incorporated and designed as a single unit
with basic operations of multiplication and
comparison. The design consists of three modules,
whose output is combined using a multiplexer at the
top level. The project is designed and implemented
using VHDL and simulated using Xilinx9.2i ISE.
17
Improved
&
Modified
Distributed
Energy
Efficient
Clustering
(M-DEEC)

18. References
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18

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19

20.  [8] Loucas Louca, Todd A. Cook, and William H. Johnson, “
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20

21.  [12] Suchitha Kamble, Prof. N.N. Mhala, “VHDL IMPLEMENTATION
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VHDL”,PROJECT REPORT-2007,UNIVERSITY OF ULSTER AT
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