This document provides a SPICE model for the TC74LCX244FT CMOS digital integrated circuit octal bus buffer manufactured by Toshiba. It includes the model parameters, subcircuit definitions for various components, and simulation results validating the timing characteristics against measurements.

1. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Device Modeling Report
Bee Technologies Inc.
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC74LCX244FT
MANUFACTURER : TOSHIBA

2. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
2A1
2OE
2Y4
2Y1
1A4
1Y3
1OE
2A2
__
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
__
U1
74LCX244
SPICE MODEL
*$
*PART NUMBER : TC74LCX244FT
*MANUFACTURER : TOSHIBA
*OCTAL BUS BUFFER, NON-INVERTED, 3-STATE OUTPUTS
*All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
.subckt 74lcx244 1OEBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2OEBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1OEBAR 2OEBAR OE1 OE2
+ D0_GATE IO_LCX244 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND
+ 1A1 1A2 1A3 1A4 OE1 1Y1 1Y2 1Y3 1Y4
+ D_LCX244 IO_LCX244 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 OE2 2Y1 2Y2 2Y3 2Y4
+ D_LCX244 IO_LCX244 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_LCX244 utgate (
+ tplhmn=1ns tplhty=6.1ns tplhmx=7.5ns
+ tphlmn=1ns tphlty=6.5ns tphlmx=7.5ns
+ tpzhmn=1ns tpzhty=7.3ns tpzhmx=9ns
+ tpzlmn=1ns tpzlty=7.7ns tpzlmx=9ns
+ tphzmn=1ns tphzty=6ns tphzmx=8ns
+ tplzmn=1ns tplzty=6.2ns tplzmx=8ns
+ )
.model IO_LCX244 uio (
+ drvh=24.5 drvl=18.7
+ inld=7pF
+ AtoD1="AtoD_LCX244" AtoD2="AtoD_LCX244_NX"

3. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ AtoD3="AtoD_LCX244" AtoD4="AtoD_LCX244_NX"
+ DtoA1="DtoA_LCX244" DtoA2="DtoA_LCX244"
+ DtoA3="DtoA_LCX244" DtoA4="DtoA_LCX244"
+ tswhl1=477ps tswlh1=470ps
+ tswhl2=477ps tswlh2=470ps
+ tswhl3=477ps tswlh3=470ps
+ tswhl4=477ps tswlh4=470ps
+ DIGPOWER="DIGIFPWR"
+ )
.subckt AtoD_LCX244 A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A LCX_CLAMP
X2 A DPWR LCX_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
O0 A DGND DO74LCX244 DGTLNET=D IO_LCX244
.ends
.subckt AtoD_LCX244_NX A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A LCX_CLAMP
X2 A DPWR LCX_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
O0 A DGND DO74LCX244_NX DGTLNET=D IO_LCX244
.ends
.subckt DtoA_LCX244 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
G_OH DPWR DPWR_OH
+ TABLE { V(DPWR_OH,DPWR) }
+ -5.5, 142mA,
+ -4.0, 140mA,
+ -3.0, 135mA,
+ -2.0, 120mA,
+ -0.6, 50mA,
+ 0.0, 0,
+ 0.5, -40mA
X1 A DPWR LCX_CLAMP
G_OL DGND_OL DGND
+ TABLE { V(DGND_OL,DGND) }
+ -0.5, -70mA,
+ 0, 0,
+ 1.0, 120mA,
+ 1.6, 150mA,
+ 2.0, 160mA,
+ 3.0, 170mA,
+ 5.5, 172mA,
X2 DGND A LCX_CLAMP

4. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
N1 A DGND_OL DPWR_OH DIN74LCX244 DGTLNET=D IO_AC_DTOA
C1 A DGND {CAPACITANCE+0.01pF}
R1 A DGND 1G
.ends
.subckt LCX_Clamp A C
G_Clamp A C TABLE { V(A,C) }
+ 0.0, 10uA
+ 0.5, 1mA
+ 5.5, 1A
.ends
.model DO74LCX244 doutput (
+ s0name="X" s0vlo=0.799 s0vhi=2.0
+ s1name="0" s1vlo=-1.5 s1vhi=0.799
+ s2name="R" s2vlo=0.799 s2vhi=1.55
+ s3name="R" s3vlo=1.45 s3vhi=2.0
+ s4name="X" s4vlo=0.799 s4vhi=2.0
+ s5name="1" s5vlo=2.0 s5vhi=7.0
+ s6name="F" s6vlo=1.45 s6vhi=2.0
+ s7name="F" s7vlo=0.799 s7vhi=1.55
+ )
.model DO74LCX244_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=2
+ s2name="1" s2vlo=2 s2vhi=7.0
+ )
.model DIN74LCX244 dinput (
+ s0name="0" s0tsw=0.7ns s0rlo=8 s0rhi=0.23K
+ s1name="1" s1tsw=0.7ns s1rlo=425 s1rhi=13
+ s2name="X" s2tsw=0.7ns s2rlo=104 s2rhi=100
+ s3name="R" s3tsw=0.7ns s3rlo=104 s3rhi=100
+ s4name="F" s4tsw=0.7ns s4rlo=104 s4rhi=100
+ s5name="Z" s5tsw=0.7ns s5rlo=200K s5rhi=200K
+ )
.MODEL IO_AC_DTOA UIO()
*$

5. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
L L L L 0
TimeTime
0s 0.5us 1.0us
1:1OEBAR
1:2OEBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LO
LO
LO
LO
LO
LO
2A1
2OE
2Y4
2Y1
1A4
1Y3
1OE
2A2
__
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
__
U1
74LCX244
R1
1MEG
LO LO
LO
LO
0
V1
3.6

6. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
L H H H 0
TimeTime
0s 0.5us 1.0us
1:1OEBAR
1:2OEBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LOHI
0
R1
1MEG
HI
V1
3.6HI
2A1
2Y4
2Y1
1A4
1Y3
2A2
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
1OE
__
2OE
__
U1
74LCX244
HI
HI
HI
HI
LO
HI

7. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
G An Yn (Measurement) Yn (Simulation)
%Error
H X Z Z 0
TimeTime
0s 0.5us 1.0us
1:1OEBAR
1:2OEBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
U1:1Y1
U1:1Y2
U1:1Y3
U1:1Y4
U1:2Y1
U1:2Y2
U1:2Y3
U1:2Y4
1
1
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
0
V1
3.6
X
R1
1MEG
2A1
2Y4
2Y1
1A4
1Y3
2A2
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
1OE
__
2OE
__
U1
74LCX244
X
CLK
DSTM1
OFFTIME = .2uS
ONTIME = .2uS
HI
HI

8. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 5V Measurement Simulation %Error
VIH (V) 2 2 0
VIL (V) 0.8 0.799170 -0.104
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
1.0V
2.0V
3.0V
(566.674u,2.0002)
(526.639u,799.170m)
Output
Input
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 3
V2
3
LO
2A1
2OE
2Y4
2Y1
1A4
1Y3
1OE
2A2
__
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
__
U1
74LCX244
0
LO
R1
1G
OUT

9. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level Output Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIH, VCC = 3 V Measurement Simulation %Error
Min VOH = (VCC - 0.2) V 2.8 2.8340 1.214
Time
0s 5ms 10ms
V(OUT)
0V
1.0V
2.0V
3.0V
Output
0
I1
-100u
LO
V1
2.1
OUT
2A1
2OE
2Y4
2Y1
1A4
1Y3
1OE
2A2
__
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
__
U1
74LCX244
LO
V2
3

10. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Low Level Output Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIL, VCC = 3 V Measurement Simulation %Error
VOL (V) 0.2 0.191208 -4.396
Time
0s 5ms 10ms
V(OUT)
0V
1.0V
2.0V
3.0V
0
I1
100u
LO
V1
0.7
OUT
2A1
2OE
2Y4
2Y1
1A4
1Y3
1OE
2A2
__
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
__
U1
74LCX244
LO
V2
3
Output

11. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 500 Ω
VCC = 2.7 V, tr=tf= 2.5 ns Measurement Simulation %Error
tPLH (ns) 7.5 7.4214 -1.048
tPHL (ns) 7.5 7.4696 -0.405
Time
0s 0.5us 1.0us
1 V(tplh_tphl) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
0V
1.5V
3.0V
2
>>
Output
Input
V2
2.7
LO
0
tplh_tphl
R1
500
2A1
2OE
2Y4
2Y1
1A4
1Y3
1OE
2A2
__
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
__
U1
74LCX244
LO
V1TD = 0.2u
TF = 3.15n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.15n
V2 = 2.7
C1
50p

12. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time, high impedance (off) to high output (tPZH)
Output disable time, high to high impedance (off) output (tPHZ)
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 500 Ω
VCC = 2.7 V, tr=tf= 2.5 ns Measurement Simulation %Error
tPZH (ns) 9 8.9765 -0.261
tPHZ (ns) 8 7.9671 -0.411
Time
0s 0.5us 1.0us
1 V(TPZH_TPHZ) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
>>
0V
1.0V
2.0V
3.0V
2
Output
Input
2A1
2OE
2Y4
2Y1
1A4
1Y3
1OE
2A2
__
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
__
U1
74LCX244
C1
50p
HI
V2
2.7
R2
500
0
HI
R1
500
tpzh_tphz
V1TD = 0.2u
TF = 3.15n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.15n
V2 = 2.7

13. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time, high impedance (off) to low output (tPZL)
Output disable time, low to high impedance (off) output (tPLZ)
Circuit simulation result
Evaluation circuit
Comparison table CL = 50 pF, RL = 500 Ω
VCC = 2.7 V, tr = tf = 2.5 ns Measurement Simulation %Error
tPZL (ns) 9 8.8887 -1.237
tPLZ (ns) 8 7.9379 -0.776
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
0V
1.5V
3.0V
2
>>
Output
Input
C1
50p
tpzl_tplzHI
R2
500
V3
2.7
0
R1
500
LO
V2
62A1
2OE
2Y4
2Y1
1A4
1Y3
1OE
2A2
__
2Y2
1A2
2A3
1Y4
VCC
1A3
2Y3
GND
1Y1
2A4
1Y2
1A1
__
U1
74LCX244
V1TD = 0.2u
TF = 3.15n
PW = 0.5u
PER = 1u
V1 = 0
TR = 3.15n
V2 = 2.7