TC7S08F PSpice Model (Free SPICE Model)

1. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
Device Modeling Report
Bee Technologies Inc.
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC7S08F
MANUFACTURER : TOSHIBA

2. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
GND
INA
OUTY
VCCINB
U1
TC7S08
SPICE MODEL
*$
*PART NUMBER: TC7S08F
*MANUFACTURER: TOSHIBA
*2-INPUT AND GATE
*All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
.SUBCKT tc7s08 A B Y DPWR DGND
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+ A B Y
+ D_7S08 IO_S08 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_7S08 ugate (
+ tplhty=4.2ns tplhmx=25ns
+ tphlty=4.6ns tphlmx=25ns )
.model IO_S08 uio (
+ drvh=87 drvl=87
+ inld=5pF
+ AtoD1="AtoD_S08" AtoD2="AtoD_S_NX08"
+ AtoD3="AtoD_S08" AtoD4="AtoD_S_NX08"
+ DtoA1="DtoA_S08" DtoA2="DtoA_S08"
+ DtoA3="DtoA_S_E08" DtoA4="DtoA_S_E08"
+ tswhl1=2.742ns tswlh1=2.758ns
+ tswhl2=2.742ns tswlh2=2.758ns
+ tswhl3=2.751ns tswlh3=2.763ns
+ tswhl4=2.751ns tswlh4=2.763ns
+ DIGPOWER="DIGIFPWR" tpwrt=2ns
+ )
.subckt AtoD_S08 A D DPWR DGND
+ params: CAPACITANCE=0
C1 A DGND {CAPACITANCE+0.01pF}
X1 DGND A S_CLAMP
X2 A DPWR S_CLAMP
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO7S08 DGTLNET=D IO_S08
.ends
.subckt AtoD_S_NX08 A D DPWR DGND

3. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
+ params: CAPACITANCE=0
C1 A DGND {CAPACITANCE+0.01pF}
X1 DGND A S_CLAMP
X2 A DPWR S_CLAMP
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO7S_NX08 DGTLNET=D IO_S08
.ends
.subckt DtoA_S08 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
G_OH DPWR DPWR_OH
+ TABLE {V(DPWR_OH,DPWR) }
+ -7.0, 22.5mA,
+ -3.5, 20.5mA,
+ -2.0, 16.5mA,
+ -1.0, 11mA,
+ 0, 0,
+ 1.5, -17.5mA
X1 A DPWR S_CLAMP
ROH DPWR DPWR_OH 100meg
G_OL DGND_OL DGND
+ TABLE { V(DGND_OL,DGND) }
+ -1.0, -11.5mA,
+ 0, 0,
+ 1.0, 11.5mA,
+ 1.5, 15mA,
+ 2.5, 18mA,
+ 5.0, 18.5mA
X2 DGND A S_CLAMP
ROL DGND DGND_OL 100MEG
N1 A DGND_OL DPWR_OH DIN7S08 DGTLNET=D IO_HC_DTOA
C1 A DGND {CAPACITANCE+0.01pF}
R1 A DGND 1G
.ends
.subckt DtoA_S_E08 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
G_OH DPWR DPWR_OH
+ VALUE = {
+ TABLE( V(DPWR,DGND),
+ 2.0, TABLE( V(DPWR_OH,DGND), ; VCC=2
+ -1.0, 3.8mA,
+ 0, 3.6mA,
+ 0.8, 3.3mA,
+ 1.4, 2.5mA,
+ 2.0, 0.0mA, ; Remaining values extrapolated from 4.5v
+ 2.5, -4.125mA,

4. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
+ 3.0, -8.835mA,
+ 3.5, -15.0mA,
+ 4.5, -25.0mA ),
+ 4.5, TABLE( V(DPWR_OH,DGND), ; VCC=4.5
+ -1.0, 22.5mA,
+ 1.0, 20.5mA,
+ 2.5, 16.5mA,
+ 3.5, 11mA,
+ 4.5, 0,
+ 6.0, -17.5mA ),
+ 6.0, TABLE( V(DPWR_OH,DGND), ; VCC=6.0
+ -1.0, 34.5mA,
+ 1.0, 33.5mA,
+ 2.5, 31mA,
+ 4.5, 17.5mA,
+ 6.0, 0,
+ 7.0, -12.5mA
+ )
+ ) * TABLE( TEMP, -50, 1.3, 25, 1, 125, 0.7)
+ }
X1 A DPWR S_CLAMP
ROH DPWR DPWR_OH 100meg
G_OL DGND_OL DGND
+ VALUE = {
+ TABLE( V(DPWR,DGND),
+ 2.0, TABLE( V(DGND_OL,DGND), ; VCC=2
+ -0.5, -2.5mA,
+ 0, 0,
+ 0.4, 2mA,
+ 0.8, 2.8mA,
+ 1.2, 3mA,
+ 2.5, 3.25mA
+ ),
+ 4.5, TABLE( V(DGND_OL,DGND), ; VCC=4.5
+ -1.0, -11.5mA,
+ 0, 0,
+ 1.0, 11.5mA,
+ 1.5, 15mA,
+ 2.5, 18mA,
+ 5.0, 18.5mA
+ ),
+ 6.0, TABLE( V(DGND_OL,DGND), ; VCC=6.0
+ -1.0, -15mA,
+ 0, 0,
+ 1.0, 15mA,

5. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
+ 2.0, 23.5mA,
+ 3.5, 28.5mA,
+ 6.5, 29.5mA
+ )
+ ) * TABLE( TEMP, -50, 1.3, 25, 1, 125, 0.7)
+ }
X2 DGND A S_CLAMP
ROL DGND DGND_OL 100MEG
N1 A DGND_OL DPWR_OH DIN7S08 DGTLNET=D IO_HC_DTOA
C1 A DGND {CAPACITANCE+0.01pF}
R1 A DGND 1G
.ends
.subckt S_Clamp A C
G_Clamp A C TABLE { V(A,C) }
+ 0.0, 1uA
+ 0.5, 1mA
+ 5.5, 1A
.ends
.model DO7S08 doutput (
+ s0name="X" s0vlo=0.299 s0vhi=0.715
+ s1name="0" s1vlo=-0.3 s1vhi=0.299
+ s2name="R" s2vlo=0.299 s2vhi=0.55
+ s3name="R" s3vlo=0.45 s3vhi=0.715
+ s4name="X" s4vlo=0.299 s4vhi=0.715
+ s5name="1" s5vlo=0.715 s5vhi=1.3
+ s6name="F" s6vlo=0.45 s6vhi=0.715
+ s7name="F" s7vlo=0.299 s7vhi=0.55)
.model DO7S_NX08 doutput (
+ s0name="0" s0vlo=-1.3 s0vhi=0.5
+ s2name="1" s2vlo=0.5 s2vhi=1.3)
.model DIN7S08 dinput (
+ s0name="0" s0tsw=8.0ns s0rlo=1 s0rhi=1000K
+ s1name="1" s1tsw=7.7ns s1rlo=100K s1rhi=1
+ s2name="X" s2tsw=4.0ns s2rlo=110 s2rhi=100
+ s3name="R" s3tsw=4.0ns s3rlo=110 s3rhi=100
+ s4name="F" s4tsw=4.0ns s4rlo=110 s4rhi=100
+ s5name="Z" s5tsw=4.0ns s5rlo=200K s5rhi=200K)
.model IO_HC_DTOA uio ()
*$

6. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
An Bn Yn (Measurement) Yn (Simulation)
%Error
L L L L 0
TimeTime
0s 0.5us 1.0us
U1:A
U1:B
Y1
0
0
0
LO
R1
1MEG
Y1
0
LO
GND
INA
OUTY
VCCINB
U1
TC7S08
V1
5

7. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
An Bn Yn (Measurement) Yn (Simulation)
%Error
L H L L 0
TimeTime
0s 0.5us 1.0us
U1:A
U1:B
Y1
0
1
0
0
HI
V1
5
LO
Y1
GND
INA
OUTY
VCCINB
U1
TC7S08
R1
1MEG

8. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
An Bn Yn (Measurement) Yn (Simulation)
%Error
H L L L 0
TimeTime
0s 0.5us 1.0us
U1:A
U1:B
Y1
1
0
0
GND
INA
OUTY
VCCINB
U1
TC7S08
R1
1MEG
V1
5
LO
HI
0
Y1

9. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
An Bn Yn (Measurement) Yn (Simulation)
%Error
H H H H 0
TimeTime
0s 0.5us 1.0us
U1:A
U1:B
Y1
1
1
1
R1
1MEG
Y1
HI
HI
V1
5
0
GND
INA
OUTY
VCCINB
U1
TC7S08

10. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 4.5V Measurement Simulation %Error
VIH (V) 3.15 3.218 2.159
VIL (V) 1.35 1.3455 -0.333
Time
0s 1.0ms 2.0ms 3.0ms 4.0ms
V(R1:1) V(V1:+)
0V
2.5V
5.0V
Output
Input
R1
1MEG
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 4.5
V2
4.5
GND
INA
OUTY
VCCINB
U1
TC7S08
0
HI

11. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
High Level and Low Level Output Voltage
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 4.5V Measurement Simulation %Error
VOH (V) 4.5 4.4955 -0.1
VOL (V) 0 0 0
Time
0s 5ms 10ms
V(V1:+)
0V
2.5V
5.0V
V(R1:1)
0V
2.5V
5.0V
SEL>> Output
Input
HI
R1
1MEG
GND
INA
OUTY
VCCINB
U1
TC7S08
V1
TD = 0.5m
TF = 3n
PW = 1m
PER = 2m
V1 = 0
TR = 3n
V2 = 4.5
0
V2
4.5

12. All Rights Reserved Copyright (C) Bee Technologies Inc. 2005
Propagation Delay Time
Circuit simulation result
Evaluation circuit
Comparison table
CL=15pF,VCC = 5V,tr=tf=6ns Measurement Simulation %Error
tTLH (ns) 5 5.0236 0.472
tTHL (ns) 5 5.0224 0.448
TpLH (ns) 7 7.0337 0.481
TpHL (ns) 7 7.0115 0.164
Time
0s 50ns 100ns
V(C1:1) V(V1:+)
0V
2.5V
5.0V
Output
Input
0
GND
INA
OUTY
VCCINB
U1
TC7S08
HI
V2
5
C1
15p
V1
TD = 10n
TF = 6n
PW = 50n
PER = 100n
V1 = 0
TR = 6n
V2 = 5