This document provides a SPICE model for the TC74VCX244FT CMOS digital integrated circuit manufactured by Toshiba. It includes: - Component details such as part number, manufacturer, and description of an octal bus buffer. - The SPICE subcircuit model for the device, including definitions for each internal gate and switching behavior at different power supply voltages. - Parameters for gate propagation delays, input/output levels, and other electrical characteristics.

1. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Device Modeling Report
Bee Technologies Inc.
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC74VCX244FT
MANUFACTURER : TOSHIBA

2. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
1A1
2Y4
1A3
1OE
1A4
2Y11Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND2A1
1Y2
__
VCC
2Y3
U1
74VCX244
SPICE MODEL
*$
*PART NUMBER : TC74VCX244FT
*MANUFACTURER : TOSHIBA
*OCTAL BUS BUFFER, NON-INVERTING, 3-STATE BOFFER
*All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
.subckt 74vcx244 1OEBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2OEBAR DPWR
X_U1 1OEBAR 1A1 2Y41 1A2 2Y31 1A3 2Y21 1A4 2Y11 DGND
+ 2A1 1Y41 2A2 1Y31 2A3 1Y21 2A4 1Y11 2OEBAR DPWR 244_1
X_U2 1OEBAR 1A1 2Y42 1A2 2Y32 1A3 2Y22 1A4 2Y12 DGND
+ 2A1 1Y42 2A2 1Y32 2A3 1Y22 2A4 1Y12 2OEBAR DPWR 244_2
X_U3 1OEBAR 1A1 2Y43 1A2 2Y33 1A3 2Y23 1A4 2Y13 DGND
+ 2A1 1Y43 2A2 1Y33 2A3 1Y23 2A4 1Y13 2OEBAR DPWR 244_3
X_U4 1OEBAR 1A1 2Y44 1A2 2Y34 1A3 2Y24 1A4 2Y14 DGND
+ 2A1 1Y44 2A2 1Y34 2A3 1Y24 2A4 1Y14 2OEBAR DPWR 244_4
X_U5 1OEBAR 1A1 2Y45 1A2 2Y35 1A3 2Y25 1A4 2Y15 DGND
+ 2A1 1Y45 2A2 1Y35 2A3 1Y25 2A4 1Y15 2OEBAR DPWR 244_5
E_E1 5 0 VALUE { IF(V(DPWR)>=1.2 & V(DPWR)<1.4,1,0) }
E_E2 4 0 VALUE { IF(V(DPWR)>=1.4 & V(DPWR)<1.65,1,0) }
E_E3 3 0 VALUE { IF(V(DPWR)>=1.65 & V(DPWR)<2.3,1,0) }
E_E4 2 0 VALUE { IF(V(DPWR)>=2.3 & V(DPWR)<=2.7,1,0) }
E_E5 1 0 VALUE { IF(V(DPWR)>2.7 & V(DPWR)<=3.6001,1,0) }
S1 1Y1 1Y11 1 0 _S1
S2 1Y1 1Y12 2 0 _S1
S3 1Y1 1Y13 3 0 _S1
S4 1Y1 1Y14 4 0 _S1
S5 1Y1 1Y15 5 0 _S1
S6 1Y2 1Y21 1 0 _S1
S7 1Y2 1Y22 2 0 _S1
S8 1Y2 1Y23 3 0 _S1
S9 1Y2 1Y24 4 0 _S1
S10 1Y2 1Y25 5 0 _S1
S11 1Y3 1Y31 1 0 _S1
S12 1Y3 1Y32 2 0 _S1
S13 1Y3 1Y33 3 0 _S1
S14 1Y3 1Y34 4 0 _S1
S15 1Y3 1Y35 5 0 _S1
S16 1Y4 1Y41 1 0 _S1
S17 1Y4 1Y42 2 0 _S1
S18 1Y4 1Y43 3 0 _S1
S19 1Y4 1Y44 4 0 _S1
S20 1Y4 1Y45 5 0 _S1
S21 2Y1 2Y11 1 0 _S1
S22 2Y1 2Y12 2 0 _S1

3. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
S23 2Y1 2Y13 3 0 _S1
S24 2Y1 2Y14 4 0 _S1
S25 2Y1 2Y15 5 0 _S1
S26 2Y2 2Y21 1 0 _S1
S27 2Y2 2Y22 2 0 _S1
S28 2Y2 2Y23 3 0 _S1
S29 2Y2 2Y24 4 0 _S1
S30 2Y2 2Y25 5 0 _S1
S31 2Y3 2Y31 1 0 _S1
S32 2Y3 2Y32 2 0 _S1
S33 2Y3 2Y33 3 0 _S1
S34 2Y3 2Y34 4 0 _S1
S35 2Y3 2Y35 5 0 _S1
S36 2Y4 2Y41 1 0 _S1
S37 2Y4 2Y42 2 0 _S1
S38 2Y4 2Y43 3 0 _S1
S39 2Y4 2Y44 4 0 _S1
S40 2Y4 2Y45 5 0 _S1
.MODEL _S1 VSWITCH Roff=1000e6 Ron=0.001u Voff=0 Von=1
.ends
*------------------244_1--(2.7 V < VCC <= 3.6 V)--------------------
.subckt 244_1 1OEBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2OEBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1OEBAR 2OEBAR OE1 OE2
+ D0_GATE IO_244_1 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND
+ 1A1 1A2 1A3 1A4 OE1 1Y1 1Y2 1Y3 1Y4
+ D_244_1 IO_244_1 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 OE2 2Y1 2Y2 2Y3 2Y4
+ D_244_1 IO_244_1 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
+ tplhmn=0.6ns tplhty=2.8ns tplhmx=3.5ns
+ tphlmn=0.6ns tphlty=2.6ns tphlmx=3.5ns
+ tpzhmn=0.6ns tpzhty=3.5ns tpzhmx=4.5ns
+ tpzlmn=0.6ns tpzlty=3.55ns tpzlmx=4.5ns
+ tphzmn=0.6ns tphzty=2.0ns tphzmx=3.0ns
+ tplzmn=0.6ns tplzty=1.98ns tplzmx=3.0ns
+ )
.model IO_244_1 uio (
+ drvh=24.5 drvl=18.7
+ inld=6pF
+ AtoD1="AtoD_244_1" AtoD2="AtoD_244_1_NX"
.model D_244_1 utgate (
+ AtoD3="AtoD_244_1" AtoD4="AtoD_244_1_NX"
+ DtoA1="DtoA_244_1" DtoA2="DtoA_244_1"
+ DtoA3="DtoA_244_1" DtoA4="DtoA_244_1"
+ tswhl1=477ps tswlh1=470ps
+ tswhl2=477ps tswlh2=470ps

4. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ tswhl3=477ps tswlh3=470ps
+ tswhl4=477ps tswlh4=470ps
+ DIGPOWER="DIGIFPWR"
+ )
.subckt AtoD_244_1 A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VCX_CLAMP
X2 A DPWR VCX_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
O0 A DGND DO74244_1 DGTLNET=D IO_244_1
.ends
.subckt AtoD_244_1_NX A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VCX_CLAMP
X2 A DPWR VCX_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
O0 A DGND DO74244_1_NX DGTLNET=D IO_244_1
.ends
.subckt DtoA_244_1 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
G_OH DPWR DPWR_OH
+ TABLE { V(DPWR_OH,DPWR) }
+ -5.5, 142mA,
+ -4.0, 140mA,
+ -3.0, 135mA,
+ -2.0, 120mA,
+ -0.6, 50mA,
+ 0.0, 0,
+ 0.5, -40mA
X1 A DPWR VCX_CLAMP
G_OL DGND_OL DGND
+ TABLE { V(DGND_OL,DGND) }
+ -0.5, -70mA,
+ 0, 0,
+ 1.0, 120mA,
+ 1.6, 150mA,
+ 2.0, 160mA,
+ 3.0, 170mA,
+ 5.5, 172mA,
X2 DGND A VCX_CLAMP
N1 A DGND_OL DPWR_OH DIN74244_1 DGTLNET=D IO_AC_DTOA
C1 A DGND {CAPACITANCE+0.01pF}
R1 A DGND 1G
.ends
.model DO74244_1 doutput (
+ s0name="X" s0vlo=0.799 s0vhi=2.0
+ s1name="0" s1vlo=-1.5 s1vhi=0.799
+ s2name="R" s2vlo=0.799 s2vhi=1.55
+ s3name="R" s3vlo=1.45 s3vhi=2.0
+ s4name="X" s4vlo=0.799 s4vhi=2.0
+ s5name="1" s5vlo=2.0 s5vhi=7.0
+ s6name="F" s6vlo=1.45 s6vhi=2.0
+ s7name="F" s7vlo=0.799 s7vhi=1.55

5. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ )
.model DO74244_1_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=2
+ s2name="1" s2vlo=2 s2vhi=7.0
+ )
.model DIN74244_1 dinput (
+ s0name="0" s0tsw=0.7ns s0rlo=7.8 s0rhi=0.23K
+ s1name="1" s1tsw=0.7ns s1rlo=425 s1rhi=13
+ s2name="X" s2tsw=0.7ns s2rlo=104 s2rhi=100
+ s3name="R" s3tsw=0.7ns s3rlo=104 s3rhi=100
+ s4name="F" s4tsw=0.7ns s4rlo=104 s4rhi=100
+ s5name="Z" s5tsw=0.7ns s5rlo=200K s5rhi=200K
+ )
.MODEL IO_AC_DTOA UIO()
.model D0_GATE ugate ()
.subckt VCX_Clamp A C
G_Clamp A C TABLE { V(A,C) }
+ 0.0, 20uA
+ 0.5, 1mA
+ 5.5, 1A
.ends
*-----------------244_2---(2.3 V <= VCC <= 2.7 V)----------------------
.subckt 244_2 1OEBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2OEBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1OEBAR 2OEBAR OE1 OE2
+ D0_GATE IO_244_2 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND
+ 1A1 1A2 1A3 1A4 OE1 1Y1 1Y2 1Y3 1Y4
+ D_244_2 IO_244_2 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 OE2 2Y1 2Y2 2Y3 2Y4
+ D_244_2 IO_244_2 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_244_2 utgate (
+ tplhmn=0.8ns tplhty=3.5ns tplhmx=4.2ns
+ tphlmn=0.8ns tphlty=3.3ns tphlmx=4.2ns
+ tpzhmn=0.8ns tpzhty=4.5ns tpzhmx=5.5ns
+ tpzlmn=0.8ns tpzlty=4.6ns tpzlmx=5.5ns
+ tphzmn=0.8ns tphzty=2.6ns tphzmx=3.2ns
+ tplzmn=0.8ns tplzty=2.6ns tplzmx=3.2ns
+ )
.model IO_244_2 uio (
+ drvh=24.5 drvl=18.7
+ inld=6pF
+ AtoD1="AtoD_244_2" AtoD2="AtoD_244_2_NX"
+ AtoD3="AtoD_244_2" AtoD4="AtoD_244_2_NX"
+ DtoA1="DtoA_244_2" DtoA2="DtoA_244_2"
+ DtoA3="DtoA_244_2" DtoA4="DtoA_244_2"
+ tswhl1=477ps tswlh1=470ps

6. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ tswhl2=477ps tswlh2=470ps
+ tswhl3=477ps tswlh3=470ps
+ tswhl4=477ps tswlh4=470ps
+ DIGPOWER="DIGIFPWR"
+ )
.subckt AtoD_244_2 A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VCX_CLAMP
X2 A DPWR VCX_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
O0 A DGND DO74244_2 DGTLNET=D IO_244_2
.ends
.subckt AtoD_244_2_NX A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VCX_CLAMP
X2 A DPWR VCX_CLAMP
C1 A DGND {CAPACITANCE+0.01pF}
O0 A DGND DO74244_2_NX DGTLNET=D IO_244_2
.ends
.subckt DtoA_244_2 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
G_OH DPWR DPWR_OH
+ TABLE { V(DPWR_OH,DPWR) }
+ -5.5, 142mA,
+ -4.0, 140mA,
+ -3.0, 135mA,
+ -2.0, 120mA,
+ -0.6, 50mA,
+ 0.0, 0,
+ 0.5, -40mA
X1 A DPWR VCX_CLAMP
G_OL DGND_OL DGND
+ TABLE { V(DGND_OL,DGND) }
+ -0.5, -70mA,
+ 0, 0,
+ 1.0, 120mA,
+ 1.6, 150mA,
+ 2.0, 160mA,
+ 3.0, 170mA,
+ 5.5, 172mA,
X2 DGND A VCX_CLAMP
N1 A DGND_OL DPWR_OH DIN74244_2 DGTLNET=D IO_AC_DTOA
C1 A DGND {CAPACITANCE+0.01pF}
R1 A DGND 1G
.ends
.model DO74244_2 doutput (
+ s0name="X" s0vlo=0.699 s0vhi=1.6
+ s1name="0" s1vlo=-1.5 s1vhi=0.699
+ s2name="R" s2vlo=0.699 s2vhi=1.55
+ s3name="R" s3vlo=1.45 s3vhi=1.6
+ s4name="X" s4vlo=0.699 s4vhi=1.6
+ s5name="1" s5vlo=1.6 s5vhi=7.0
+ s6name="F" s6vlo=1.45 s6vhi=1.6

7. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ s7name="F" s7vlo=0.699 s7vhi=1.55
+ )
.model DO74244_2_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=2
+ s2name="1" s2vlo=2 s2vhi=7.0
+ )
.model DIN74244_2 dinput (
+ s0name="0" s0tsw=0.7ns s0rlo=11s0rhi=0.21K
+ s1name="1" s1tsw=0.7ns s1rlo=330 s1rhi=13
+ s2name="X" s2tsw=0.7ns s2rlo=104 s2rhi=100
+ s3name="R" s3tsw=0.7ns s3rlo=104 s3rhi=100
+ s4name="F" s4tsw=0.7ns s4rlo=104 s4rhi=100
+ s5name="Z" s5tsw=0.7ns s5rlo=200K s5rhi=200K
+ )
*------------------244_3--(1.65 V <= VCC < 2.3 V)-------------------
.subckt 244_3 1OEBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2OEBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1OEBAR 2OEBAR G1 G2
+ D0_GATE IO_244_3 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND
+ 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4
+ D_244_3 IO_244_3 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4
+ D_244_3 IO_244_3 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_244_3 utgate (
+ tplhmn=1.5ns tplhty=7.3ns tplhmx=8.4ns
+ tphlmn=1.5ns tphlty=7.7ns tphlmx=8.4ns
+ tpzhmn=1.5ns tpzhty=8.2ns tpzhmx=9.8ns
+ tpzlmn=1.5ns tpzlty=8.8ns tpzlmx=9.8ns
+ tphzmn=1.5ns tphzty=4.8ns tphzmx=5.8ns
+ tplzmn=1.5ns tplzty=5.1ns tplzmx=5.8ns
+ )
.model IO_244_3 uio (
+ drvh=35.3 drvl=46.9
+ inld=6pF
+ AtoD1="AtoD_244_3" AtoD2="AtoD_244_3_NX"
+ AtoD3="AtoD_244_3" AtoD4="AtoD_244_3_NX"
+ DtoA1="DtoA_244_3" DtoA2="DtoA_244_3"
+ DtoA3="DtoA_244_3" DtoA4="DtoA_244_3"
+ tswhl1=529ps tswlh1=695ps
+ tswhl2=513ps tswlh2=718ps
+ tswhl3=529ps tswlh3=695ps
+ tswhl4=513ps tswlh4=718ps
+ DIGPOWER="DIGIFPWR" tpwrt=2.9ns
+ )
.subckt AtoD_244_3 A D DPWR DGND
+ params: CAPACITANCE=0

8. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
X1 DGND A VCX_CLAMP
X2 A DPWR VCX_CLAMP
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74244_3 DGTLNET=D IO_244_3
C1 A DGND {CAPACITANCE+0.1pF}
D0 DGND a D74SCLMP
D1 1 2 D74
D2 2 DGND D74
D3 3 1 D74
D4 3 A D74
D5 1 a D74S
R1 DPWR 3 3700k
.ends
.subckt AtoD_244_3_NX A D DPWR DGND
+ params: CAPACITANCE=0
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74244_3_NX DGTLNET=D IO_244_3
C1 A DGND {CAPACITANCE+0.1pF}
D0 DGND a D74SCLMP
D1 1 2 D74
D2 2 DGND D74
D3 3 1 D74
D4 3 A D74
D5 1 a D74S
R1 DPWR 3 3700k
.ends
.subckt DtoA_244_3 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
N1 A DGND DPWR DIN74244_3 DGTLNET=D IO_244_3
C1 A DGND {CAPACITANCE+0.1pF}
.ends
.model DO74244_3 doutput (
+ s0name="X" s0vlo=0.199 s0vhi=0.65
+ s1name="0" s1vlo=-0.2 s1vhi=0.199
+ s2name="R" s2vlo=0.199 s2vhi=0.55
+ s3name="R" s3vlo=0.45 s3vhi=0.65
+ s4name="X" s4vlo=0.199 s4vhi=0.65
+ s5name="1" s5vlo=0.65 s5vhi=1.3
+ s6name="F" s6vlo=0.45 s6vhi=0.65
+ s7name="F" s7vlo=0.199 s7vhi=0.55
+ )
.model D74SCLMP d (
+ is=1e-11vj=.7 rs=2 cjo=2pf
+ )
.model D74 d (
+ is=1e-16rs=25 cjo=2pf
+ )
.model D74S d (
+ is=1e-12vj=.7 rs=25 cjo=2pf
+ )
.model DO74244_3_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=1.0725
+ s2name="1" s2vlo=1.0725 s2vhi=7.0

9. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ )
.model DIN74244_3 dinput (
+ s0name="0" s0tsw=1.0ns s0rlo=22s0rhi=180
+ s1name="1" s1tsw=1.0ns s1rlo=400 s1rhi=43.8
+ s2name="X" s2tsw=1.0ns s2rlo=49.4 s2rhi=127
+ s3name="R" s3tsw=1.0ns s3rlo=49.4 s3rhi=127
+ s4name="F" s4tsw=1.0ns s4rlo=49.4 s4rhi=127
+ s5name="Z" s5tsw=1.0ns s5rlo=200K s5rhi=200K
+ )
*------------------244_4--(1.4 V <= VCC < 1.65 V)---------------------
.subckt 244_4 1OEBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2OEBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1OEBAR 2OEBAR G1 G2
+ D0_GATE IO_244_4 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND
+ 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4
+ D_244_4 IO_244_4 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4
+ D_244_4 IO_244_4 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_244_4 utgate (
+ tplhmn=2.0ns tplhty=15.6ns tplhmx=16.8ns
+ tphlmn=2.0ns tphlty=16.1ns tphlmx=16.8ns
+ tpzhmn=2.0ns tpzhty=16.8ns tpzhmx=19.6ns
+ tpzlmn=2.0ns tpzlty=18.8ns tpzlmx=19.6ns
+ tphzmn=2.0ns tphzty=10ns tphzmx=11.6ns
+ tplzmn=2.0nss tplzty=10.4ns tplzmx=11.6ns
+ )
.model IO_244_4 uio (
+ drvh=35.3 drvl=46.9
+ inld=6pF
+ AtoD1="AtoD_244_4" AtoD2="AtoD_244_4_NX"
+ AtoD3="AtoD_244_4" AtoD4="AtoD_244_4_NX"
+ DtoA1="DtoA_244_4" DtoA2="DtoA_244_4"
+ DtoA3="DtoA_244_4" DtoA4="DtoA_244_4"
+ tswhl1=529ps tswlh1=695ps
+ tswhl2=513ps tswlh2=718ps
+ tswhl3=529ps tswlh3=695ps
+ tswhl4=513ps tswlh4=718ps
+ DIGPOWER="DIGIFPWR" tpwrt=2.9ns
+ )
.subckt AtoD_244_4 A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VCX_CLAMP
X2 A DPWR VCX_CLAMP
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74244_4 DGTLNET=D IO_244_4
C1 A DGND {CAPACITANCE+0.1pF}

10. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
D0 DGND a D74SCLMP
D1 1 2 D74
D2 2 DGND D74
D3 3 1 D74
D4 3 A D74
D5 1 a D74S
R1 DPWR 3 3700k
.ends
.subckt AtoD_244_4_NX A D DPWR DGND
+ params: CAPACITANCE=0
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74244_4_NX DGTLNET=D IO_244_4
C1 A DGND {CAPACITANCE+0.1pF}
D0 DGND a D74SCLMP
D1 1 2 D74
D2 2 DGND D74
D3 3 1 D74
D4 3 A D74
D5 1 a D74S
R1 DPWR 3 3700k
.ends
.subckt DtoA_244_4 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
N1 A DGND DPWR DIN74244_4 DGTLNET=D IO_244_4
C1 A DGND {CAPACITANCE+0.1pF}
.ends
.model DO74244_4 doutput (
+ s0name="X" s0vlo=0.0499 s0vhi=0.65
+ s1name="0" s1vlo=-0.2 s1vhi=0.0499
+ s2name="R" s2vlo=0.0499 s2vhi=0.55
+ s3name="R" s3vlo=0.45 s3vhi=0.65
+ s4name="X" s4vlo=0.0499 s4vhi=0.65
+ s5name="1" s5vlo=0.65 s5vhi=1.3
+ s6name="F" s6vlo=0.45 s6vhi=0.65
+ s7name="F" s7vlo=0.0499 s7vhi=0.55 )
.model DO74244_4_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=0.91
+ s2name="1" s2vlo=0.91 s2vhi=7.0 )
.model DIN74244_4 dinput (
+ s0name="0" s0tsw=1.0ns s0rlo=163 s0rhi=7.5k
+ s1name="1" s1tsw=1.0ns s1rlo=2.65k s1rhi=146
+ s2name="X" s2tsw=1.0ns s2rlo=49.4 s2rhi=127
+ s3name="R" s3tsw=1.0ns s3rlo=49.4 s3rhi=127
+ s4name="F" s4tsw=1.0ns s4rlo=49.4 s4rhi=127
+ s5name="Z" s5tsw=1.0ns s5rlo=200K s5rhi=200K )
*-------------------244_5--(1.2 V <= VCC < 1.4 V)--------------------
.subckt 244_5 1OEBAR 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 DGND
+ 2A1 1Y4 2A2 1Y3 2A3 1Y2 2A4 1Y1 2OEBAR DPWR
+ params: MNTYMXDLY=0 IO_LEVEL=0
UAB inva(2) DPWR DGND
+ 1OEBAR 2OEBAR G1 G2
+ D0_GATE IO_244_5 IO_LEVEL={IO_LEVEL}
U1 buf3a(4) DPWR DGND

11. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
+ 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4
+ D_244_5 IO_244_5 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
U2 buf3a(4) DPWR DGND
+ 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4
+ D_244_5 IO_244_5 MNTYMXDLY={MNTYMXDLY}
+ IO_LEVEL={IO_LEVEL}
.ends
.model D_244_5 utgate (
+ tplhmn=3.0ns tplhty=41ns tplhmx=42ns
+ tphlmn=3.0ns tphlty=41.5ns tphlmx=42ns
+ tpzhmn=3.0ns tpzhty=47.7ns tpzhmx=49ns
+ tpzlmn=3.0ns tpzlty=48.2ns tpzlmx=49ns
+ tphzmn=3.0ns tphzty=27ns tphzmx=29ns
+ tplzmn=3.0ns tplzty=27ns tplzmx=29ns )
.model IO_244_5 uio (
+ drvh=35.3 drvl=46.9
+ inld=6pF
+ AtoD1="AtoD_244_5" AtoD2="AtoD_244_5_NX"
+ AtoD3="AtoD_244_5" AtoD4="AtoD_244_5_NX"
+ DtoA1="DtoA_244_5" DtoA2="DtoA_244_5"
+ DtoA3="DtoA_244_5" DtoA4="DtoA_244_5"
+ tswhl1=529ps tswlh1=695ps
+ tswhl2=513ps tswlh2=718ps
+ tswhl3=529ps tswlh3=695ps
+ tswhl4=513ps tswlh4=718ps
+ DIGPOWER="DIGIFPWR" tpwrt=2.9ns )
.subckt AtoD_244_5 A D DPWR DGND
+ params: CAPACITANCE=0
X1 DGND A VCX_CLAMP
X2 A DPWR VCX_CLAMP
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74244_5 DGTLNET=D IO_244_5
C1 A DGND {CAPACITANCE+0.1pF}
D0 DGND a D74SCLMP
D1 1 2 D74
D2 2 DGND D74
D3 3 1 D74
D4 3 A D74
D5 1 a D74S
R1 DPWR 3 3700k
.ends
.subckt AtoD_244_5_NX A D DPWR DGND
+ params: CAPACITANCE=0
ENORM NORM DGND VALUE={V(A,DGND)/(V(DPWR,DGND)+1U)}
O0 NORM DGND DO74244_5_NX DGTLNET=D IO_244_5
C1 A DGND {CAPACITANCE+0.1pF}
D0 DGND a D74SCLMP
D1 1 2 D74
D2 2 DGND D74
D3 3 1 D74
D4 3 A D74
D5 1 a D74S

12. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
R1 DPWR 3 3700k
.ends
.subckt DtoA_244_5 D A DPWR DGND
+ params: DRVL=0 DRVH=0 CAPACITANCE=0
N1 A DGND DPWR DIN74244_5 DGTLNET=D IO_244_5
C1 A DGND {CAPACITANCE+0.1pF}
.ends
.model DO74244_5 doutput (
+ s0name="X" s0vlo=0.0499 s0vhi=0.8
+ s1name="0" s1vlo=-0.2 s1vhi=0.0499
+ s2name="R" s2vlo=0.0499 s2vhi=0.55
+ s3name="R" s3vlo=0.45 s3vhi=0.8
+ s4name="X" s4vlo=0.0499 s4vhi=0.8
+ s5name="1" s5vlo=0.8 s5vhi=1.3
+ s6name="F" s6vlo=0.45 s6vhi=0.8
+ s7name="F" s7vlo=0.0499 s7vhi=0.55 )
.model DO74244_5_NX doutput (
+ s0name="0" s0vlo=-1.5 s0vhi=0.96
+ s2name="1" s2vlo=0.96 s2vhi=7.0 )
.model DIN74244_5 dinput (
+ s0name="0" s0tsw=1.0ns s0rlo=11.5 s0rhi=280
+ s1name="1" s1tsw=1.0ns s1rlo=400 s1rhi=35
+ s2name="X" s2tsw=1.0ns s2rlo=49.4 s2rhi=127
+ s3name="R" s3tsw=1.0ns s3rlo=49.4 s3rhi=127
+ s4name="F" s4tsw=1.0ns s4rlo=49.4 s4rhi=127
+ s5name="Z" s5tsw=1.0ns s5rlo=200K s5rhi=200K
+ )
*$

13. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
OE An Yn (Measurement) Yn (Simulation)
%Error
L L L L 0
Time
0s 0.5us 1.0us
V(U1:1Y1) V(U1:1Y2) V(U1:1Y3) V(U1:1Y4) V(U1:2Y1)
V(U1:2Y2) V(U1:2Y3) V(U1:2Y4)
0V
2.0V
4.0V
0s 0.5us 1.0us
1:1OEBAR
1:2OEBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
0
0
0
0
0
0
0
0
0
0
R1
1MEG
LO
LO
LO
V1
3.6
LO
LO
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
LO
LO
LO
LO
0

14. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
OE An Yn (Measurement) Yn (Simulation)
%Error
L H H H 0
Time
0s 0.5us 1.0us
V(U1:1Y1) V(U1:1Y2) V(U1:1Y3) V(U1:1Y4) V(U1:2Y1)
V(U1:2Y2) V(U1:2Y3) V(U1:2Y4)
0V
2.0V
4.0V
0s 0.5us 1.0us
1:1OEBAR
1:2OEBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
0
0
1
1
1
1
1
1
1
1
HI
HI
LO
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
HI
0
HI
HI
V1
3.6
R1
1MEG
HI
HI
HI

15. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Truth Table
Circuit simulation result
Evaluation circuit
Comparison table
Input Output
OE An Yn (Measurement) Yn (Simulation)
%Error
H X Z Z 0
Time
0s 0.5us 1.0us
V(1Y1) V(1Y2) V(1Y3) V(1Y4) V(2Y1) V(2Y2) V(2Y3)
V(2Y4)
0V
1.0V
2.0V
3.0V
0s 0.5us 1.0us
1:1OEBAR
1:2OEBAR
U1:1A1
U1:1A2
U1:1A3
U1:1A4
U1:2A1
U1:2A2
U1:2A3
U1:2A4
1
1
1
1
1
1
1
1
1
1
1Y3
2Y1
2Y4 1Y1
X
HI
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
CLK
DSTM1
OFFTIME = .2uS
ONTIME = .2uS
2Y3
V1
3.6
HI
1Y4
2Y2
X
0
1Y2
R1
1MEG

16. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage (2.7 V < VCC ≤ 3.6 V)
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 3.3 V Measurement Simulation %Error
VIH (V) 2 2 0
VIL (V) 0.8 0.799082 -0.115
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
2.0V
4.0V
(560.609u,2.0001)
(524.215u,799.082m)
Output
Input
LO
V2
3.3
0
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
OUT
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 3.3 R1
1G

17. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage (2.3 V ≤ VCC ≤ 2.7 V)
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 2.5 V Measurement Simulation %Error
VIH (V) 1.6 1.6 0
VIL (V) 0.7 0.699080 -0.131
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
1.0V
2.0V
3.0V
(563.998u,1.6000)
(527.963u,699.080m)
Output
Input
V2
2.5
0
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
R1
1G
LO
OUT
LO
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 2.5

18. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage (1.65 V ≤ VCC < 2.3 V)
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 1.8 V Measurement Simulation %Error
Min VIH = (VCC*0.65) (V) 1.17 1.1702 0.017
Max VIL = (VCC*0.2) (V) 0.36 0.358320 -0.467
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
1.0V
2.0V
(565.008u,1.1702)
(519.907u,358.320m)
Output
Input
V2
1.8
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
OUT
0
LO
LO
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 1.8 R1
1G

19. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage (1.4 V ≤ VCC < 1.65 V)
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 1.5 V Measurement Simulation %Error
Min VIH = (VCC*0.65) (V) 0.975 0.975248 0.025
Max VIL = (VCC*0.05) (V) 0.075 0.074927 -0.097
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
0.5V
1.0V
1.5V
(565.017u,975.248m)
(504.995u,74.927m)
Output
Input
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
OUT
LO
0
V2
1.5
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 1.5 R1
1G

20. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level and Low Level Input Voltage (1.2 V ≤ VCC < 1.4 V)
Circuit simulation result
Evaluation circuit
Comparison table
VCC = 1.2 V Measurement Simulation %Error
Min VIH = (VCC*0.8) (V) 0.96 0.9605 0.052
Max VIL = (VCC*0.05) (V) 0.06 0.059885 -0.192
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(OUT) V(V1:+)
0V
0.4V
0.8V
1.2V
(580.042u,960.500m)
(504.990u,59.885m)
Output
Input
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
OUT
LO
0
V2
1.2
V1
TD = 0.5m
TF = 0.1m
PW = 1m
PER = 2m
V1 = 0
TR = 0.1m
V2 = 1.2 R1
1G

21. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level Output Voltage (2.7 V < VCC ≤ 3.6 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIH, VCC = 3.3 V Measurement Simulation %Error
Min VOH = (VCC - 0.2) V 3.1 3.1176 0.568
Time
0s 5ms 10ms
V(OUT)
0V
1.0V
2.0V
3.0V
Output
V1
2.1
OUT
I1
-100u
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
0
V2
3.3
LO
LO

22. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Low Level Output Voltage (2.7 V < VCC ≤ 3.6 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIL, VCC = 3.3 V Measurement Simulation %Error
VOL (V) 0.2 0.207763 3.882
Time
0s 5ms 10ms
V(OUT)
0V
1.0V
2.0V
3.0V
OUT
V1
0.7
LO
V2
3.3
0
I1
100u
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
LO
Output

23. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level Output Voltage (2.3 V ≤ VCC ≤ 2.7 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIH, VCC = 2.5 V Measurement Simulation %Error
Min VOH = (VCC - 0.2) V 2.3 2.3257 1.117
Time
0s 5ms 10ms
V(OUT)
0V
1.0V
2.0V
2.5V
Output
0
V1
1.7
LO
LO
V2
2.5
OUT
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
I1
-100u

24. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Low Level Output Voltage (2.3 V ≤ VCC ≤ 2.7 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIL, VCC = 2.5 V Measurement Simulation %Error
VOL (V) 0.2 0.202055 1.028
Time
0s 5ms 10ms
V(OUT)
0V
1.0V
2.0V
2.5V
OUT
LO
I1
100u
0
V2
2.5
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
V1
0.6
LO
Output

25. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level Output Voltage (1.65 V ≤ VCC < 2.3 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIH, VCC = 1.8 V Measurement Simulation %Error
Min VOH = (VCC - 0.2) V 1.6 1.6184 1.150
Time
0s 5ms 10ms
V(OUT)
0V
0.5V
1.0V
1.5V
Output
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
LO
V1
1.2
LO
I1
-100u
0
OUT
V2
1.8

26. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Low Level Output Voltage (1.65 V ≤ VCC < 2.3 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIL, VCC = 1.8 V Measurement Simulation %Error
VOL (V) 0.2 0.198 -1
Time
0s 5ms 10ms
V(OUT)
0V
0.5V
1.0V
1.5V
V2
1.8
I1
100u
V1
0.3
OUT
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
0
LO
Output

27. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level Output Voltage (1.4 V ≤ VCC < 1.65 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIH, VCC = 1.5 V Measurement Simulation %Error
Min VOH = (VCC - 0.1) V 1.4 1.4078 0.557
Time
0s 5ms 10ms
V(OUT)
0V
0.5V
1.0V
1.5V
Output
V1
0.985
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
0
LO
V2
1.5
LO
OUT
I1
-100u

28. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Low Level Output Voltage (1.4 V ≤ VCC < 1.65 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIL, VCC = 1.5 V Measurement Simulation %Error
VOL (V) 0.05 0.04786 -4.28
Time
0s 5ms 10ms
V(OUT)
0V
0.5V
1.0V
1.5V
OUT
LO
LO
0
I1
100u
V1
0.07
V2
1.5
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
Output

29. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
High Level Output Voltage (1.2 V ≤ VCC < 1.4 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIH, VCC = 1.2 V Measurement Simulation %Error
Min VOH = (VCC - 0.1) V 1.1 1.1002 0.018
Time
0s 5ms 10ms
V(OUT)
0V
0.4V
0.8V
1.2V
Output
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
0
LO
LO
I1
-100u
V1
0.97
V2
1.2
OUT

30. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Low Level Output Voltage (1.2 V ≤ VCC < 1.4 V)
Circuit simulation result
Evaluation circuit
Comparison table
VIN = VIL, VCC = 1.2 V Measurement Simulation %Error
VOL (V) 0.05 0.048446 -3.108
Time
0s 5ms 10ms
V(OUT)
0V
0.4V
0.8V
1.2V
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
V2
1.2
V1
0.05
I1
100u
LO
OUT
LO
0
Output

31. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time ( VCC = 1.2 V)
Circuit simulation result
Evaluation circuit
Comparison table CL = 15 pF, RL = 2 KΩ
VCC = 1.2 V, tr = tf = 2 ns Measurement Simulation %Error
tpLH (ns) 42 41.898 -0.243
tpHL (ns) 42 41.570 -1.024
Time
0s 0.5us 1.0us
1 V(tplh_tphl) 2 V(V1:+)
0V
0.4V
0.8V
1.2V
1
0V
1.2V
2
>>
Output
Input
V2
1.2
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
LO
R1
2k
0
C1
15p
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.2
tplh_tphl

32. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time ( VCC = 1.5 V)
Circuit simulation result
Evaluation circuit
Comparison table CL = 15 pF, RL = 2 KΩ
VCC = 1.5 V, tr=tf= 2 ns Measurement Simulation %Error
tpLH (ns) 16.8 16.565 -1.399
tpHL (ns) 16.8 16.616 -1.095
Time
0s 0.5us 1.0us
1 V(tplh_tphl) 2 V(V1:+)
0V
0.5V
1.0V
1.5V
1
0V
1.5V
2
>>
Output
Input
V2
1.5
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
LO
R1
2k
0
C1
15p
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.5
tplh_tphl

33. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time ( VCC = 1.8 V)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC = 1.8 V, tr=tf= 2 ns Measurement Simulation %Error
tpLH (ns) 8.4 8.2821 -1.404
tpHL (ns) 8.4 8.3285 -0.851
Time
0s 0.5us 1.0us
1 V(tplh_tphl) 2 V(V1:+)
0V
1.0V
2.0V
1
0V
1.5V
2.0V
2
>>
Output
Input
V2
1.8
LO
C1
30p
0
tplh_tphl
R1
500
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.8
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244

34. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time ( VCC = 2.5 V)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC = 2.5 V, tr=tf= 2 ns Measurement Simulation %Error
tpLH (ns) 4.2 4.1775 -0.536
tpHL (ns) 4.2 4.1338 -1.576
Time
0s 0.5us 1.0us
1 V(tplh_tphl) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
0V
1.5V
3.0V
2
>>
Output
Input
LO
R1
500
V2
2.5
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 2.5
0
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
LO
C1
30p
tplh_tphl

35. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Propagation Delay Time ( VCC = 3.3)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC = 3.3 V, tr=tf= 2 ns Measurement Simulation %Error
tpLH (ns) 3.5 3.457 -1.229
tpHL (ns) 3.5 3.4915 -0.243
Time
0s 0.5us 1.0us
1 V(tplh_tphl) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
0V
1.5V
3.0V
2
>>
Output
Input
V2
3.3
LO
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
C1
30p
LO
R1
500
0
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 2.7
tplh_tphl

36. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time(tPZH) and Output disable time(tPHZ) ( VCC = 1.2)
Circuit simulation result
Evaluation circuit
Comparison table CL = 15 pF, RL = 2 kΩ
VCC =1.2 V, tr=tf= 2 ns Measurement Simulation %Error
tPHZ (ns) 29 28.866 -0.462
tpZH (ns) 49 48.920 -0.163
Time
0s 0.5us 1.0us
1 V(TPZH_TPHZ) 2 V(V1:+)
0V
0.4V
0.8V
1.2V
1
0V
0.4V
0.8V
1.2V
2
>>
Output
Input
tpzh_tphz
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
R1
2K
HI
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.2
C1
15p
R2
2K
V2
1.2
HI
0

37. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time(tPZH) and Output disable time(tPHZ) ( VCC = 1.5)
Circuit simulation result
Evaluation circuit
Comparison table CL = 15 pF, RL = 2 kΩ
VCC =1.5 V, tr=tf= 2 ns Measurement Simulation %Error
tPHZ (ns) 11.6 11.335 -2.284
tpZH (ns) 19.6 19.540 -0.306
Time
0s 0.5us 1.0us
1 V(TPZH_TPHZ) 2 V(V1:+)
0V
0.5V
1.0V
1.5V
1
0V
0.5V
1.0V
1.5V
2
>>
Output
Input
V2
1.5
HI
R1
2K
R2
2K
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
HI
0
tpzh_tphz
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.5
C1
15p

38. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time(tPZH) and Output disable time(tPHZ) ( VCC = 1.8)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC =1.8 V, tr=tf= 2 ns Measurement Simulation %Error
tPHZ (ns) 5.8 5.7099 -1.553
tpZH (ns) 9.8 9.758 -0.429
Time
0s 0.5us 1.0us
1 V(TPZH_TPHZ) 2 V(V1:+)
0V
0.5V
1.0V
1.5V
1
0V
1.0V
2.0V
2
>>
Output
Input
tpzh_tphz
R2
500
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.8
C1
30p
HI
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
R1
500
HI
V2
1.8
0

39. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time(tPZH) and Output disable time(tPHZ) ( VCC = 2.5)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC =2.5 V, tr=tf= 2 ns Measurement Simulation %Error
tPHZ (ns) 3.2 3.2053 0.166
tpZH (ns) 5.5 5.4764 -0.429
Time
0s 0.5us 1.0us
1 V(TPZH_TPHZ) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
0V
1.0V
2.0V
3.0V
2
>>
Output
Input
HI
V2
2.5
HI
R2
500
tpzh_tphz
C1
30p
R1
500
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 2.5
0

40. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time(tPZH) and Output disable time(tPHZ) ( VCC = 3.3)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC = 3.3 V, tr=tf= 2 ns Measurement Simulation %Error
tPHZ (ns) 3 2.9521 -1.597
tpZH (ns) 4.5 4.4339 -1.469
Time
0s 0.5us 1.0us
1 V(TPZH_TPHZ) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
0V
1.0V
2.0V
3.0V
2
>>
Output
Input
0
C1
30p
HI
tpzh_tphz
R2
500
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 2.7
R1
500
HI
V2
3.3

41. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time (tPZL) and Output disable time (tPLZ) ( VCC = 1.2)
Circuit simulation result
Evaluation circuit
Comparison table CL = 15 pF, RL = 2 kΩ
VCC =1.2 V, tr=tf= 2 ns Measurement Simulation %Error
tPLZ (ns) 29 28.524 -1.641
tpZL (ns) 49 48.294 -1.441
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
1.0V
1
0V
1.0V
2
>>
Output
Input
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.2
V2
2.4
C1
15p
tpzl_tplzHI
V3
1.2
R2
2k
LO
R1
2k
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
0

42. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time (tPZL) and Output disable time (tPLZ) ( VCC = 1.5)
Circuit simulation result
Evaluation circuit
Comparison table CL = 15 pF, RL = 2 kΩ
VCC =1.5 V, tr=tf= 2 ns Measurement Simulation %Error
tPLZ (ns) 11.6 11.518 -0.707
tpZL (ns) 19.6 19.395 -1.046
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
1.0V
1.5V
1
0V
1.0V
1.5V
2
>>
Output
Input
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
0
R2
2k
V3
1.5
HI
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.5
C1
15p
tpzl_tplzLO
V2
3
R1
2k

43. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time (tPZL) and Output disable time (tPLZ) ( VCC = 1.8)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC =1.8 V, tr=tf= 2 ns Measurement Simulation %Error
tPLZ (ns) 5.8 5.7361 -1.102
tpZL (ns) 9.8 9.746 -0.551
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
1.0V
2.0V
1
0V
1.0V
2.0V
2
>>
Output
Input
V2
3.6
R1
500
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 1.8
LO
C1
30p
HI
V3
1.8
0
tpzl_tplz
R2
500

44. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time (tPZL) and Output disable time (tPLZ) ( VCC = 2.5)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC = 2.5 V, tr=tf= 2 ns Measurement Simulation %Error
tPLZ (ns) 3.2 3.1922 -0.244
tpZL (ns) 5.5 5.4955 -0.082
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
0V
1.0V
2.0V
3.0V
2
>>
Output
Input
0
C1
30p
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 2.5
R1
500
HI
R2
500
tpzl_tplz
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
LO
V2
5
V3
2.5

45. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
Output enable time (tPZL) and Output disable time (tPLZ) ( VCC = 3.3)
Circuit simulation result
Evaluation circuit
Comparison table CL = 30 pF, RL = 500 Ω
VCC = 3.3 V, tr=tf= 2 ns Measurement Simulation %Error
tPLZ (ns) 3 3.0229 0.763
tpZL (ns) 4.5 4.4805 -0.433
Time
0s 0.5us 1.0us
1 V(TPZL_TPLZ) 2 V(V1:+)
0V
1.0V
2.0V
3.0V
1
0V
1.0V
2.0V
3.0V
2
>>
Output
Input
R1
500
0
1A1
2Y4
1A3
1OE
1A4
2Y1 1Y4
__
2OE
2A4
2Y2
2A3
1Y3
1Y1
1A2
2A2
GND 2A1
1Y2
__
VCC
2Y3
U1
74VCX244
HI
C1
30p
R2
500
V1TD = 0.2u
TF = 2.5n
PW = 0.5u
PER = 1u
V1 = 0
TR = 2.5n
V2 = 2.7
V2
6
LO tpzl_tplz
V3
3.3