The document discusses priority assignment for tasks and direct memory access (DMA) transactions on a multiprocessor system-on-chip (MPSoC) platform. It proposes several approaches for priority assignment, including workload-based fixed priority, bandwidth-based dynamic priority, and simulated annealing. It also describes models for tasks, DMA transactions, and the system, and evaluates schedulability using concepts like contention intervals. The goal is to maximize bus utilization while meeting timing constraints.

1. 多核心匯流排與直接存取記憶體之優先權配置
Priority Assignment
on the MPSoC with DMAC
Presenter: Shih-Peng Yu
Professor: Ya-Shu Chen
Department of Electrical Engineering,
National Taiwan University of Science and Technology
M10007411@mail.ntust.edu.tw
2013/10/04

2. Outline
• Introduction
• Related work
• Problem definition
• Approach
• Experimental result
• Conclusions
2

3. Introduction
 Embedded system
 Peripheral device
• Camera
• Display
• Storage
3

4. Direct memory access control(DMAC)
 Direct memory access(DMAC)
Transfer data without core
 Transfer type
• Memory to memory
• Memory to peripheral devices
L1 Memory
L3 Memory
L2 Memory
Device1
Device n
.
.
.
.
.
4

5. Introduction
UART Transfer Data
(kbps)
CPU Idle rate (%)
No DMA
CPU Idle rate (%)
With DMA
Can’t work
Can’t work
Can’t work
A B
[1] Sachin Gupta and Lakshmi Natarajan‘Optimizing Embedded Applications using DMA,” Published in EE Times Design
 DMAC is powerful to improve the system performance.
• Increase core idle time (A)
• Decrease system power (B) [1]
5

6. Motivation
Bus: Which master can be serviced first?
DMAC : Which device can be serviced first?
6
BUS
C𝟎 C𝟏
DMAC
𝐷0 𝐷1 𝐷2
Memory
C𝒏
BUS
Arbiter
𝐷𝑛

7. Motivation
BUS Priority : DMAC>C0>C1
BUS Priority : C0>C1>DMAC
7
T1,1
(2) I1,2
(3)
T1,3
(2)
T1,0
(5)
(4)
(4)
𝐓𝟏
𝐝𝟏=30
𝐃𝟎
T2,0
(5)
I2,1
(2)
T2,2
(7)
T2,3
(6)
𝐝𝟐=30
𝐓𝟐
(3)
(3)
𝐃𝟎
1
CE
1,3
2
DE0,1
(7)
1
DE
0,2
(7)

8. Related work
8
[2] Ya-Shu Chen, Song-Jian Tang and Shi-Wu Lo,“A Priority Assignment Strategy of Processing Elementsover an On-Chip Bus,”
Proceedings of the 2007 ACM symposium on Applied computing May 3, 2007
[3] Pi-Cheng Hsiu, Member’’Multilayer Bus Optimization for Real-Time Embedded Systems ,” Computers, IEEE Transactions on
(Volume:61 , Issue: 11 ) ,Nov. 2012
 Priority assignment
• Ya-Shu Chen, [2] propose a priority assignment strategy based
on Simulated Annealing (SA) to minimize the number of
priorities for each PE’s.
• Pi-Cheng Hsiu, [3] propose a dynamic-programming approach
for scheduling real-time tasks with precedence constraints to
minimizing the communication cost in multilayer bus embedded
systems.

9. Related work
9
[4] Joosun Hahn,Rhan Ha,Sang Lyul Min,Jane W.-S. Liu,’’ Analysis of Worst Case DMA Response Time in a Fixed-Priority Bus
Arbitration Protocol,” Journal Real-Time Systems Volume 23, Issue 3 , pp 209-238 , 2002-11-01
[5] Tai-Yi Huang, Chih-Chieh Chou, Po-Yuan Chen“Bounding the Execution Times of DMA I/O Tasks on Hard-Real-Time
Embedded Systems,” 9th International Conference, RTCSA, February 18-20, 2003
[6] Tai-Yi Huang,J. W.-S. Liu,Jen-Yao Chung’’ Allowing Cycle-Stealing Direct Memory Access I/O Concurrent with Hard-Real-
Time Programs ,” IEEE Computer Society Washington , 1996
 Response time analysis
• Joosun Hahn, [4] propose a technique for finding the worst case
response time (WCRT) of DMA request that is needed in the
schedulability analysis of a whole real-time system.
• Tai-Yi Huang, [5] presents a method for bounding the worst-
case execution time of a cycle-stealing DMA I/O task executing
concurrently with a set of CPU tasks on a single-processor
system.
• Tai-Yi Huang,[6] presents an analytical method for bounding
the WCET of a program executing concurrently with cycle-
stealing DMA I/O.

10. Problem definition
 Input：Task set and MPSoC architecture
 Output：Cores, DMAC and Devices priority assignment
 Constraint：Meet timing constrains
 Objective：Maximum the bus utilization
Bus utilization =
System exectuion time − BUS Idle Time
System exectuion time
10

11. System model
BUS
C𝟎 C𝟏
DMAC
𝐷0 𝐷1 𝐷2
Memory
C𝒏
BUS
Arbiter
𝐷𝑛

12. DMAC model
12
 Channels schedule
Arbiter controller
.
.
.
.
FIFO
Ch0
DMAC
D0
Memory
D1 Ch1
Dn Chn

13. Task model
13
T1.1
T1.2 T1.3 T1.4
T1.5
T1.7
𝐈𝟏.𝟔
T2.1
T2.2 T2.3
T2.5
𝐈𝟐.𝟒
C Subtask
D Subtask
CPU transmission(CE)
DMAC transmission(DE)
1
CE1,2
1
CE2,7
1
CE3,5
1
CE1,3
1
CE1,4
2
CE1,2
2
CE1,3
1
DE4,6
1
DE6,7
2
DE2,4
2
DE4,5
𝐝𝟏
𝐓𝟏
𝐝𝟐
𝐓𝟐

14. Approach
14
 Subtask assignment
• Subtask cluster [8] : Minimize number of data transaction
• Worst fit assignment : Balance the workload of tasks
 Priority assignment
• Workload-based (Fix priority)
• Bandwidth-based (Dynamic priority)
• SA
 Schedulability bound
• Priority order
• Distinct path
• Contention Interval
[8]Cyun-Yi Jheng, Ya-Shu Chen “On-line Real-Time Task Management for Three-dimensional Network on Chips,” Anti-Counterfeiting,
Security and Identification (ASID), 2012 International Conference ,July,13,2011

15. Subtask assignment
15
[8]Cyun-Yi Jheng, Ya-Shu Chen “On-line Real-Time Task Management for Three-dimensional Network on Chips,” Anti-
Counterfeiting, Security and Identification (ASID), 2012 International Conference ,July,13,2011
T1,1
(2)
T1,2
(7)
T1,3
(6)
T1,5
(3)
T1,6
(4)
T2,0
(2)
T2,1
(4)
T2,2
(2)
T2,3
(4)
I2,5
(6)
T2,6
(2)
T1,0
(4)
I1,4
(7)
T2,4
(2)
𝐝𝟐=80
𝐓𝟐
(3) (5)
(2)
(6)
(2)
(3)
(2)
(4)
(5) (5)
(5)
(2)
𝐓𝟏
𝐝𝟏=80
𝐃𝟎
𝐃𝟏

16. Subtask assignment
16
BUS
C0 C1
DMAC
𝐷0
Memory
BUS
Arbiter
𝐷1
Worst fit partition

17. Workload-based
17
 For fix arbiter
 Setting the workload of every data transaction
 The urgency level is directly proportional to the workload value.
 The priority order of master is highest, if the master has large workload
value
Wtransaction =
CTi,j
+ CEi,j
𝑇𝑑
WMaster = Wtransaction
CTi,j
: Execution time of Subtask
CEi,j
:Execution time of data transaction
𝑇𝑑 : Task deadline

18. Workload-based
18
T1,1
(2)
T1,2
(7)
T1,3
(6)
T1,5
(3)
T1,6
(4)
T2,0
(4)
T2,1
(4)
T2,2
(2)
T2,3
(4)
I2,5
(6)
T2,6
(4)
T1,0
(4)
I1,4
(7)
T2,4
(2)
1
CE0,1
(2)
2
CE0,2
(4)
1
DE2,4
(6) 2
DE2,5
(5)
2
DE5,6
(3)
1
CE3,6
(2)
𝐃𝟎
𝐓𝟏
𝐝𝟏=30
𝐓𝟐
𝐝𝟐=30
𝐃𝟏
C0 =
2+2+6+3+2+4
30
= 0.633
C1 =
2+4
30
+
4+2+5+6+3+4
30
= 1
D0 =
6+7
30
= 0.433
D1 =
5+6+3+4
30
+
3+4
30
=0.833
DMAC = D0 + D1 = 1.266
Priority : DMAC >𝐶1 >𝐶0
Priority: 𝐷1> 𝐷0

19. Scheduability test
19
ST𝑃 =
Tsump
dP − (Comm + Cont)p
Schedulable: 0<STP<1
Compare contention :
1.Priority order
2.Distinct path
3.Contention Interval
-ASAP(Start time)
-ALAP(End time)
Tsum:Total execution time of subtask on the path
dp: Path deadline
Comm: Data transaction time
Cont: Contention time
T1,1
(2)
T1,2
(7)
T1,3
(6)
T1,5
(3)
T1,6
(4)
T1,0
(4)
I1,4
(7)
1
CE0,1
(2)
1
DE2,4
(6)
1
CE3,6
(2)
𝐃𝟎
𝐓𝟏
𝐝𝟏=30

20. Scheduability test
20
Compare contention :
1.Priority order
2.Distinct path
and on different path
3.Contention Interval
T1,1
(2)
T1,2
(7)
T1,3
(6)
T1,5
(3)
T1,6
(4)
T2,0
(4)
T2,1
(4)
T2,2
(2)
T2,3
(4)
I2,5
(6)
T2,6
(4)
T1,0
(4)
I1,4
(7)
T2,4
(2)
1
CE0,1
(2) 2
CE0,2
(4)
1
DE2,4
(6) 2
DE2,5
(5)
2
DE5,6
(3)
1
CE3,6
(2)
𝐃𝟎
𝐓𝟏
𝐝𝟏=30
𝐓𝟐
𝐝𝟐=30
𝐃𝟏
1
CE0,1
2
CE
0,2
<
1
CE0,1
2
CE0,2
A B
Start
Time
End
Time
A 4 14
B 4 10

21. Bandwidth-based
21
 For the dynamic bus arbiter [7] and the dynamic DMAC [8]
 Server Size Setting
𝐁𝐔𝐒 𝐦𝐚𝐬𝐭𝐞𝐫 𝐬𝐞𝐫𝐯𝐞𝐫 𝐬𝐢𝐳𝐞 =
𝐌𝐚𝐬𝐭𝐞𝐫 𝐰𝐨𝐫𝐤 𝐥𝐨𝐚𝐝
𝐁𝐔𝐒 𝐰𝐨𝐫𝐤 𝐥𝐨𝐚𝐝
𝐃𝐞𝐯𝐢𝐜𝐞 𝐬𝐞𝐫𝐯𝐞𝐫 𝐬𝐢𝐳𝐞 =
𝐃𝐞𝐯𝐢𝐜𝐞 𝐰𝐨𝐫𝐤 𝐥𝐨𝐚𝐝
𝐃𝐌𝐀𝐂 𝐰𝐨𝐫𝐤 𝐥𝐨𝐚𝐝
[7] Eric S. Collins, Reginald J. Hill, Brett L. Lindsley‘Dynamic bus arbitration priority and task switching based on shared memory fullness in a
multi-processor system” , Motorola, Inc.,US 09/089,721,12/5 2000
[8] Steven E. Olson, Jhy-Ping Shaw‘High speed dynamic chaining of DMA operations without suspending a DMA controller or incurring race
conditions.” , Oak Technology, US 09/130,885, 3/06 2001
According to work load

22. Bandwidth-based
22
 Deadline setting [9]
 According to the deadline value to determine the service
order
𝐄𝐝 = 𝐦𝐚𝐱 𝐓𝐀𝐫𝐫𝐢𝐯𝐚𝐥 , 𝐄′𝐝 +
𝐄𝐞
𝐔𝐒
[ [9] Marco Spuri , Giorgio Buttazzo ‘ Scheduling Aperiodic Tasks in Dynamic Priority.” , journal Real-Time Systems , July. 1996
𝐄𝐝:The deadline of data transaction
𝐓𝐀𝐫𝐫𝐢𝐯𝐚𝐥 : Arrival time of data transaction
𝐄′𝐝: The deadline of previous data transaction
𝐄𝐞: The execution time of data transaction
𝐔𝐒 : The sever size

23. Bandwidth-based
23
Work Load:
C0 : 0.633
C1 : 1
D0 : 0.433
D1 : 0.833
DMAC Total Work Load=0.433+0.833=1.266
BUS Total Work Load=0.633+1+1.266=2.899
Server size:
C0 : 0.633
2.899
= 0.22
C1 :
1
2.899
= 0.34
DMAC :
1.266
2.899
= 0.44
D0 :
0.433
1.266
= 0.34
D1 :
0.833
1.266
= 0.66

24. Bandwidth-based
24
2
CE0,2
1
CE0,1
: max 4,0 +
4
0.34
=15
: max 4,0 +
2
0.22
=13
Deadline assignment:
Server size:
C0 : 0.633
2.899
= 0.22
C1 :
1
2.899
= 0.34
DMAC :
1.266
2.899
= 0.44
D0 :
0.433
1.266
= 0.34
D1 :
0.833
1.266
= 0.66

25. SA algorithm
25
 Initial state
Workload-based priority assignment
 Perturbation strategy
• Swap bus master priority order(Cores and DMAC)
• Swap DMAC master priority order (Devices)
 Energy function
Bus utilization =
System execution time − BUS Idle Time
System execution time

26. Experimental setting
26
 Input
• By TGFF [10]
Degree (in, out)=(2,3)
Number of task set=1000
Number of task=1~5
Number of subtask =20~80
• SA Setting
Initial temperature : 100
End temperature : 20
Iteration : 25
𝜌=0.9
[10]R. P. Dick, D. L. Rhodes, and W. Wolf. Tgff: task graphs for free. In
Proceedings of the 6th international workshop on Hardware/software codesign,
CODES/CASHE ’98, pages 97–101, Washington, DC, USA, 1998. IEEE
Computer Society.
Performance metrics
•Bus utilization
•Meet ratio
•Algorithm Time
Comparison
Cycle stealing

27. Experimental result
27
Variation of core number
• Device : 2
• IO-ratio : 0.3

28. Experimental result
28
Variation of core number
• Device : 2
• IO-ratio : 0.3

29. Experimental result
29

30. Experimental result
30
Variation of ratio of device numbers
• Core : 4
• IO-ratio : 0.3

31. Experimental result
31

32. Experimental result
Variation of device tasks
• Core : 4
• Device: 2
32

33. Experimental result
Variation of device tasks
• Core : 4
• Device: 2
33

34. Experimental result
34
Optimum-near
• Core : 4
• Device:2
• IO-Ratio : 0.3

35. Experimental result
35
Optimum-near
• Core : 4
• Device:2
• IO-Ratio : 0.3

36. Experimental result
Variation of iteration setting
• Core : 4
• Device:2
• IO-Ratio : 0.3
36

37. Conclusions
 Priority Assignment on the MPSoC with DMA
• Precedence constraint scheduling
• Core and DMAC priority setting
• Device priority setting
 We propose
• Workload-based
• Bandwidth-based
• SA
 Future work
• Multi/Multilayer Bus
• Energy aware
37

38. References
[1] Sachin Gupta and Lakshmi Natarajan‘Optimizing Embedded Applications using DMA.” Published in EE
Times Design
[2] Ya-Shu Chen, Song-Jian Tang and Shi-Wu Lo “A Priority Assignment Strategy of Processing Elementsover
an On-Chip Bus,”, Proceedings of the 2007 ACM symposium on Applied computing May 3, 2007
[3] Pi-Cheng Hsiu, Member’’ Multilayer Bus Optimization for Real-Time Embedded Systems ,” Computers,
IEEE Transactions on (Volume:61 , Issue: 11 ) ,Nov. 2012
[4] Joosun Hahn,Rhan Ha,Sang Lyul Min,Jane W.-S. Liu,’’Analysis of Worst Case DMA Response Time in a
Fixed-Priority Bus Arbitration Protocol,” Journal Real-Time Systems Volume 23, Issue 3 , pp 209-238 , 2002-
11-01
[5] Tai-Yi Huang, Chih-Chieh Chou, Po-Yuan Chen“Bounding the Execution Times of DMA I/O Tasks on Hard-
Real-Time Embedded Systems,” 9th International Conference, RTCSA, February 18-20, 2003
[6] Tai-Yi Huang,J. W.-S. Liu,Jen-Yao Chung’’Allowing Cycle-Stealing Direct Memory Access I/O Concurrent
with Hard-Real-Time Programs ,” IEEE Computer Society Washington , 1996
[7] Eric S. Collins, Reginald J. Hill, Brett L. Lindsley‘Dynamic bus arbitration priority and task switching based
on shared memory fullness in a multi-processor system” , Motorola, Inc.,US 09/089,721,12/5 2000
[8] Steven E. Olson, Jhy-Ping Shaw‘High speed dynamic chaining of DMA operations without suspending a
DMA controller or incurring race conditions.” , Oak Technology, US 09/130,885, 3/06 2001
[9] Marco Spuri , Giorgio Buttazzo ‘ Scheduling Aperiodic Tasks in Dynamic Priority.” , journal Real-Time
Systems , July. 1996
[10]R. P. Dick, D. L. Rhodes, and W. Wolf. Tgff: task graphs for free. In Proceedings of the 6th international
workshop on Hardware/software codesign, CODES/CASHE ’98, pages 97–101, Washington, DC, USA, 1998.
IEEE Computer Society.
38

39. 39
Thanks for your attention!

40. Algorithm Time
40
Core 4 8 16 32 64
OPT 53.71 72576 3.766*
10^13
4.73*
10^35
2.283*
10^89
SA 89.84 89.84 92.341 90.239 89.487
BandWidth 0.004 0.004 0.003 0.004 0.004
WorkLoad 0.004 0.004 0.003 0.004 0.004
CYC 0.001 0.002 0.001 0.001 0.001

41. Introduction
41
Data transaction(E) (Execution Time , deadline)
E1(1,2)
E2(2,5)

42. Task Variation
42
Variation of tasks
• Core : 4
• Device:2
• IO-Ratio : 0.3

43. Task Variation
43
Variation of tasks
• Core : 4
• Device:2
• IO-Ratio : 0.3

44. In out Variation
44
Variation of in-out for subtask
• Core : 4
• Device:2
• IO-Ratio : 0.3

45. In out Variation
45
Variation of in-out for subtask
• Core : 4
• Device:2
• IO-Ratio : 0.3

46. Scheduability Test
46
Variation of in-out for subtask
• Core : 4
• Device:2
• IO-Ratio : 0.3

47. 47

48. 48

49. 多核心匯流排與直接存取記憶體之優先權配置
Priority Assignment
on the MPSoC with DMAC
Presenter: Shih-Peng Yu
Professor: Ya-Shu Chen
Department of Electrical Engineering,
National Taiwan University of Science and Technology
M10007411@mail.ntust.edu.tw
2013/10/04

50. Algorithm Time
50
Core 4 8 16 32 64
OPT 2445.5 4032000 2.09*
10^15
2.63*
10^37
1.26*
10^91
SA 523.11 526.24 524.712 525.184 524.69
BandWidth 0.016 0.016 0.016 0.017 0.016
WorkLoad 0.016 0.016 0.016 0.017 0.016
CYC 0.001 0.002 0.02 0.002 0.002