The document discusses an integer and logic unit used in microprocessors. It describes how the unit performs integer and logic operations like addition, multiplication, OR, and AND. It specifically mentions using a carry save adder for addition with 3 inputs and a Booth multiplier for high-speed multiplication. The document also provides details on an arithmetic logic unit (ALU), bus concept, input/output representation, interaction with other units, carry save adders, Booth multipliers, logic gates, and timing diagrams.

1. Group - P
Integer and Logic Unit by
8

2. Integer and Logic Unit
 Used for Integer and Logic Operations on
Microprocessor
 In our project:
1. Arithmetic- Addition and Multiplication
2. Logic- OR and AND
 Addition using Carry Save Adder
Issue- 3 inputs
 Multiplication using Booth Multiplier
High speed
2Seer Akademi (2011-13)

3. What is ALU?
• ALU stands for: Arithmetic Logic Unit.
ALU is a digital circuit that performs
Arithmetic (Add, Sub . . .) and Logical
(AND, OR, NOT) operations.
• John Von Neumann proposed the ALU in
1945 when he was working on EDVAC.
3Seer Akademi (2011-13)

4. Bus Concept
4Seer Akademi (2011-13)

5. I/O Representation
5Seer Akademi (2011-13)

6. Interaction with Other Units
Seer Akademi (2011-13) 6

7. Carry Save Adder:
• The basic CSA (carry save adder) is similar to the full
adder but the architecture is different.
• The operation and the principle of CSA is based on
formulae
A + B + C= SUM+2*CARRY
SUM=(A+B+C)mod2 and COUNT=((A+B+C)-
SUM)/2)
• For example if we add three numbers
X=0101,Y=0011,Z=0100.
• Sum=0010 and Saved Carry= 1010 was calculated in
CSA and next in the carry look adder/ ripple carry
adder the output new sum= 1100 and here new carry
is 0.
7Seer Akademi (2011-13)

8. Carry Save Adder
8Seer Akademi (2011-13)

9. Booth Multiplier –
Operation (step by step)
• mr-Multiplier,md-Multiplicand
• Shift md
• 2’s Complemet the md
• Shift md
• Encode the mr
• Partial product generation by addiing
shifting bits of md bits with respect to mr bits
• Final 3 stages of partial product generated
bits are added in end
Seer Akademi (2011-13) 9

10. 10
OR & AND
INPUT
A B
OUTPU
T
A + B
0 0 0
0 1 1
1 0 1
1 1 1
INPUT
OUTPU
T
A B
A AND
B
0 0 0
0 1 0
1 0 0
1 1 1
Seer Akademi (2011-13)

11. Timing Diagram
11Seer Akademi (2011-13)

12. 12
Queries
Seer Akademi (2011-13)

13. Fin
13Seer Akademi (2011-13)