13-11-2020 1Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Contact E-mail:
acdean@rmd.ac.in
kkthyagharajan@yahoo.com
kkthyagharajan@gmail.com
Dr. K.K. THYAGHARAJAN
Professor & Dean (Academic)
Department of Electronics and Communication Engineering
RMD ENGINEERING COLLEGE
Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Multiplication & Division Algorithms
Click on the links given below to view video
https://youtu.be/thC8B4B-PyY
https://youtu.be/m7JtcP5QmFA
https://youtu.be/NbfTKSm4ubM
https://youtu.be/RhiBtztCESI
13-11-2020 3Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
PART - 1
Modified Booth’s Algorithm for
Multiplication
13-11-2020 4Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Multiplication using bit-pair recoding
• Bit-pair recoding of multiplier is one of the modified Booth’s algorithm
• This speeds up multiplication process
• Reduces the number of summands to half.
Bit-pair recoding table Multiplier bit-pair Multiplier bit
on the right
Bit-pair recoded
bit at position i
i+1 i i-1
0 0 0 0
0 O 1 +1
0 1 0 +1
0 1 1 +2
1 0 0 -2
1 0 1 -1
1 1 0 -1
1 1 1 0
Remember this table
13-11-2020 5Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Multiplication using bit-pair recoding
B  Multiplicand ; Q  Multiplier
Bit-pair recoding is applied only to the multiplier
If multiplier is negative, take 2’s complement before recoding
Hint: Add one extra bit in addition to the number of bits required
to represent B or Q which ever is maximum.
Example: Recode the multiplier value 3 using bit-pair recoding.
Use 4 bits.
Convert to binary Add 0 near LSb Pair (3) bits Get code from
the table
Put the codes in proper places
Q  +3 
13-11-2020 6Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Multiplication using bit-pair recoding
Multiplicand B = -6 ; Multiplier Q = 3
Any negative number is represented using 2’s complement. Use 4 bits to
represent each number.
6  0110
-6  1’s complement + 1
Example 1 : Multiply -6 X 3 using bit-pair recoding method
8 4 2 1
0 1 1 0
1 0 0 1
1
1 0 1 0 B = 1010 = -6
Q = +3 = 0011
8 4 2 1
0 0 1 1
+6
Recoded Q
0 0 1 1 0
-1+1
13-11-2020 7Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Example 1: Contd. . . .
B = -6 =
Recoded Multiplier-Q
1 0 1 0
+1 -1
0 0 0 0 0 1 1 0
Multiplying -6 by -1 gives +6
i.e. 0110. Since this is +ve no.
extend the left sign bits by 0s
1 1 1 0 1 0
Multiply B by +1 and
shift left by 2 bits.
Since this is negative
number, extend the
left sign bits by 1s
1 1 1 0 1 1 1 0
13-11-2020 8Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Example 1: Contd. . . .
Since MSB is 1, the result is negative and the value is 2’s
complement of 1 1 1 0 1 1 1 0
0 0 0 1 0 0 0 1
1
0 0 0 1 0 0 1 0
1’s Complement
2’s Complement
128 64 32 16 8 4 2 1
0 0 0 1 0 0 1 0
Result is 16+2 = 18 i.e. -18
13-11-2020 9Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Multiplication using bit-pair recoding
Write the binary code of multiplicand & multiplier
Use same number of bits for both the values such that it is
the maximum number of bits required either by
multiplicand or by multiplier and add one more at the left
(MSB) for sign.
If any value is negative, represent it using 2’s complement
Find the recoded (bit-pair) values of multiplier by adding a
‘0’ at the right side. Extend the MSB if necessary.
If the recoded value has -1 or -2 , find out the 2’s
complement of the multiplicand for further use.
What do you have to understand?
13-11-2020 10Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Multiplication using bit-pair recoding
Multiplicand B = 13 ; Multiplier Q = -6
Any negative number is represented using 2’s complement. Use 5 bits (one for sign)
to represent each number because 13 requires 4 bits
Example 2 : Multiply 13 X -6 using bit-pair recoding method
16 8 4 2 1
0 0 1 1 0
1 1 0 0 1
1
1 1 0 1 0
Q = 11010 = -6
+6
Recoded Q
1 1 0 1 0
-2-1
6 = 00110
Q = -6 = (1S complement of +6 )+1
0
Sign bit
To bit-pair recode add a zero
near LSB , get table and get code
13-11-2020 11Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Multiplication using bit-pair recoding
B = +13 = 01101
16 8 4 2 1
0 1 1 0 1
Since the recoded multiplier has negative values, find out the 2’s complement of the
multiplicand (B) for future use
Sign bit
0 1 1 0 1B = +13
2’s complement
1 0 0 1 0
1
1 0 0 1 1- 13 1 0 0 1 1
1’s complement
13-11-2020 12Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Example 1: Contd. . . .
To multiply +13 by -2, Take the 2’s
complement of 13 shift left by one
bit and add 0 at the right
0 1 1 0 1
0 -1 -2
B= +13
Recoded Multiplier
1 1 1 1 1 0 0 1 1 0
To multiply +13 by -1, Take the 2’s
complement of 13. Put this two
positions left. Extend the sign bits
1 1 1 1 0 0 1 1
1 1 1 0 1 1 0 0 1 0
0 0 0 0 0 0multiply +13 by 0. Put this two
positions left
1
Since MSB is 1 the result is negative and the value is obtained by 2’s complement
13-11-2020 13Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Example 1: Contd. . . .
1 1 1 0 1 1 0 0 1 0
Since MSB is 1 the result is negative and the value is obtained by 2’s complement of
0 0 0 1 0 0 1 1 0 1 1’s complement
1
0 0 0 1 0 0 1 1 1 0 Result in binary
0 0 0 1 0 0 1 1 1 0
128 64 32 16 8 4 2 1
Result in decimal value
Result : -(64+8+4+2) = -78
─
13-11-2020 14Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
PART - 2
Division Algorithm
13-11-2020 15Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Binary Division
Manual Division
1001010
Dividend
/ 1000
Divisor
1000
0 0 0 1 0 0 1
1 0 0 1 0 1 0
1 0 0 0
1 0 1 0
1 0 0 0
0 0 1 0 Remainder
Quotient
Divisor has been shifted right
Quotient bit is shifted left and 1
or 0 is added in the right
13-11-2020 16Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Division-Hardware
Remainder
Quotient
Dividend
64-bit ALU
Shift Right
Shift Left
Write
Control
32 bits
64 bits
64 bits
64-bit Divisor register, 64-bit ALU, 64-bit Remainder register, and
32-bit Quotient register
Divisor
subtract
13-11-2020 17Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Division Algorithm
2b. Restore the original value by adding the
Divisor register to the Remainder register, &
place the sum in the Remainder register. Also
shift the Quotient register to the left, setting
the new least significant bit to 0.
Test
Remainder
Remainder < 0Remainder  0
Subtract the Divisor register from the
Remainder register, and place the result
in the Remainder register.
2a. Shift the Quotient
register to the left setting
the new rightmost bit to 1.
3. Shift the Divisor register right by 1 bit.
Done
Yes: n+1 repetitions )
Place Dividend in Remainder
n+1
repetition?
No: < n+1 repetitions
‘n’ is the number
of bits in the
quotient and
remainder
13-11-2020 18Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Division Algorithms
Dividend Divisor Quotient Remainder Sign of Quotient Sign of Remainder
+ + + + Quotient is positive if both
dividend & divisor have same
sign Remainder has
the same sign
as dividend
- - + -
+ - - + Quotient is negative if sign of
dividend is different from the
sign of the divisor- + - -
What do you have to remember?
 A-register is used to store remainder. It is initialized with zero and has one bit
more than the number of bits in the divisor.
 Initially dividend is stored in Q-register and after performing the division Q-
register holds Quotient.
 Divisor is stored in B-register. One extra ‘0’ is added as MSB
 If the operands are signed values, proceed assuming both as positive and at the
end assign signs as given in the above table.
13-11-2020 19Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Q0 = 0 ; A  A+B
Is
MSB of A = 1?
YesNo
A  0 ; Q  Dividend
B  Divisor ; SC  no_of_bits in the dividend
Q  1
SC  SC-1.
Stop
Yes
start
Is
SC<0?
No
Shift left A,Q
A  A-B
Restoring
Division
Algorithm
13-11-2020 20Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
SC
A Q
Steps Explanation
A4 A3 A2 A1 A0 Q3 Q2 Q1 Q0
4 0 0 0 0 0 1 0 1 0 Initial
3 0 0 0 0 1 0 1 0 SHL A,Q A-B = A+(-B)= A + 2’s complement of B
A  00001 + 11101 ; A = 111101 1 1 1 0 0 1 0 A A-B
0 0 0 0 1 0 1 0 0 MSB = 1; So A A+B ; Q0 =0 A  11110 + 00011 ; A= 1 00001
2 0 0 0 1 0 1 0 0 SHL A,Q A-B = A+(-B)= A + 2’s complement of B
A  00010 + 11101 ; A = 111111 1 1 1 1 1 0 0 A A-B
0 0 0 1 0 1 0 0 0 MSB = 1; So A A+B ; Q0 =0 A  11111 + 00011 ; A= 1 00010
1 0 0 1 0 1 0 0 0 0 SHL A,Q
0 0 0 1 0 0 0 0 A A-B A  00101 + 11101 ; A= 1 00010
0 0 0 1 0 0 0 0 1 MSB = 0; So Q0 =1
0 0 0 1 0 0 0 0 1 SHL A,Q
0 0 0 0 1 0 0 1 A A-B A  00100 + 11101 ; A= 1 00001
0 0 0 0 1 0 0 1 1 MSB = 0; So Q0 =1
Restoring Division Example 1: 1010 / 0011  10/3
A= 00000 ; Q=1010 (Dividend) ; B= 00011 (Divisor with MS bit) ; -B = 2’s Complement of B = 1’s complement of B +1 = 11100 +1 = 11101
Remainder = 1 Quotient = 3
13-11-2020 21Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
A  A+B
Is
MSB of A = 1?
YesNo
A  0 ; Q  Dividend
B  Divisor ; SC  no_of_bits in the dividend
Q0 = 1
SC  SC-1.
Stop
No
start
Is
SC<0?
No
Shift left A,Q
Non-Restoring
Division
Algorithm
Is
MSB of A = 1?
YesNo
A  A─B
Q0 = 0
Yes
Is
MSB of A = 1?
A  A+B
Yes
13-11-2020 22Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
SC
A Q
Steps Explanation
A4 A3 A2 A1 A0 Q3 Q2 Q1 Q0
4 0 0 0 0 0 1 0 1 0 Initial
3 0 0 0 0 1 0 1 0 SHL A,Q A-B = A+(-B)= A+ 2’s complement of B
A  00001 + 11101 ; A = 111101 1 1 1 0 0 1 0 0 MSB = 0; A A-B
Now MSB =1, so Q0 =0
2 1 1 1 0 0 1 0 0 SHL A,Q A  11100 + 00011 ; A= 11111
1 1 1 1 1 1 0 0 0 MSB =1 so A A+B
Now MSB =1, so Q0 =0
1 1 1 1 1 1 0 0 0 SHL A,Q
0 0 0 1 0 0 0 0 1 MSB =1 so A A+B
Now MSB =0, so Q0 =1
A  11111 + 00011
A= 1 00010
0 0 0 1 0 0 0 0 1 SHL A,Q
0 0 0 0 1 0 0 1 1 MSB = 0; A A-B
Now MSB =0, so Q0 =1
A  00100 + 11101 ; A= 1 00001
Non-Restoring Division Example 1: 1010 / 0011  10/3
A= 00000 ; Q=1010 (Dividend) ; B= 00011 (Divisor with MS bit) ; -B = 2’s Complement of B = 1’s complement of B +1 = 11100 +1 = 11101
Remainder = 1 Quotient = 3
13-11-2020 23Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
SC
A Q
Steps Explanation
A4 A3 A2 A1 A0 Q3 Q2 Q1 Q0
4 0 0 0 0 0 1 1 0 0 Initial
3 0 0 0 0 1 1 0 0 SHL A,Q A-B = A+(-B)= A+ 2’s complement of B
A  00001 + 11101 ; A = 111101 1 1 1 0 1 0 0 0 MSB = 0; A A-B
Now MSB =1, so Q0 =0
2 1 1 1 0 1 0 0 0 SHL A,Q A  11101 + 00011 ; A= 1 00000
0 0 0 0 0 0 0 0 1 MSB =1 so A A+B
Now MSB =0, so Q0 =1
1 0 0 0 0 0 0 0 1 SHL A,Q
1 1 1 0 1 0 0 1 0 MSB =0 so A A-B
Now MSB =1, so Q0 =0
A  00000+ 11101
A= 11101
0 1 1 0 1 0 0 1 0 SHL A,Q
1 1 1 0 1 0 1 0 0 MSB = 1; A A+B
Now MSB =1, so Q0 =0
A  11010 + 00011 ; A= 11101
1 1 1 0 1 0 1 0 0 MSB = 1; A A+B A  11101 + 00011; A=1 00000
Non-Restoring Division Example 2: -12 / +3  1100 / 0011 (don’t add any sign bit)
A= 00000 ; Q=1100 (Dividend) ; B= 00011 (Divisor with MS bit) ; -B = 2’s Complement of B = 1’s complement of B +1 = 11100 +1 = 11101
Remainder = 00000Quotient
13-11-2020 24Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Answer:
Remainder = 00000
Quotient = 0100
In this problem since the dividend is negative the
remainder will be negative (ref slide 18) i.e. -0 = 0
Since dividend & divisor have different signs, the
quotient is negative i.e. -4

PPT 2 - CA unit II 22 7-2020

  • 1.
    13-11-2020 1Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Contact E-mail: acdean@rmd.ac.in kkthyagharajan@yahoo.com kkthyagharajan@gmail.com Dr. K.K. THYAGHARAJAN Professor & Dean (Academic) Department of Electronics and Communication Engineering RMD ENGINEERING COLLEGE Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE Multiplication & Division Algorithms Click on the links given below to view video https://youtu.be/thC8B4B-PyY https://youtu.be/m7JtcP5QmFA https://youtu.be/NbfTKSm4ubM https://youtu.be/RhiBtztCESI
  • 2.
    13-11-2020 3Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE PART - 1 Modified Booth’s Algorithm for Multiplication
  • 3.
    13-11-2020 4Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Multiplication using bit-pair recoding • Bit-pair recoding of multiplier is one of the modified Booth’s algorithm • This speeds up multiplication process • Reduces the number of summands to half. Bit-pair recoding table Multiplier bit-pair Multiplier bit on the right Bit-pair recoded bit at position i i+1 i i-1 0 0 0 0 0 O 1 +1 0 1 0 +1 0 1 1 +2 1 0 0 -2 1 0 1 -1 1 1 0 -1 1 1 1 0 Remember this table
  • 4.
    13-11-2020 5Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Multiplication using bit-pair recoding B  Multiplicand ; Q  Multiplier Bit-pair recoding is applied only to the multiplier If multiplier is negative, take 2’s complement before recoding Hint: Add one extra bit in addition to the number of bits required to represent B or Q which ever is maximum. Example: Recode the multiplier value 3 using bit-pair recoding. Use 4 bits. Convert to binary Add 0 near LSb Pair (3) bits Get code from the table Put the codes in proper places Q  +3 
  • 5.
    13-11-2020 6Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Multiplication using bit-pair recoding Multiplicand B = -6 ; Multiplier Q = 3 Any negative number is represented using 2’s complement. Use 4 bits to represent each number. 6  0110 -6  1’s complement + 1 Example 1 : Multiply -6 X 3 using bit-pair recoding method 8 4 2 1 0 1 1 0 1 0 0 1 1 1 0 1 0 B = 1010 = -6 Q = +3 = 0011 8 4 2 1 0 0 1 1 +6 Recoded Q 0 0 1 1 0 -1+1
  • 6.
    13-11-2020 7Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Example 1: Contd. . . . B = -6 = Recoded Multiplier-Q 1 0 1 0 +1 -1 0 0 0 0 0 1 1 0 Multiplying -6 by -1 gives +6 i.e. 0110. Since this is +ve no. extend the left sign bits by 0s 1 1 1 0 1 0 Multiply B by +1 and shift left by 2 bits. Since this is negative number, extend the left sign bits by 1s 1 1 1 0 1 1 1 0
  • 7.
    13-11-2020 8Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Example 1: Contd. . . . Since MSB is 1, the result is negative and the value is 2’s complement of 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 0 1’s Complement 2’s Complement 128 64 32 16 8 4 2 1 0 0 0 1 0 0 1 0 Result is 16+2 = 18 i.e. -18
  • 8.
    13-11-2020 9Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Multiplication using bit-pair recoding Write the binary code of multiplicand & multiplier Use same number of bits for both the values such that it is the maximum number of bits required either by multiplicand or by multiplier and add one more at the left (MSB) for sign. If any value is negative, represent it using 2’s complement Find the recoded (bit-pair) values of multiplier by adding a ‘0’ at the right side. Extend the MSB if necessary. If the recoded value has -1 or -2 , find out the 2’s complement of the multiplicand for further use. What do you have to understand?
  • 9.
    13-11-2020 10Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Multiplication using bit-pair recoding Multiplicand B = 13 ; Multiplier Q = -6 Any negative number is represented using 2’s complement. Use 5 bits (one for sign) to represent each number because 13 requires 4 bits Example 2 : Multiply 13 X -6 using bit-pair recoding method 16 8 4 2 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 1 0 Q = 11010 = -6 +6 Recoded Q 1 1 0 1 0 -2-1 6 = 00110 Q = -6 = (1S complement of +6 )+1 0 Sign bit To bit-pair recode add a zero near LSB , get table and get code
  • 10.
    13-11-2020 11Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Multiplication using bit-pair recoding B = +13 = 01101 16 8 4 2 1 0 1 1 0 1 Since the recoded multiplier has negative values, find out the 2’s complement of the multiplicand (B) for future use Sign bit 0 1 1 0 1B = +13 2’s complement 1 0 0 1 0 1 1 0 0 1 1- 13 1 0 0 1 1 1’s complement
  • 11.
    13-11-2020 12Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Example 1: Contd. . . . To multiply +13 by -2, Take the 2’s complement of 13 shift left by one bit and add 0 at the right 0 1 1 0 1 0 -1 -2 B= +13 Recoded Multiplier 1 1 1 1 1 0 0 1 1 0 To multiply +13 by -1, Take the 2’s complement of 13. Put this two positions left. Extend the sign bits 1 1 1 1 0 0 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0multiply +13 by 0. Put this two positions left 1 Since MSB is 1 the result is negative and the value is obtained by 2’s complement
  • 12.
    13-11-2020 13Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Example 1: Contd. . . . 1 1 1 0 1 1 0 0 1 0 Since MSB is 1 the result is negative and the value is obtained by 2’s complement of 0 0 0 1 0 0 1 1 0 1 1’s complement 1 0 0 0 1 0 0 1 1 1 0 Result in binary 0 0 0 1 0 0 1 1 1 0 128 64 32 16 8 4 2 1 Result in decimal value Result : -(64+8+4+2) = -78 ─
  • 13.
    13-11-2020 14Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE PART - 2 Division Algorithm
  • 14.
    13-11-2020 15Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Binary Division Manual Division 1001010 Dividend / 1000 Divisor 1000 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 Remainder Quotient Divisor has been shifted right Quotient bit is shifted left and 1 or 0 is added in the right
  • 15.
    13-11-2020 16Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Division-Hardware Remainder Quotient Dividend 64-bit ALU Shift Right Shift Left Write Control 32 bits 64 bits 64 bits 64-bit Divisor register, 64-bit ALU, 64-bit Remainder register, and 32-bit Quotient register Divisor subtract
  • 16.
    13-11-2020 17Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Division Algorithm 2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. Test Remainder Remainder < 0Remainder  0 Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. 2a. Shift the Quotient register to the left setting the new rightmost bit to 1. 3. Shift the Divisor register right by 1 bit. Done Yes: n+1 repetitions ) Place Dividend in Remainder n+1 repetition? No: < n+1 repetitions ‘n’ is the number of bits in the quotient and remainder
  • 17.
    13-11-2020 18Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Division Algorithms Dividend Divisor Quotient Remainder Sign of Quotient Sign of Remainder + + + + Quotient is positive if both dividend & divisor have same sign Remainder has the same sign as dividend - - + - + - - + Quotient is negative if sign of dividend is different from the sign of the divisor- + - - What do you have to remember?  A-register is used to store remainder. It is initialized with zero and has one bit more than the number of bits in the divisor.  Initially dividend is stored in Q-register and after performing the division Q- register holds Quotient.  Divisor is stored in B-register. One extra ‘0’ is added as MSB  If the operands are signed values, proceed assuming both as positive and at the end assign signs as given in the above table.
  • 18.
    13-11-2020 19Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Q0 = 0 ; A  A+B Is MSB of A = 1? YesNo A  0 ; Q  Dividend B  Divisor ; SC  no_of_bits in the dividend Q  1 SC  SC-1. Stop Yes start Is SC<0? No Shift left A,Q A  A-B Restoring Division Algorithm
  • 19.
    13-11-2020 20Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE SC A Q Steps Explanation A4 A3 A2 A1 A0 Q3 Q2 Q1 Q0 4 0 0 0 0 0 1 0 1 0 Initial 3 0 0 0 0 1 0 1 0 SHL A,Q A-B = A+(-B)= A + 2’s complement of B A  00001 + 11101 ; A = 111101 1 1 1 0 0 1 0 A A-B 0 0 0 0 1 0 1 0 0 MSB = 1; So A A+B ; Q0 =0 A  11110 + 00011 ; A= 1 00001 2 0 0 0 1 0 1 0 0 SHL A,Q A-B = A+(-B)= A + 2’s complement of B A  00010 + 11101 ; A = 111111 1 1 1 1 1 0 0 A A-B 0 0 0 1 0 1 0 0 0 MSB = 1; So A A+B ; Q0 =0 A  11111 + 00011 ; A= 1 00010 1 0 0 1 0 1 0 0 0 0 SHL A,Q 0 0 0 1 0 0 0 0 A A-B A  00101 + 11101 ; A= 1 00010 0 0 0 1 0 0 0 0 1 MSB = 0; So Q0 =1 0 0 0 1 0 0 0 0 1 SHL A,Q 0 0 0 0 1 0 0 1 A A-B A  00100 + 11101 ; A= 1 00001 0 0 0 0 1 0 0 1 1 MSB = 0; So Q0 =1 Restoring Division Example 1: 1010 / 0011  10/3 A= 00000 ; Q=1010 (Dividend) ; B= 00011 (Divisor with MS bit) ; -B = 2’s Complement of B = 1’s complement of B +1 = 11100 +1 = 11101 Remainder = 1 Quotient = 3
  • 20.
    13-11-2020 21Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE A  A+B Is MSB of A = 1? YesNo A  0 ; Q  Dividend B  Divisor ; SC  no_of_bits in the dividend Q0 = 1 SC  SC-1. Stop No start Is SC<0? No Shift left A,Q Non-Restoring Division Algorithm Is MSB of A = 1? YesNo A  A─B Q0 = 0 Yes Is MSB of A = 1? A  A+B Yes
  • 21.
    13-11-2020 22Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE SC A Q Steps Explanation A4 A3 A2 A1 A0 Q3 Q2 Q1 Q0 4 0 0 0 0 0 1 0 1 0 Initial 3 0 0 0 0 1 0 1 0 SHL A,Q A-B = A+(-B)= A+ 2’s complement of B A  00001 + 11101 ; A = 111101 1 1 1 0 0 1 0 0 MSB = 0; A A-B Now MSB =1, so Q0 =0 2 1 1 1 0 0 1 0 0 SHL A,Q A  11100 + 00011 ; A= 11111 1 1 1 1 1 1 0 0 0 MSB =1 so A A+B Now MSB =1, so Q0 =0 1 1 1 1 1 1 0 0 0 SHL A,Q 0 0 0 1 0 0 0 0 1 MSB =1 so A A+B Now MSB =0, so Q0 =1 A  11111 + 00011 A= 1 00010 0 0 0 1 0 0 0 0 1 SHL A,Q 0 0 0 0 1 0 0 1 1 MSB = 0; A A-B Now MSB =0, so Q0 =1 A  00100 + 11101 ; A= 1 00001 Non-Restoring Division Example 1: 1010 / 0011  10/3 A= 00000 ; Q=1010 (Dividend) ; B= 00011 (Divisor with MS bit) ; -B = 2’s Complement of B = 1’s complement of B +1 = 11100 +1 = 11101 Remainder = 1 Quotient = 3
  • 22.
    13-11-2020 23Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE SC A Q Steps Explanation A4 A3 A2 A1 A0 Q3 Q2 Q1 Q0 4 0 0 0 0 0 1 1 0 0 Initial 3 0 0 0 0 1 1 0 0 SHL A,Q A-B = A+(-B)= A+ 2’s complement of B A  00001 + 11101 ; A = 111101 1 1 1 0 1 0 0 0 MSB = 0; A A-B Now MSB =1, so Q0 =0 2 1 1 1 0 1 0 0 0 SHL A,Q A  11101 + 00011 ; A= 1 00000 0 0 0 0 0 0 0 0 1 MSB =1 so A A+B Now MSB =0, so Q0 =1 1 0 0 0 0 0 0 0 1 SHL A,Q 1 1 1 0 1 0 0 1 0 MSB =0 so A A-B Now MSB =1, so Q0 =0 A  00000+ 11101 A= 11101 0 1 1 0 1 0 0 1 0 SHL A,Q 1 1 1 0 1 0 1 0 0 MSB = 1; A A+B Now MSB =1, so Q0 =0 A  11010 + 00011 ; A= 11101 1 1 1 0 1 0 1 0 0 MSB = 1; A A+B A  11101 + 00011; A=1 00000 Non-Restoring Division Example 2: -12 / +3  1100 / 0011 (don’t add any sign bit) A= 00000 ; Q=1100 (Dividend) ; B= 00011 (Divisor with MS bit) ; -B = 2’s Complement of B = 1’s complement of B +1 = 11100 +1 = 11101 Remainder = 00000Quotient
  • 23.
    13-11-2020 24Dr. K.K.THYAGHARAJAN, RMD ENGINEERING COLLEGE Answer: Remainder = 00000 Quotient = 0100 In this problem since the dividend is negative the remainder will be negative (ref slide 18) i.e. -0 = 0 Since dividend & divisor have different signs, the quotient is negative i.e. -4