The document describes a student thesis project to design and build a Programmable Logic Controller (PLC) using an FPGA and microcontroller. The project involves designing electrical circuits based on these components, creating a printed circuit board layout, and testing the functionality of the completed PLC board. The PLC contains a main board with an FPGA and microcontroller to run the core logic, and a separate power board to handle input/output functions and connect to external devices and systems. Schematics and circuit designs are provided for the various components and subsystems that make up the PLC.

1. Zanjan University
Department of Electrical Engineering
Bachelor Thesis
Title
Making PLC (Programmable logic controller) by FPGA and
microcontroller
By
Mojtaba Hajimiri
Ali nilechi
Supervisor
Dr. Siroos Toofan

2.  PLC (Programmable logic controller) is one of the important
parts in industry. So our purpose in this project were making a
PLC. Towards this end, an electrical circuit is designed based
on FPGA and other microcontrollers. Then, a PCB is designed
using altium designer, and the functionality of the board is
tested.
 Our PLC in here contains 2 boards :
 1- main board: this board consist of altera cyclone ii
EP2C8T144C8 FPGA and atmega128. we used this board as
our main board. We writes the PLCs main program in quartus
software (by graphical language-like FBD in PLC) on FPGA
and then we sends our commands to atmega128 microcontroller
that can be connected to our power board (by rs232 or ...).
 2-power board: this board consists of atmega128
microcontroller as main processor and can been connected to
our main board (by rs232 or ...). We used this board as our
input-output board. this board consists of some protection
circuits in his inputs that can be acquire different types of
inputs. in this board we used relays to control automation
systems.

3.  Power board

4.  Power board schematic:

5.  Input circuits:

6.  Output relay circuit:

7.  lcd & hmtr & mmc circuit:
1
2
3
4
5
6
HMTR
Header
6
V
C
C
V
C
C
G
N
D
G
N
D
rx0
tx0
V
C
C
G
N
D
V
C
C
3
1
2
1
0
K
R_LCD
RPot
G
N
D
1
2
3
4
5
6
7
8
eeprom
Header
4X2
G
N
D
G
N
D
1
VCC
2
V
O
3
R
S
4
R/W
5
E
6
DB0
7
DB1
8
DB2
9
DB3
1
0
DB4
1
1
DB5
1
2
DB6
1
3
DB7
1
4
A
1
5
K
1
6
LCD
1
2
3
4
5
6
7
8
9
1
0
m
m
c
Header
10
1
K
rmmc1
Res1
1
K
rmmc2
Res1
s
s
o
mosio
v
3
3
scko
v
3
3
v
3
3
G
N
D
misoo
c
4
c
5
c
6
c
7
c
0
c
1
c
2
V
C
C
G
N
D
V
C
C
SDA

8.  DAC circuits:
V
C
C
-vcc
1
K
Res1
G
N
D
1
K
rdac11
Res1
1
K
rdac1
Res1
1
0
0
p
F
cdac1
Cap
1
2
3
out_pin
Header
3H
1
2
con_analog
G
N
D
8
3
2
4
5
1
6
7
OPAMP1
LM741CN
VLC
1
IOUT
2
V
-
3
IOUT
4
B
1
5
B
2
6
B
3
7
B
4
8
B
5
9
B
6
1
0
B
7
1
1
B
8
1
2
V
+
1
3
VREF(+)
1
4
VREF(-)
1
5
COMP
1
6
dac081
DAC0800LCN
a
0
a
1
a
2
a
3
a
4
a
5
a
6
a
7
V
C
C
V
C
C
G
N
D
-vcc
G
N
D
VLC
1
IOUT
2
V
-
3
IOUT
4
B
1
5
B
2
6
B
3
7
B
4
8
B
5
9
B
6
1
0
B
7
1
1
B
8
1
2
V
+
1
3
VREF(+)
1
4
VREF(-)
1
5
COMP
1
6
dac082
DAC0800LCN
8
3
2
4
5
1
6
7
opamp2
LM741CN
e
0
e
1
e
2
e
3
e
4
e
5
e
6
e
7
1
K
rdac2
Res1
1
K
rop2
Res1
1
K
rdac21
Res1
V
C
C
G
N
D
V
C
C
V
C
C
-vcc
cadc2
-vcc

9.  Power circuit:

10.  Main board:

11.  Power circuit:A
C
2
V
+
1
A
C
3
V
-
4
BRIDGE
POWER
DC_Jack
I
N
1
3
O
U
T
2
G
N
D
G
N
D
4
L7805CT
L7805CT
G
N
D
100UF
C
1
Cap
100UF
C
2
Cap
1
0
0
n
F
C
3
Cap
1
K
R
1
Res1
LED_POWER
LED0
47UF
c
4
Cap
G
N
D
V
C
C
1
0
0
n
F
C
5
Cap
Semi
1
0
0
n
F
C
6
Cap
Semi
1
0
0
n
F
C
7
Cap
Semi
1
0
0
n
F
C
8
Cap
Semi
1
0
0
n
F
C
9
Cap
Semi
1
0
0
n
F
C10
Cap
Semi
1
0
0
n
F
C11
Cap
Semi
1
0
0
n
F
C12
Cap
Semi
1
0
0
n
F
C13
Cap
Semi
1
0
0
n
F
C14
Cap
Semi
1
0
0
n
F
C15
Cap
Semi
1
0
0
n
F
C16
Cap
Semi
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
1
0
0
n
F
C18
Cap
Semi
1
0
0
n
F
C19
Cap
Semi
1
0
0
n
F
C20
Cap
Semi
1
0
0
n
F
C21
Cap
Semi
1
0
0
n
F
C22
Cap
Semi
1
0
0
n
F
C23
Cap
Semi
1
0
0
n
F
C24
Cap
Semi
1
0
0
n
F
C25
Cap
Semi
G
N
D
1
VIN
2
V
O
U
T
3
MCP1700T_1
MCP1700T-1202E/MB
G
N
D
1
VIN
2
V
O
U
T
3
MCP1700T_2
MCP1700T-1202E/MB
G
N
D
G
N
D
G
N
D
1
0
0
n
F
C28
Cap
Semi
1
0
0
n
F
C29
Cap
Semi
G
N
D
G
N
D
G
N
D
+3V3
+1V2
USB3V
N
C
4
INH
2
VIN
1
6
V
O
U
T
5
G
N
D
L
F
3
3
_
3
LF33ABPT
N
C
4
INH
2
VIN
1
6
V
O
U
T
5
G
N
D
L
F
3
3
_
1
LF33ABPT
N
C
4
INH
2
VIN
1
6
V
O
U
T
5
G
N
D
L
F
3
3
_
2
LF33ABPT
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
47UF
C17
Cap
1
2
3
4
5
6
7
8
POWER
SUPPLY
JUMPER
Header
4X2H
G
N
D
G
N
D
1
0
0
n
F
C27
Cap
Semi
1
0
0
n
F
C26
Cap
Semi
VCC_in
VCC_in
47UF
c60
Cap
47UF
c61
Cap
47UF
c62
Cap
G
N
D
G
N
D
G
N
D
+3V3
USB3V
1
0
0
n
F
c25_1
Cap
Semi

12.  Osillator schematics:E
G
N
D
Out
VCC
OSC_2
27MH
G
N
D
G
N
D
1
0
0
n
F
C_OS1
Cap
Semi
1
0
0
n
F
C_OS2
Cap
Semi
G
N
D
G
N
D
16MHZ
27MH
PUSH_B0
SMB
G
N
D
1
K
R
2
Res3
G
N
D
EXT_CLOCK0
PUSH_B1
SMB
G
N
D
1
K
R
3
Res3
G
N
D
EXT_CLOCK1
PUSH_B2
SMB
G
N
D
1
K
R
4
Res3
G
N
D
EXT_CLOCK2
PUSH_B5
SMB
G
N
D
1
K
R
7
Res3
G
N
D
EXT_CLOCK5
PUSH_B4
SMB
G
N
D
1
K
R
6
Res3
G
N
D
EXT_CLOCK4
PUSH_B3
SMB
G
N
D
1
K
R
5
Res3
G
N
D
EXT_CLOCK3
+3V3
+3V3
E
G
N
D
Out
VCC
OSC_1
16MH
16MHZ
27MH
EXT_CLOCK0
EXT_CLOCK1
EXT_CLOCK2
EXT_CLOCK3
EXT_CLOCK4
EXT_CLOCK5
1
0
0
n
F
C_P0
1
0
0
n
F
C_P5
1
0
0
n
F
C_P4
1
0
0
n
F
C_P1
1
0
0
n
F
C_P2
1
0
0
n
F
C_P3

13.  Serial communication:
C1+
1
V
D
D
2
C1-
3
C2+
4
C2-
5
VEE
6
T2OUT
7
R2IN
8
R2OUT
9
T2IN
1
0
T1IN
1
1
R1OUT
1
2
R1IN
1
3
T1OUT
1
4
G
N
D
1
5
V
C
C
1
6
m_MAX232
MAX232ESE
C1+
1
V
D
D
2
C1-
3
C2+
4
C2-
5
VEE
6
T2OUT
7
R2IN
8
R2OUT
9
T2IN
1
0
T1IN
1
1
R1OUT
1
2
R1IN
1
3
T1OUT
1
4
G
N
D
1
5
V
C
C
1
6
F_MAX232
MAX232ESE
1
2
3
4
5
6
7
8
9
1
1
1
0
m_RS232
D
Connector
9
1
2
3
4
5
6
7
8
9
1
1
1
0
F_RS232
D
Connector
9
G
N
D
G
N
D
1
U
C30
Cap
Semi
1
U
C31
Cap
Semi
1
U
C32
Cap
Semi
1
U
C33
Cap
Semi
1
U
C34
Cap
Semi
1
U
C35
Cap
Semi
1
U
C36
Cap
Semi
1
U
C37
Cap
Semi
G
N
D
G
N
D
v
3
7
G
N
D
G
N
D
G
N
D
G
N
D
V
C
C
m_UART_TXD
m_UART_RXD
G
N
D
G
N
D
F_UART_TXD
F_UART_RXD
+3V3
F_UART_TXD
F_UART_RXD
m_UART_RXD
m_UART_TXD

14.  atmega 128 schematic:
P
E
N
1
PE0
(RXD0/PDI)
2
PE1
(TXD0/PDO)
3
PE2
(XCK0/AIN0)
4
PE3
(OC3A/AIN1)
5
PE4
(OC3B/INT4)
6
PE5
(OC3C/INT5)
7
PE6
(T3/INT6)
8
PE7
(IC3/INT7)
9
PB0
(SS)
1
0
PB1
(SCK)
1
1
PB2
(MOSI)
1
2
PB3
(MISO)
1
3
PB4
(OC0)
1
4
PB5
(OC1A)
1
5
PB6
(OC1B)
1
6
PB7
(OC2/OC1C)
1
7
TOSC2/PG3
1
8
TOSC1/1PG4
1
9
RESET
2
0
V
C
C
2
1
G
N
D
2
2
XTAL2
2
3
XTAL1
2
4
PD0
(SCL/INT0)
2
5
PD1
(SDA/INT1)
2
6
PD2
(RXD1/INT2)
2
7
PD3
(TXD1/INT3)
2
8
PD4
(IC1)
2
9
PD5
(XCK1)
3
0
PD6
(T1)
3
1
PD7
(T2)
3
2
PG0
(WR)
3
3
PG1
(RD)
3
4
PC0
(A8)
3
5
PC1
(A9)
3
6
PC2
(A10)
3
7
PC3
(A11)
3
8
PC4
(A12)
3
9
PC5
(A13)
4
0
PC6
(A14)
4
1
PC7
(A15)
4
2
PG2
(ALE)
4
3
PA7
(AD7)
4
4
PA6
(AD6)
4
5
PA5
(AD5)
4
6
PA4
(AD4)
4
7
PA3
(AD3)
4
8
PA2
(AD2)
4
9
PA1
(AD1)
5
0
PA0
(AD0)
5
1
V
C
C
5
2
G
N
D
5
3
PF7
(ADC7/TDI)
5
4
PF6
(ADC6/TDO)
5
5
PF5
(ADC5/TMS)
5
6
PF4
(ADC4/TCK)
5
7
PF3
(ADC3)
5
8
PF2
(ADC2)
5
9
PF1
(ADC1)
6
0
PF0
(ADC0)
6
1
AREF
6
2
G
N
D
6
3
A
V
C
C
6
4
micro
ATmega128-16AC
1
2
3
4
5
6
7
8
9
1
0
programer
Header
5X2
V
C
C
G
N
D
reset
rx0
tx0
rx0
tx0
reset
SW_RESET
SW-PB
G
N
D
1
K
R
8
Res1
V
C
C
1
2
XTAL
XTAL
1
0
0
p
F
cx1
Cap
1
0
0
p
F
cx2
Cap
G
N
D
1
2
3
4
5
6
HMTR
Header
6
V
C
C
V
C
C
G
N
D
rx0
tx0
G
N
D
V
C
C
G
N
D
V
C
C
G
N
D
G
N
D
1
VCC
2
V
O
3
R
S
4
R/W
5
E
6
DB0
7
DB1
8
DB2
9
DB3
1
0
DB4
1
1
DB5
1
2
DB6
1
3
DB7
1
4
A
1
5
K
1
6
LCD
c
0
c
1
c
2
c
4
c
5
c
6
c
7
1
2
3
4
5
6
7
8
9
1
0
ADC_PORT
Header
5X2
f
0
f
1
f
2
f
3
f
4
f
5
f
6
f
7
f
0
f
1
f
2
f
3
f
4
f
5
f
6
f
7
G
N
D
a_ref
a_ref
1
0
0
n
F
C40
Cap
1
0
0
n
F
C41
Cap
1
0
0
n
F
C38
Cap
G
N
D
G
N
D
1
0
0
n
F
C39
Cap
G
N
D
G
N
D
V
C
C
1
K
R10
Res3
1
2
3
4
5
6
7
8
9
1
0
PIN_OUT
Header
5X2
G
N
D
G
N
D
a
5
a
6
a
7
G
N
D
m_UART_TXD
m_UART_RXD
V
C
C
1
0
K
R
9
Res3
1
2
XTAL1
32.768kHZ
b
0
b
1
b
2
b
4
b
5
b
6
b
7
g
0
g
1
g
2
b
0
b
1
b
2
b
4
b
5
b
6
b
7
c
3
e
0
e
1
e
2
e
3
e
4
e
5
e
6
e
7
e
0
e
1
e
2
e
3
e
4
e
5
e
6
e
7
g
3
d
4
d
5
d
6
d
7
a
0
a
1
a
2
a
3
a
4
1
2
3
4
xtal_jumper
Header
2X2
V
C
C
m_UART_RXD
m_UART_TXD
b
1
3
3
0
R27
Res1
3
1
2
1
0
K
R_lcd
RPot

15.  FPGA & microcontroller connection:
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_m1
74LVX4245
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_m4
74LVX4245
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_m2
74LVX4245
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_m3
74LVX4245
g
0
g
1
g
2
g
3
V
C
C
V
C
C
V
C
C
V
C
C
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
a
0
a
1
a
2
a
3
a
4
a
5
a
6
a
7
c
0
c
1
c
2
c
3
c
4
c
5
c
6
c
7
d
4
d
5
d
6
d
7
126_m_I
129_m_I
132_m_I
133_m_I
134_m_I
135_m_I
136_m_I
137_m_I
139_m_T/R
141_m_N_OE
142_m_I
143_m_I
144_m_I
3_m_I
4_m_I
7_m_I
8_m_I
9_m_I
24_m_T/R
25_m_N_OE
28_m_I
30_m_I
31_m_I
32_m_I
40_m_T/R
41_m_N_OE
42_m_I
43_m_I
44_m_I
45_m_I
125_m_T/R
G
N
D
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
3_m_I
4_m_I
7_m_I
8_m_I
9_m_I
25_m_N_OE
28_m_I
30_m_I
31_m_I
32_m_I
126_m_I
129_m_I
132_m_I
133_m_I
134_m_I
135_m_I
136_m_I
137_m_I
141_m_N_OE
142_m_I
143_m_I
144_m_I
42_m_I
43_m_I
44_m_I
45_m_I
41_m_N_OE

16.  USB circuits:
EESK
1
EEDATA
2
V
C
C
3
RESET#
4
RSTOUT#
5
3V3OUT
6
USBDP
7
USBDM
8
G
N
D
9
PWREN#
1
0
SI
/
WU
1
1
RXF#
1
2
VCCIO
1
3
TXE#
1
4
W
R
1
5
RD#
1
6
G
N
D
1
7
D
7
1
8
D
6
1
9
D
5
2
0
D
4
2
1
D
3
2
2
D
2
2
3
D
1
2
4
D
O
2
5
V
C
C
2
6
XTIN
2
7
XTOUT
2
8
A
G
N
D
2
9
A
V
C
C
3
0
TEST
3
1
E
E
C
S
3
2
FT245BM
FT245BM
C
S
1
D
O
4
D
I
3
N
C
7
VSS
5
CLK
2
N
C
6
V
C
C
8
93C46
93C46A-I/P
G
N
D
2
7
p
F
C47
Cap
Semi
2
7
p
F
C48
Cap
Semi
G
N
D
G
N
D
3
3
n
F
C45
Cap
Semi
G
N
D
2
7
R
R19
Res3
2
7
R
R20
Res3
D
+
D
+
D
-
D
-
E
E
C
S
EESK
EEDATA
EECS
E
E
S
K
EEDATA
2K2
R25
Res3
1
0
K
R26
Res3
G
N
D
G
N
D
1.5K
R21
Res3
99_USB0
100_USB1
101_USB2
103_USB3
104_USB4
112_USB5
113_USB6
114_USB7
115_USB_RD#
118_USB_WR
119_USB_TXE#
120_USB_RXF
V
C
C
1
5
_
3
3
n
F
C46
Cap
Semi
4
7
0
R22
Res3
V
C
C
G
N
D
4K7
R17
Res3
1
0
K
R18
Res3
G
N
D
1
0
K
R23
Res3
1
0
K
R24
Res3
G
N
D
USB3V
USB3V
USB3V
USB3V
115_USB_RD#
118_USB_WR
G
N
D
99_USB0
100_USB1
101_USB2
103_USB3
104_USB4
112_USB5
113_USB6
114_USB7
115_USB_RD#
118_USB_WR
119_USB_TXE#
120_USB_RXF
V
B
U
S
1
D
-
2
D
+
3
G
N
D
4
J
1
1-1470156-1
1
2
XTAL3
6MHZ

17.  FPGA schematics:
IO,
(ASDO)
1
IO,
(nCSO)
2
IO,
LVDS15p
(CRC_ERROR)
3
IO,
LVDS15n
(CLKUSR)
4
IO,
VREFB1N0
7
IO,
LVDS8p,
(DPCLK0/DQS0L)
8
IO,
LVDS8n
9
IO,
LVDS7p,
(DPCLK1/DQS1L)
2
4
IO,
LVDS7n
2
5
IO,
VREFB1N1
2
8
I
O
3
0
IO,
PLL1_OUTp
3
1
IO,
PLL1_OUTn
3
2
BANK
1
EP2C8T144C8A
EP2C8T144C8
IO,
LVDS37n
1
1
2
IO,
LVDS37p
1
1
3
IO,
LVDS36n
1
1
4
IO,
LVDS36p
1
1
5
IO,
LVDS34n
1
1
8
IO,
LVDS34p,
(DPCLK8/DQS0T)
1
1
9
IO,
VREFB2N0
1
2
0
IO,
LVDS33n
1
2
1
IO,
LVDS33p
1
2
2
IO,
LVDS29n,
DQ1T0
1
2
5
IO,
LVDS29p,
DQ1T1
1
2
6
IO,
LVDS26p,
DQ1T2
1
2
9
IO,
VREFB2N1
1
3
2
IO,
LVDS23n,
DQ1T3
1
3
3
IO,
LVDS23p,
DQ1T4
1
3
4
IO,
LVDS19n,
DQ1T5
1
3
5
IO,
LVDS19p,
(DPCLK10/DQS1T)
1
3
6
IO,
LVDS18n,
DQ1T6
1
3
7
IO,
LVDS18p,
DQ1T7
1
3
9
IO,
LVDS17p,
DQ1T8
1
4
1
IO,
LVDS17n
(DEV_CLRn)
1
4
2
IO,
LVDS16p,
(DM1T/BWS#1T)
1
4
3
IO,
LVDS16n
1
4
4
BANK
2
EP2C8T144C8B
EP2C8T144C8
IO,
LVDS56n,
(DM1R/BWS#1R)
7
3
IO,
LVDS56p,
DQ1R8
7
4
IO,
LVDS54n
(INIT_DONE)
7
5
IO,
LVDS54p
(nCEO)
7
6
IO,
VREFB3N1
7
9
IO,
LVDS48n,
DQ1R7
8
6
IO,
LVDS48p,
(DPCLK6/DQS1R)
8
7
IO,
LVDS47n,
DQ1R6
9
2
IO,
LVDS47p,
(DPCLK7/DQS0R)
9
3
IO,
LVDS46n,
DQ1R5
9
4
IO,
LVDS46p,
DQ1R4
9
6
IO,
LVDS45n,
DQ1R3
9
7
IO,
VREFB3N0
9
9
IO,
LVDS39n,
DQ1R2
1
0
0
IO,
LVDS39p,
DQ1R1
1
0
1
IO,
PLL2_OUTp,
DQ1R0
1
0
3
IO,
PLL2_OUTn
1
0
4
BANK
3
EP2C8T144C8C
EP2C8T144C8
IO,
LVDS77n
(DEV_OE)
4
0
IO,
LVDS77p,
(DM1B/BWS#1B)
4
1
IO,
LVDS76p,
DQ1B8
4
2
IO,
LVDS76n,
DQ1B7
4
3
IO,
LVDS75p,
DQ1B6
4
4
IO,
LVDS75n,
DQ1B5
4
5
IO,
LVDS74p,
(DPCLK2/DQS1B)
4
7
IO,
LVDS74n
4
8
IO,
VREFB4N1
5
1
IO,
LVDS70p,
DQ1B4
5
2
IO,
LVDS68p,
DQ1B3
5
3
IO,
LVDS68n,
DQ1B2
5
5
IO,
LVDS67p,
DQ1B1
5
7
IO,
LVDS67n,
DQ1B0
5
8
IO,
LVDS66p
5
9
IO,
LVDS66n
6
0
IO,
VREFB4N0
6
3
IO,
LVDS60p,
(DPCLK4/DQS0B)
6
4
IO,
LVDS60n
6
5
IO,
LVDS59n
6
7
IO,
LVDS58p
6
9
IO,
LVDS58n
7
0
IO,
LVDS57p
7
1
IO,
LVDS57n
7
2
BANK
4
EP2C8T144C8D
EP2C8T144C8
TDO
1
0
TMS
1
1
TCK
1
2
TDI
1
3
DATA0
1
4
DCLK
1
5
nCE
1
6
nCONFIG
2
0
nSTATUS
8
2
CONF_DONE
8
3
MSEL1
8
4
MSEL0
8
5
EP2C8T144C8E
EP2C8T144C8
VCCIO1
5
VCCIO1
2
3
VCCINT
2
6
VCCIO1
2
9
VCCIO4
4
6
VCCINT
5
0
VCCIO4
5
4
VCCINT
6
2
VCCIO4
6
6
VCCIO3
7
7
VCCINT
8
1
VCCIO3
9
5
VCCIO3
1
0
2
VCCIO2
1
1
6
VCCINT
1
2
4
VCCIO2
1
2
7
VCCINT
1
3
1
VCCIO2
1
3
8
EP2C8T144C8F
EP2C8T144C8
G
N
D
6
G
N
D
1
9
G
N
D
2
7
G
N
D
3
3
G
N
D
3
9
G
N
D
4
9
G
N
D
5
6
G
N
D
6
1
G
N
D
6
8
G
N
D
7
8
G
N
D
8
0
G
N
D
9
8
G
N
D
1
0
5
G
N
D
1
1
1
G
N
D
1
1
7
G
N
D
1
2
3
G
N
D
1
2
8
G
N
D
1
3
0
G
N
D
1
4
0
EP2C8T144C8G
EP2C8T144C8
GND_PLL1
3
4
VCCD_PLL1
3
5
GND_PLL1
3
6
VCCA_PLL1
3
7
GNDA_PLL1
3
8
GND_PLL2
1
0
6
VCCD_PLL2
1
0
7
GND_PLL2
1
0
8
VCCA_PLL2
1
0
9
GNDA_PLL2
1
1
0
EP2C8T144C8H
EP2C8T144C8
CLK0,
LVDSCLK0p
INPUT
1
7
CLK1,
LVDSCLK0n
INPUT
1
8
CLK2,
LVDSCLK1p
INPUT
2
1
CLK3,
LVDSCLK1n
INPUT
2
2
CLK7,
LVDSCLK3n
INPUT
8
8
CLK6,
LVDSCLK3p
INPUT
8
9
CLK5,
LVDSCLK2n
INPUT
9
0
CLK4,
LVDSCLK2p
INPUT
9
1
EP2C8T144C8I
EP2C8T144C8
G
N
D
G
N
D
nCS
1
DATA
2
V
C
C
3
G
N
D
4
ASDI
5
DCLK
6
V
C
C
7
V
C
C
8
EPCS1
EPCS1SI8
DATA
DCLK
nCS
ASDI
DATA
DCLK
ASDI
nCS
G
N
D
G
N
D
1
0
0
n
F
C42
Cap
Semi
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_F2
Component_1
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_F3
Component_1
47_T/R
48_N_OE
51_I/O
52_I/O
53_I/O
55_I/O
57_I/O
58_I/O
59_I/O
60_I/O
63_T/R
64_N_OE
65_I/O
67_I/O
69_I/O
70_I/O
71_I/O
72_I/O
73_I/O
74_I/O
T/R
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
A
5
8
A
6
9
A
7
1
0
G
N
D
1
1
G
N
D
1
2
G
N
D
1
3
B
7
1
4
B
6
1
5
B
5
1
6
B
4
1
7
B
3
1
8
B
2
1
9
B
1
2
0
B
0
2
1
N_OE
2
2
V
C
C
B
2
3
V
C
C
B
2
4
vcca
1
74LVX4245
74LV_F1
Component_1
75_T/R
76_N_OE
79_I/O
86_I/O
87_I/O
92_I/O
93_I/O
94_I/O
96_I/O
97_I/O
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
V
C
C
V
C
C
V
C
C
1
2
3
4
5
6
7
8
9
1
0
F_programer
Header
5X2
TCK
TDI
TDO
TMS
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
F_IO_1
Header
9X2H
G
N
D
G
N
D
IO_0
IO_1
IO_2
IO_3
IO_4
IO_5
IO_6
IO_7
IO_8
IO_9
IO_10
IO_11
IO_12
IO_13
IO_14
IO_15
IO_0
IO_1
IO_2
IO_3
IO_4
IO_5
IO_6
IO_7
IO_8
IO_9
IO_10
IO_11
IO_12
IO_13
IO_14
IO_15
IO_16
IO_17
IO_18
IO_19
IO_20
IO_21
IO_22
IO_23
IO_16
IO_17
IO_18
IO_19
IO_20
IO_21
IO_22
IO_23
99_USB0
100_USB1
101_USB2
103_USB3
104_USB4
112_USB5
113_USB6
114_USB7
115_USB_RD#
118_USB_WR
119_USB_TXE#
120_USB_RXF
1
2
3
4
5
6
7
8
9
1
0
F_IO_2
Header
5X2H
G
N
D
G
N
D
1
2
3
4
5
A_RES_1K
TCK
TDO
TMS
TDI
1
K
Res3
G
N
D
1
K
R12
Res3
G
N
D
1
0
K
R16
Res3
1
0
K
R13
Res3
1
0
K
R14
Res3
1
0
K
R15
Res3
G
N
D
1
2
3
4
5
6
7
8
9
1
0
F_programer_1
Header
5X2
G
N
D
DCLK
CONF_DONE
nCONFIG
nSTATUS
nCE
nCE
CONF_DONE
nCONFIG
DATA
ASDI
nCE
nCS
nSTATUS
CONF_DONE
nCONFIG
G
N
D
16MHZ
27MH
EXT_CLOCK0
EXT_CLOCK1
EXT_CLOCK2
EXT_CLOCK3
EXT_CLOCK4
EXT_CLOCK5
79_I/O
86_I/O
87_I/O
92_I/O
93_I/O
94_I/O
96_I/O
97_I/O
76_N_OE
75_T/R
47_T/R
48_N_OE
51_I/O
52_I/O
53_I/O
55_I/O
57_I/O
58_I/O
59_I/O
60_I/O
63_T/R
64_N_OE
65_I/O
67_I/O
69_I/O
70_I/O
71_I/O
72_I/O
73_I/O
74_I/O
42_m_I
43_m_I
44_m_I
45_m_I
40_m_T/R
41_m_N_OE
24_m_T/R
25_m_N_OE
28_m_I
30_m_I
31_m_I
32_m_I
125_m_T/R
126_m_I
129_m_I
132_m_I
133_m_I
134_m_I
135_m_I
136_m_I
137_m_I
139_m_T/R
141_m_N_OE
142_m_I
143_m_I
144_m_I
3_m_I
4_m_I
7_m_I
8_m_I
9_m_I
1
2
MSEL1
10mH
L
1
Inductor
Iron
10mH
L
2
Inductor
Iron
1
0
0
n
F
C43
Cap
Semi
1
0
0
n
F
C44
Cap
Semi
G
N
D
G
N
D
F_UART_TXD
F_UART_RXD
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+1V2
+1V2
+1V2
99_USB0
100_USB1
101_USB2
103_USB3
104_USB4
42_m_I
43_m_I
44_m_I
45_m_I
112_USB5
113_USB6
114_USB7
115_USB_RD#
118_USB_WR
119_USB_TXE#
120_USB_RXF
3_m_I
4_m_I
7_m_I
8_m_I
9_m_I
24_m_T/R
25_m_N_OE
28_m_I
30_m_I
31_m_I
32_m_I
F_UART_TXD
F_UART_RXD
125_m_T/R
126_m_I
129_m_I
132_m_I
133_m_I
134_m_I
135_m_I
136_m_I
137_m_I
139_m_T/R
141_m_N_OE
142_m_I
143_m_I
144_m_I
40_m_T/R
41_m_N_OE
27MH
16MHZ
EXT_CLOCK0
EXT_CLOCK5
EXT_CLOCK1
EXT_CLOCK4
EXT_CLOCK2
EXT_CLOCK3
1
0
0
n
F
C42_1
Cap
Semi
G
N
D

18.  Power board:

19.  Main board: