This document provides specifications for an N-channel logic level enhancement mode field effect transistor in an SOP-8 package from NIKO-SEM. Key specifications include: - Absolute maximum ratings including gate-source voltage up to ±20V, continuous drain current up to 7A, and pulsed drain current up to 40A. - Electrical characteristics including drain-source breakdown voltage of 30V, gate threshold voltage of 1-3V, and on-state drain-source resistance of 8.5-12mΩ. - Dynamic characteristics such as input capacitance of 846pF, output capacitance of 225pF, and total gate charge of 8.1nC.

1. REV 1.1
1
Jan-22-2010
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P1203BV
SOP-8
Halogen-Free & Lead-Free
NIKO-SEM
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS
Gate-Source Voltage VGS ±20 V
TA = 25 °C 11
Continuous Drain Current
TA = 100 °C
ID
7
Pulsed Drain Current
1
IDM 40
Avalanche Current IAS 28
A
Avalanche Energy L = 0.1mH EAS 40 mJ
TA = 25 °C 2.5
Power Dissipation
TA = 100 °C
PD
1
W
Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150 °C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS
Junction-to-Case RθJC 25
Junction-to-Ambient RθJA 50
°C / W
1
Pulse width limited by maximum junction temperature.
ELECTRICAL CHARACTERISTICS (TA = 25 °C, Unless Otherwise Noted)
LIMITS
PARAMETER SYMBOL TEST CONDITIONS
MIN TYP MAX
UNIT
STATIC
Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = 250µA 30
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA 1 1.8 3
V
Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V ±100 nA
VDS = 24V, VGS = 0V 1
Zero Gate Voltage Drain Current IDSS
VDS = 20V, VGS = 0V, TC = 125 °C 10
µA
On-State Drain Current
1
ID(ON) VDS = 10V, VGS = 10V 40 A
VGS = 4.5V, ID = 11A 14 17.5Drain-Source On-State
Resistance
1 RDS(ON)
VGS = 10V, ID = 11A 8.5 12
mΩ
Forward Transconductance
1
gfs VDS = 5V ID = 11A 40 S
PRODUCT SUMMARY
V(BR)DSS RDS(ON) ID
30V 12mΩ 11A G
D
S
4 :GATE
5,6,7,8 :DRAIN
1,2,3 :SOURCE
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2. REV 1.1
2
Jan-22-2010
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P1203BV
SOP-8
Halogen-Free & Lead-Free
NIKO-SEM
DYNAMIC
Input Capacitance Ciss 846
Output Capacitance Coss 225
Reverse Transfer Capacitance Crss
VGS = 0V, VDS = 12V, f = 1MHz
126
pF
Gate Resistance RG VGS = 0V, f = 1MHz 1.65 Ω
(VGS=10V) 17
Total Gate Charge
2
Qg (VGS=4.5V
)
8.1
Gate-Source Charge
2
Qgs 2.7
Gate-Drain Charge
2
Qgd
VDS = 0.5V(BR)DSS, ID = 8.8A
4
nC
Turn-On Delay Time
2
td(on) 9
Rise Time
2
tr 40
Turn-Off Delay Time
2
td(off) 20
Fall Time
2
tf
VDS = 15V, ID ≅ 12.5A,
VGS = 10V,RGEN = 3Ω
6
nS
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TA = 25 °C)
Continuous Current IS 1.9 A
Forward Voltage
1
VSD IF = 25A, VGS = 0V 1.3 V
Reverse Recovery Time trr IF = 11 A, dlF/dt = 100A / µS 21 nS
Reverse Recovery Charge Qrr 10 nC
1
Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％.
2
Independent of operating temperature.
REMARK: THE PRODUCT MARKED WITH “P1203BV”, DATE CODE or LOT #
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3. REV 1.1
3
Jan-22-2010
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P1203BV
SOP-8
Halogen-Free & Lead-Free
NIKO-SEM
Source-Drain Diode Forward Voltage
0
2
4
6
8
10
0 5 10 15 20
ID=8.8A
VDS=15V
Ciss
Coss
Crss
0.00E+00
2.00E+03
4.00E+03
6.00E+03
8.00E+03
1.00E+04
0 5 10 15 20 25 30
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50 -25 0 25 50 75 100 125 150
RDS(ON) ╳╳╳╳
VGS=10V
ID=11A
RDS(ON) ╳╳╳╳
RDS(ON) ╳╳╳╳
RDS(ON) ╳╳╳╳
RDS(ON) ╳╳╳╳
RDS(ON) ╳╳╳╳
RDS(ON) ╳╳╳╳
RDS(ON) ╳╳╳╳
RDS(ON) ╳╳╳╳
0
5
10
15
20
25
30
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
TJ=25° C
TJ=125° C
TJ= -20° C
0 0.5 1 1.5 2 2.5
0
5
10
15
20
25
4.5V
3V
30
4V
VG S = 10V
7V
Output Characteristics
ID,Drain-To-SourceCurrent(A)
Transfer Characteristics
ID,Drain-To-SourceCurrent(A)
VGS, Gate-To-Source Voltage(V)VDS, Drain-To-Source Voltage(V)
On-Resistance VS Temperature
RDS(ON)ON-Resistance(OHM)
TJ , Junction Temperature(˚C)
Capacitance CharacteristicC,Capacitance(pF)
VDS, Drain-To-Source Voltage(V)
Gate charge Characteristics
Characteristics
Qg , Total Gate Charge
VGS,Gate-To-SourceVoltage(V)
VSD, Source-To-Drain Voltage(V)
IS,SourceCurrent(A)
0.1 0.3 0.5 0.7 0.9 1.1
1.0E+01
TJ =150°C
TJ =25°C
1.0E+00
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E+02
1.3
1.0E-05
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4. REV 1.1
4
Jan-22-2010
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P1203BV
SOP-8
Halogen-Free & Lead-Free
NIKO-SEM
single Pluse
Duty Cycle=0.5
0.2
0.1
0.05
0.02
0.01
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02
Note
1.Duty cycle, D= t1 / t2
2.RthJA = 50 ℃℃℃℃/W
3.TJ-TA = P*RthJA(t)
4.RthJA(t) = r(t)*RthJA
0
10
20
30
40
50
0.001 0.01 0.1 1 10
SINGLE PULSE
RθJA= 50˚˚˚˚C/W
TA=25˚˚˚˚C
1ms
10S
1S
DC
100ms
10ms
100uS
0.01
0.1
1
10
100
0.1 1 10 100
NOTE :
1.VGS= 10V
2.TA=25˚˚˚˚ C
3.RθJA = 50˚˚˚˚C/W
4.Single Pulse
Operation in This Area
is Limited by RDS(ON)
↓↓↓↓
Safe Operating Area Single Pulse Maximum Power Dissipation
ID,DrainCurrent(A)
Power(W)
Single Pulse Time(s)VDS, Drain-To-Source Voltage(V)
Transient Thermal Response Curve
r(t),NormalizedEffective
TransientThermalResistance
T1 , Square Wave Pulse Duration[sec]
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5. REV 1.1
5
Jan-22-2010
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P1203BV
SOP-8
Halogen-Free & Lead-Free
NIKO-SEM
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