Original Power MOSFET IRFP140PBF IRFP140 IRFP140N 100V 33A TO-247 New Intern...AUTHELECTRONIC
Original Power MOSFET IRFP140PBF IRFP140 IRFP140N 100V 33A TO-247 New International Rectifier
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Original Mosfet IRFB18N50KPBF IRFB18N50K FB18N50K 18N50K 500V 17A TO-220 New ...AUTHELECTRONIC
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Original Power MOSFET IRFP140PBF IRFP140 IRFP140N 100V 33A TO-247 New Intern...AUTHELECTRONIC
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Original Mosfet IRFB18N50KPBF IRFB18N50K FB18N50K 18N50K 500V 17A TO-220 New ...AUTHELECTRONIC
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Original N-Channel Mosfet IRFB3077PBF IRFB3077 3077 75V 120A TO-220 New IRAUTHELECTRONIC
Original N-Channel Mosfet IRFB3077PBF IRFB3077 3077 75V 120A TO-220 New IR
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Original Dual P-Channel Mosfet RF7316TRPBF IRF7316 F7316 7316 SOP-8 New IRAUTHELECTRONIC
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Original N-Channel Mosfet IRF2907ZPBF 2907 75V 170A TO-220 New IRAUTHELECTRONIC
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Original N-CHANNEL Mossfet IRFB4227PBF IRFB4227 4227 130A 200V TO-220 New IRAUTHELECTRONIC
Original N-CHANNEL Mossfet IRFB4227PBF IRFB4227 4227 130A 200V TO-220 New IR
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Original Power MOSFET IRFP460PBF IRFP460 460 500V 20A TO-247 New Vishay Silic...AUTHELECTRONIC
Original Power MOSFET IRFP460PBF IRFP460 460 500V 20A TO-247 New Vishay Siliconix
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Original Power N-Channel MOSFET FR13N15D FR13N15 13N15 150V 14A TO-252 New In...AUTHELECTRONIC
Original Power N-Channel MOSFET FR13N15D FR13N15 13N15 150V 14A TO-252 New International Rectifier
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Original N - Channel Mosfet IRFR3709ZTRPBF FR3709Z 3709 FR3709 TO-252 New IRAUTHELECTRONIC
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Original N-Channel Mosfet IRFB3077PBF IRFB3077 3077 75V 120A TO-220 New IRAUTHELECTRONIC
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Original Power MOSFET IRFP460PBF IRFP460 460 500V 20A TO-247 New Vishay Silic...AUTHELECTRONIC
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Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Forklift Classes Overview by Intella PartsIntella Parts
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Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
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6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...
Original Mosfet IRF7493TRPBF IRF7493 F7493 7493 SOP-8 New IR
1. www.irf.com 1
7/29/03
SO-8
Top View
81
2
3
4 5
6
7
D
D
D
DG
S
A
S
S
A
IRF7493
HEXFET® Power MOSFET
Notes through … are on page 9
PD - 94654B
l High frequency DC-DC converters
Benefits
Applications
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
VDSS RDS(on) max Qg (typ.)
80V 15m:@VGS=10V 35nC
Absolute Maximum Ratings
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
ID @ TC = 70°C Continuous Drain Current, VGS @ 10V A
IDM
Pulsed Drain Current c
PD @TC = 25°C Maximum Power Dissipation f W
PD @TC = 70°C Maximum Power Dissipation f
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Lead ––– 20
RθJA
Junction-to-Ambient f ––– 50
Max.
9.3
7.4
74
± 20
80
-55 to + 150
2.5
0.02
1.6
2. IRF7493
2 www.irf.com
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 80 ––– ––– V
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.074 ––– mV/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 11.5 15 mΩ
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leakage ––– ––– -200
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs Forward Transconductance 13 ––– ––– S
Qg Total Gate Charge ––– 35 53
Qgs Gate-to-Source Charge ––– 5.7 –––
Qgd Gate-to-Drain Charge ––– 12 –––
td(on) Turn-On Delay Time ––– 8.3 –––
tr Rise Time ––– 7.5 –––
td(off) Turn-Off Delay Time ––– 30 ––– ns
tf Fall Time ––– 12 –––
Ciss Input Capacitance ––– 1510 –––
Coss Output Capacitance ––– 320 ––– pF
Crss Reverse Transfer Capacitance ––– 130 –––
Coss Output Capacitance ––– 1130 –––
Coss Output Capacitance ––– 210 –––
Crss eff. Effective Output Capacitance ––– 320 –––
Avalanche Characteristics
Parameter Units
EAS Single Pulse Avalanche Energyd mJ
IAR Avalanche CurrentÙ A
Diode Characteristics
Parameter Min. Typ. Max. Units
IS Continuous Source Current ––– ––– 9.3
(Body Diode) A
ISM Pulsed Source Current ––– ––– 74
(Body Diode)Ù
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 37 56 ns
Qrr Reverse Recovery Charge ––– 52 78 nC
RG = 6.2Ω
Conditions
VGS = 10V
Max.
180
5.6
VGS = 0V, VDS = 0V to 64V g
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 5.6A e
TJ = 25°C, IF = 5.6A, VDD = 15V
di/dt = 100A/µs e
TJ = 25°C, IS = 5.6A, VGS = 0V e
showing the
integral reverse
p-n junction diode.
Typ.
–––
–––
VGS = 10V
VGS = 0V
VDS = 25V
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 64V, ƒ = 1.0MHz
VDD = 40V, e
ID = 5.6A
MOSFET symbol
VDS = VGS, ID = 250µA
VDS = 80V, VGS = 0V
VDS = 64V, VGS = 0V, TJ = 125°C
ƒ = 1.0MHz
VDS = 15V, ID = 5.6A
VDS = 40V
VGS = 20V
VGS = -20V
ID = 5.6A
4. IRF7493
4 www.irf.com
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 8. Maximum Safe Operating Area
1 10 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
100000
C,Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 10 20 30 40 50 60
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS,Gate-to-SourceVoltage(V)
VDS= 64V
VDS= 40V
VDS= 16V
ID= 5.6A
0.2 0.4 0.6 0.8 1.0 1.2
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
ISD,ReverseDrainCurrent(A)
TJ = 25°C
TJ = 150°C
VGS = 0V
0 1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID,Drain-to-SourceCurrent(A)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
5. IRF7493
www.irf.com 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 10a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on) tr td(off) tf
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-VDD
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
25 50 75 100 125 150
TC , Case Temperature (°C)
0
2
4
6
8
10
ID,DrainCurrent(A)
1E-005 0.0001 0.001 0.01 0.1 1 10 100
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
100
ThermalResponse(ZthJC)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
6. IRF7493
6 www.irf.com
Fig 13. On-Resistance Vs. Gate VoltageFig 12. On-Resistance Vs. Drain Current
Fig 14a&b. Basic Gate Charge Test Circuit
and Waveform
Fig 15a&b. Unclamped Inductive Test circuit
and Waveforms
Fig 15c. Maximum Avalanche Energy
Vs. Drain Current
D.U.T.
VDS
IDIG
3mA
VGS
.3µF
50KΩ
.2µF12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
VGS
QG
QGS QGD
VG
Charge
tp
V(BR)DSS
IAS
RG
IAS
0.01Ωtp
D.U.T
LVDS
+
-
VDD
DRIVER
A
15V
20V
4.0 8.0 12.0 16.0
VGS, Gate -to -Source Voltage (V)
0.010
0.020
0.030
RDS(on),Drain-to-SourceOnResistance(Ω)
ID = 5.6A
25 50 75 100 125 150
Starting TJ, Junction Temperature (°C)
0
100
200
300
400
500
EAS,SinglePulseAvalancheEnergy(mJ)
ID
TOP 2.5A
4.5A
BOTTOM 5.6A
0 20 40 60 80
ID , Drain Current (A)
0.011
0.012
0.013
RDS(on),Drain-to-SourceOnResistance(Ω)
VGS = 10V
7. IRF7493
www.irf.com 7
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D =
P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+-
-
-
ƒ
„
‚
RG
VDD• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 17. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
8. IRF7493
8 www.irf.com
SO-8 Package Details
SO-8 Part Marking
EXAMPLE: THIS IS AN IRF7101 (MOSFET)
INTERNATIONAL
RECTIFIER
LOGO
F7101
YWW
XXXX
PART NUMBER
LOT CODE
WW = WEEK
Y = LAST DIGIT OF THE YEAR
DATE CODE (YWW)
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX
MILLIMETERSINCHES
MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
8 7
5
6 5
D B
E
A
e6X
H
0.25 [.010] A
6
7
K x 45°
8X L 8X c
y
0.25 [.010] C A B
e1
A
A18X b
C
0.10 [.004]
431 2
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050]
4. OUTLINE CONFORMS TO JEDECOUTLINE MS-012AA.
NOTES:
1. DIMENSIONING& TOLERANCINGPER ASME Y14.5M-1994.
2. CONTROLLINGDIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERINGTO
ASUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
8X 1.78 [.070]
9. IRF7493
www.irf.com 9
Repetitive rating; pulse width limited by
max. junction temperature.
Notes:
‚ Starting TJ = 25°C, L = 12mH
RG = 25Ω, IAS = 5.6A.
ƒ Pulse width ≤ 300µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.7/03
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS