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Optimized architecture for SNOW 3G

The document presents an optimized architecture for the Snow 3G stream cipher, employed as a confidentiality and integrity algorithm in telecommunications. It introduces two performance enhancement techniques: a novel carry-lookahead architecture to reduce propagation delay in modulo adders and a redesigned S-box to minimize chip area. The optimized architecture was implemented using VHDL on an FPGA, achieving a maximum frequency of 254.9 MHz and a throughput of 7.2235 Gbps.

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International Journal of Electrical and Computer Engineering (IJECE) Vol. 11, No. 1, February 2021, pp. 545~557 ISSN: 2088-8708, DOI: 10.11591/ijece.v11i1.pp545-557  545 Journal homepage: http://ijece.iaescore.com Optimized architecture for SNOW 3G N. B. Hulle1 , Prathiba B2 , Sarika R. Khope3 , K. Anuradha4 , Yogini Borole5 , D. Kotambkar6 1,2,3,5 Department of Electronics and Telecommunication, G H Raisoni Institute of Engineering and Technology, India 4 Department of Computer Science and Engineering, Gokaraju Rangaraju Institute of Engineering and Technology, India 6 Department of Electronics Design Technology, Shri Ramdeobaba College of Engineering and Management, India Article Info ABSTRACT Article history: Received Apr 3, 2020 Revised Jun 19, 2020 Accepted Aug 11, 2020 SNOW 3G is a synchronous, word-oriented stream cipher used by the 3GPP standards as a confidentiality and integrity algorithms. It is used as first set in long term evolution (LTE) and as a second set in universal mobile telecommunications system (UMTS) networks. The cipher uses 128-bit key and 128 bit IV to produce 32-bit ciphertext. The paper presents two techniques for performance enhancement. The first technique uses novel CLA architecture to minimize the propagation delay of the 232 modulo adders. The second technique uses novel architecture for S-box to minimize the chip area. The presented work uses VHDL language for coding. The same is implemented on the FPGA device Virtex xc5vfx100e manufactured by Xilinx. The presented architecture achieved a maximum frequency of 254.9 MHz and throughput of 7.2235 Gbps. Keywords: Cryptography FPGA SNOW 3G Stream cipher VHDL Wireless network security This is an open access article under the CC BY-SA license. Corresponding Author: N. B. Hulle, Department of Electronics and Telecommunication, G H Raisoni Institute of Engineering and Technology, Pune, India. Email: nagnath.hulle@raisoni.net 1. INTRODUCTION Security of the records is important in the systems where personal and financial matters are involved. Hiding of information from unauthorized users becomes essential in such systems and services. Cryptography is one of the widely used techniques for securing information from eavesdroppers. Considering the need to secure information many researchers are working in the area of information security. To maintain advanced network security, the concern network architecture must change from traditional security to advanced security. The same may be achieved by sinking holes in the security wall. Cryptography algorithms and their associated key are more secure when it is implemented on a hardware platform [1]. Side-channel attacks and fault attacks may exist. However, developed algorithms must be fast enough to support autonomous protocols. These protocols use different encryption algorithms for a different session. Many recent autonomous protocols like secure sockets layer (SSL) and internet protocol security (IPsec) use different ciphers for different sessions. Hardware implementation of the cryptographic algorithm on FPGA devices is attractive solutions because FPGAs are reconfigurable [2-8]. This property provides flexibility for dynamic system development and capable of implementing a wide range of functions/architectures/algorithms. It seems to be significant to emphasize FPGA based implementations of cryptographic algorithms, especially high throughput architectures [9]. SNOW 3G algorithm is the core of the 3rd generation partnership project (3GPP) algorithms UEA2 and UIA2. The 3GPP is a joint attempt between telecommunication associations (TG) to make globally applicable specifications for long term evolution (LTE) mobile phone systems [10, 11].
 ISSN: 2088-8708 Int J Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 546 The presented work uses optimized architecture for SNOW 3G stream cipher. This architecture requires only 2K bytes of memory for implementation of S-box in place of 8K bytes of memory required for the existing SNOW 3G architectures [10-16]. The paper is arranged in the following sections. Section-2 provides initial versions of SNOW stream cipher [17]. Section-3 provides the working and design parameters of the SNOW 3G algorithm. Section-4 lists existing work related to presented techniques. Section-5 presents optimized SNOW 3G architecture and its analysis. The results are discussed in Section-6 and Section-7 concludes the presented work. 2. INITIAL VERSIONS OF SNOW The researcher Patrik Ekdahl et. al. proposed a stream cipher SNOW (SNOW 1.0) in the year 2000 [18], after two years Hawkes et. al. described a new attack known as a guess-and-determine attack [19] on SNOW 1.0. SNOW 1.0 has two limitations. The first limitation was finite state machine (FSM) has a single input, which allows the attacker to disturb the working procedure in FSM and second SNOW 1.0 was little unlucky in choosing feedback polynomial. This allows creating bitwise correspondence in FSM and which is the base of distinguishing attack. Patrik Ekdahl et. al. the proposed a new version of SNOW cipher as SNOW 2.0 [20] with modifications in SNOW 1.0 [18]. They provided two inputs to FSM and modified feedback polynomial in the new version SNOW 2.0. The two inputs to FSM in SNOW 2.0 makes the guess-and-determine attack more difficult because FSM update registers R1 and R2 do not depend only on FSM output. The polynomial selection in SNOW 1.0 was made to speed up the multiplication by left shift operation in LFSR. This allows the result of multiplication to appear at many places as a bit shifted version of the original word. Such a selection of polynomial provides a base for correlation attack in the initial version [18]. SNOW 2.0 provides better distribution of the bits in feedback function by defining field (F_2^32) as an extension over the field (F_2^8). Each multiplication was implemented as shifting the content by one byte and unconditional XOR with 256 possible patterns. So SNOW 2.0 [20] is strong against correlation attack as compared to Snow 1.0 [18]. During the evaluation of The European Telecommunications Standards Institute (ETSI)/Security Algorithms Group of Experts (SAGE), the SNOW 2.0 was further modified to increase its resistance against algebraic attacks and the new design named as SNOW 3G [10]. 3. SPECIFICATIONS AND WORKING OF SNOW 3G SNOW 3G generates a 32-bit ciphertext per clock cycle with the help of a 128-bit key and 128-bit initialization vector (IV) as shown in Figure 1. It consists of the main four modules initial operations, linear feedback shift register (LFSR), finite state machine (FSM), and a feedback path. The initial operations will divide 128 bit Key into four blocks as per equations (01), (02), (03), and (04). Similarly, it also divides 128 bit IV into four blocks as per equations (05), (06), (07), and (08) [10]. 𝐾3 = 𝑘[0] ‖ 𝑘[1] ‖ 𝑘[2] ‖ … ‖ 𝑘[31] (1) 𝐾2 = 𝑘[32] ‖ 𝑘[33] ‖ 𝑘[34] ‖ … ‖ 𝑘[63] (2) 𝐾1 = 𝑘[64] ‖ 𝑘[65] ‖ 𝑘[66] ‖ … ‖ 𝑘[95] (3) 𝐾0 = 𝑘[96] ‖ 𝑘[97] ‖ 𝑘[98] ‖ … ‖ 𝑘[127] (4) 𝐼𝑉3 = 𝑖𝑣[0] ‖ 𝑖𝑣[1] ‖ 𝑖𝑣[2] ‖ … ‖ 𝑖𝑣[31] (5) 𝐼𝑉2 = 𝑖𝑣[32] ‖ 𝑖𝑣[33] ‖ 𝑖𝑣[34] ‖ … ‖ 𝑖𝑣[63] (6) 𝐼𝑉1 = 𝑖𝑣[64] ‖ 𝑖𝑣[65] ‖ 𝑖𝑣[66] ‖ … ‖ 𝑖𝑣[95] (7) 𝐼𝑉0 = 𝑖𝑣[96] ‖ 𝑖𝑣[97] ‖ 𝑖𝑣[98] ‖ … ‖ 𝑖𝑣[127] (8) where 𝑘[0], 𝑖𝑣[0] are LSB part and 𝑘[127], 𝑖𝑣[127] are MSB part of the key and IV respectively. Initial operations are performed on key and iv as per Table 1. The output of the initial operations block is loaded into LFSR before the first clock cycle [10]. The second module LFSR consists of sixteen stages each having parallel 32 bits. Contents of LFSR are shifted from MSB (S15) to LSB (S0) in each clock cycle. S15 receives new value from the feedback path at each clock cycle. Third module FSM consists of
Int J Elec & Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 547 three parallel 32-bit update registers R1, R2, R3, two S-Boxes S1, S2 each of 4Kbytes, two 32 bit modulo adders and two 32 bit XOR gates. The final module is the feedback path which consists of functions MULα, DIVα, and many XOR operations. The two functions MULα and DIVα are implemented as lookup tables. Divide KEY and IV 128 32 32 32 32 32 K0 K1 K2 K3 IV0 IV1 IV2 IV3 Initial Operations S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 128 LFSR S5 S15 S2 S11 S0 FSM 32 32 Feedback 32 32 Key Stream 32 32 32 F v Key IV Mode 0 1 0: Initialization mode 1: Keystream mode Clk Rst1 Rst2 Figure 1. Existing SNOW 3G architectures Table 1. LFSR initialization calculations 𝑆0 = 𝐾0 ⊕ 1 𝑆4 = 𝐾0 𝑆8 = 𝐾0 ⊕ 1 𝑆12 = 𝐾0 ⊕ 𝐼𝑉1 𝑆1 = 𝐾1 ⊕ 1 𝑆5 = 𝐾1 𝑆9 = 𝐾1 ⊕ 1 ⊕ 𝐼𝑉3 𝑆13 = 𝐾1 𝑆2 = 𝐾2 ⊕ 1 𝑆6 = 𝐾2 𝑆10 = 𝐾2 ⊕ 1 ⊕ 𝐼𝑉2 𝑆14 = 𝐾2 𝑆3 = 𝐾3 ⊕ 1 𝑆7 = 𝐾3 𝑆11 = 𝐾3 ⊕ 1 𝑆15 = 𝐾3 ⊕ 𝐼𝑉0 SNOW 3G works into two modes of operation, initialization mode and keystream mode. At the start of initialization, the model system should reset LFSR and FSM using terminals Rst1 and Rst2 respectively. In the first clock cycle values calculated in the initialization, a mode is loaded into sixteen stages of LFSR but FSM registers should remain in a reset state. In the second clock cycle, Rst2=0 and now LFSR is clocked. At each clock, 32-bit output F of FSM is combined with S0, S2 & S11 in the feedback path by selecting mode 0 from a select line of the multiplexer and applied to S15 as intermediate signal v. The following equation provides the intermediate signal v in the initialization mode [10]. 𝑣 = (𝑆0,1‖𝑆0,2‖𝑆0,3‖0𝑥00) ⊕ 𝑀𝑈𝐿𝛼(𝑆0,0) ⊕ S2 ⊕ (0𝑥00‖𝑆11,0‖𝑆11,1‖𝑆11,2) ⊕ 𝐷𝐼𝑉 𝛼(𝑆11,3) ⊕ F (9) After 32 clock cycles, SNOW 3G enters into keystream mode. Operations in this mode are the same as initialization mode but the only difference is that output F of FSM is not combined in feedback path by making mode = 1 from the multiplexer. The intermediate signal in keystream mode is given by the following equation [10]. 𝑣 = (𝑆0,1‖ 𝑆0,2‖𝑆0,3‖0𝑥00) ⊕ 𝑀𝑈𝐿𝛼(𝑆0,0) ⊕ S2 ⊕ (0𝑥00‖𝑆11,0‖𝑆11,1‖𝑆11,2) ⊕ 𝐷𝐼𝑉 𝛼(𝑆11,3) (10) In keystream mode, FSM is clocked for one clock cycle and its first output is discarded when it is clocked for n clock cycles to encrypt n number of 32-bit words, where n = number of 32-bit data words is to be encrypted [10].
 ISSN: 2088-8708 Int J Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 548 4. RELATED WORK The study of existing architectures of SNOW 3G evolved two challenges. One minimizing propagation delay of the 232 modulo adders and other is minimizing the chip area of S-boxes. The researcher Kitsos et al. [12] realized S-boxes using 8 lookup tables. Each lookup table consumes 1 KB memory, so memory used for S-box realization is 8 KB. Jairaj et al. used symmetry of S-box lookup tables to minimize cache requirement in the software implementation of SNOW 3G [21]. Kitsos et al. [12] used conventional CLA for modulo adder implementation. The researcher Pai and Chen [22] presented a modified CLA design to minimize the propagation delay. Traboulsi et al. [23] implemented SNOW 3G on an embedded platform. The motive of the design was to minimize the memory required for S-box implementation. Researchers used 2 lookup tables in place of 8 lookup tables for implementation of 2 S-boxes. Eight-bit shifting with cache memory is used efficiently to minimize memory requirement. 5. PRESENTED SNOW 3G ARCHITECTURE Considering the challenges of existing FSM, the proposed implementation uses the following refinements to improve the performance of the SNOW 3G algorithm. - Use of novel modulo CLA architecture over 232 to minimize propagation delay in FSM, which decides the critical delay of the algorithm - Use of novel S-Box architecture to minimize chip area 5.1. Novel modulo CLA architecture over 232 Modulo adders are usually implemented by using ripple-carry adders, but this technique increases the propagation delay of the critical path. The propagation delay of n bit ripple carries adder is (2n+1) gate delays. Modulo adder over 232 implemented by using ripple-carry adders will have delay of (2*32+1 = 65) 65 gates delay, assuming average gate delay of 10 ηs the total delay of one modulo adder will be 65*10 = 650 ηs. FSM consists of two such adders so a total delay of modulo adders for single computation will be 1300 ηs. The propagation delay of modulo adders can be minimized by using CLA for its implementation. Existing CLAs are realized by using basic gates i.e. AND, XOR, and OR gates, but Pai et al. realized CLA by using universal gates i.e. NAND or NOR gates [22]. The same design minimized gate requirement as compared to existing architectures. At the same time, this CLA [22, 24] designs are faster than conventional CLA architectures. Adder architecture [25] developed for LILI-II cipher uses different approach for addiation. Reduction in propagation delay and chip area is possible in existing architectures [12-16, 22], so the presented research work uses universal gates for CLA implementation and other techniques to minimize the number of gates required. Novel modulo CLA architecture over 232 uses following three architectures in multilevel CLA designs for performance improvement - 4 bit CLA at LSB (to calculate S0 to S3) - 4 bit CLA at middle stages (to calculate S4 to S27) - 4 bit CLA at MSB (to calculate S28 to S31) Using the above CLA architectures novel architecture for modulo CLA over 232 was designed as shown in Figure 2. Presented modulo adder architecture is an area, propagation delay, and energy-efficient as compared to existing modulo CLA architectures. Gate reduction at level 2, Stage 1 Unused logic circuit reduction Four bit LSB adder Four bit middle stage adder Four bit MSB adder Gate reduction at level 3, stage 1 FA_WC S0 G0 B0 A0 FA_NAND S1 G1 P1 B1 A1 C1 FA_NAND S2 G2 P2 B2 A2 C2 FA_NAND S3 G3 P3 B3 A3 C3 GG0 FA_NAND S4 G4 P4 B4 A4 C4 FA_NAND S5 G5 P5 B5 A5 C5 FA_NAND S6 G6 P6 B6 A6 C6 FA_NAND S7 G7 P7 B7 A7 C7 GG1 PG1 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 FA_NAND S8 G8 P8 B8 A8 C8 FA_NAND S9 G9 P9 B9 A9 C9 FA_NAND S10 G10 P10 B10 A10 C10 FA_NAND S11 G11 P11 B11 A11 C11 GG2 PG2 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 FA_NAND S12 G12P12 B12 A12 C12 FA_NAND S13 G13P13 B13 A13 C13 FA_NAND S14 G14 P14 B14 A14 C14 FA_NAND S15 G15 P15 B15 A15 C15 GG3 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 PG3 GG16 FA_NAND S16 G16P16 B16 A16 FA_NAND S17 G17P17 B17 A17 C17 FA_NAND S18 G18 P18 B18 A18 C18 FA_NAND S19 G19 P19 B19 A19 C19 GG4 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 PG4 FA_NAND S20 G20P20 B20 A20 FA_NAND S21 G21P21 B21 A21 C21 FA_NAND S22 G22 P22 B22 A22 C22 FA_NAND S23 G23 P23 B23 A23 C23 GG5 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 PG5 FA_NAND S24 G24P24 B24 A24 FA_NAND S25 G25P25 B25 A25 C25 FA_NAND S26 G26 P26 B26 A26 C26 FA_NAND S27 G27 P27 B27 A27 C27 GG6 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 PG6 C16 C20 C24 FA_NAND S28 G28 P28 B28 A28 FA_NAND S29 G29 P29 B29 A29 C29 FA_NAND S30 G30 P30 B30 A30 C30 FA_NAND_WGIPI S31 B31 A31 C31 C28 Figure 2. Novel modulo CLA architecture over 232
Int J Elec & Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 549 5.2. Novel S-Box architecture Two S-boxes S1 & S2 are used in SNOW 3G architecture each requires memory of 4 KB. The lookup table of S1 is taken from the Rijndael substitution box and a lookup table of S2 is based on Dickson polynomial over GF-28. As per design specification, each S-box (S1 or S2) is implemented by using 4 lookup tables and each lookup table has 256 values each of 4 bytes. So the implementation of each lookup table requires (256x4 = 1024bytes of memory). Each S-box has 4 lookup tables, so total memory required for the implementation of S1 or S2 is (4x1024 = 4K) 4KB. The total memory needed for the realization of two S-boxes is 8KB. Existing implementation [10-16, 26-29] uses S-box architecture as shown in Figure 3. S1_T0 S1_T1 S1_T2 S1_T3 32 8 8 8 8 32 32 32 32 32 S2_T0 S2_T1 S2_T2 S2_T3 32 8 8 8 8 32 32 32 32 32 S-box S1 Implementation S-box S2 Implementation Figure 3. Existing S-boxes architecture The four lookup tables of S1 i.e. S1_T0 to S1_T3 as shown in Figure 3 has the same content but exist in 8 bit shifted form. Analogous is the case of S-box S2. Presented novel S-box architectures use a single lookup table for implementation of S-box (S1 or S2). Presented research work uses two architectures for S-box implementation. First architecture as shown in Figure 4, consumes fewer resources but useful to low-frequency applications only. Second architecture as shown in Figure 5, consumes fewer resources as compared to existing architectures but required more resources as compared to Novel S-box architecture-1. Addr1 Addr2 Addr3 Addr4 DataOut1 DataOut2 DataOut3 DataOut4 8 8 8 8 32 32 32 32 Multiport ROM 8 32 32 Bit Latch 32 32 32 32 32 Bit Latch 32 Bit Latch 32 Bit Latch 2 Bit Counter Figure 4. Novel S-Box architecture1 Presented designs require 2 KB of memory for the realization of S-boxes S1 & S2. These designs save 6 KB of memory as compared to existing designs. S-box architecture-1 saves 6 KB memory at the cost of some additional hardware (Single 2-bit counter, two 4 I/p multiplexers, and four 32 bit latches). This architecture is 4 times slower than conventional architectures and useful for low-frequency applications. S-box architecture-2 has the same speed as conventional architectures but uses 4 additional 256:1 multiplexers. The second architecture can be used for low and high-speed applications depending on cost and speed tradeoffs
 ISSN: 2088-8708 Int J Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 550 LOC1 LOC0 LOC255 MUX MUX MUX Out1 for A1 Out2 for A2 Out4 for A4 Address A1 Address A2 Address A4 32 32 32 8 8 8 Figure 5. Novel S-Box architecture 2 5.3. Optimized SNOW 3G architecture Optimized SNOW 3G architecture as shown in Figure 6 is designed using novel modulo CLA architecture and novel S-Box architecture as discussed in the previous section. SNOW 3G architecture designed using S-Box architecture-1 is used for low-frequency applications and needs two clock arrangements. Whereas SNOW 3G architecture designed using S-Box architecture-2 is used for high-frequency applications and needs a single clock. Internal block diagram of optimized SNOW 3G architecture as shown in Figure 7. Divide KEY and IV 128 32 32 32 32 32 K0 K1 K2 K3 IV0 IV1 IV2 IV3 Initial Operations S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 128 LFSR S5 S15 S2 S11 S0 Feedback 32 32 Key Stream 32 32 32 F v Key IV Mode 0 1 0: Initialization mode 1: Keystream mode Clkfast Rst1 S1 and S2 Logic 2 bit Register Clkslow Other logic in FSM Rst2 FSM Figure 6. Top module of refined SNOW 3G architecture
Int J Elec & Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 551 32 32 32 S0 S1 S2 S5 S14 S15 .. .. .. LFSR 32 R3 R1 S2-BOX R2 S1-BOX 32 32 32 32 32 32 32 32 32 Feedback FSM Mode 0 1 32 S11 Divide KEY and IV 128 K0 K1 K2 K3 IV0 IV1 IV2 IV3 Initial Operations S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 128 KEY IV Key Stream Out 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 DIVα >> 8 32 32 32 32 MULα << 8 32 0: Initialization mode 1: Keystream mode 0 1 F v Mod CLA Mod CLA Figure 7. Internal block diagram of optimized SNOW 3G architecture FSM of SNOW 3G architecture consists of two modulo adders and two S-Boxes. Two modulo adders will decide the speed of the algorithm and two S-boxes will decide hardware utilization of the algorithm. The use of novel modulo CLA over 232 minimizes propagation delay and the use of novel S-box architecture minimizes hardware utilization. These refinements help to improve the performance of the SNOW 3G algorithm in terms of throughput and area. Optimized SNOW 3G architecture uses VHDL language for coding. The same is implemented on the FPGA device Virtex xc5vfx100e manufactured by Xilinx [30]. The presented architecture achieved a maximum frequency of 254.9 MHz and throughput of 7.2235 Gbps. Table 2 shows particulars about the technology used. Figure 8 and Figure 9 show RTL schematic and output waveform of the presented architecture respectively. Table 2. Technology used details SNOW3GNEW Project Status (05/03/2020 - 11:34:41) Project File: SNOW3GOPT.xise Parser Errors: No Errors Module Name: SNOW3G Implementation State: Synthesized Target Device: xc5vfx100t-3ff1136  Errors: No Errors Product Version: ISE 13.2  Warnings: No Warnings Design Goal: Balanced  Routing Results: Design Strategy: Xilinx Default (unlocked)  Timing Constraints: Environment: System Settings  Final Timing Score:
 ISSN: 2088-8708 Int J Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 552 Figure 8. RTL schematic Figure 9. Output waveform 6. RESULT AND DISCUSSIONS The following section discusses the result in terms of area, propagation delay, throughput, and memory utilized for presented SNOW 3G architecture. 6.1. The area 6.1.1. Novel modulo CLA architecture over 232 Presented novel modulo CLAs are used as modulo adders over 232 in Optimized SNOW 3G architecture. A comparison of device utilization of existing [13, 22] and presented architectures is shown in Figure 10.
Int J Elec & Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 553 Figure 10. Comparisons of hardware utilization for CLA architectures 6.1.2. Novel S-Box architecture Optimized SNOW 3G architecture uses Novel S-box architecture to avoid redundancy of lookup tables. Presented Novel S-Box architecture-1 is suitable for low-frequency applications and Novel S-Box architecture-2 is useful for high-frequency applications. The use of these novel architectures minimizes hardware requirement as shown in the Figure 11. The comparison shows that the hardware resources used in the presented architectures are less than existing architectures [12-16]. The reduction in area is possible because S-box is designed using one lookup table in place of four lookup tables. Figure 11. Comparisons of hardware utilization for S-box 6.1.3. Optimized SNOW 3G architecture Optimized SNOW 3G architecture uses refined modulo CLA over 232 and refined S-box to for performance improvement. Hardware resources used by optimized SNOW 3G architecture are presented in Table 3 and Table 4 shows comparisons of hardware resources used by optimized SNOW 3G and existing architectures [12-16]. The comparison shows that optimized SNOW 3G architecture utilizes minimum resources as compared to architecture presented Kitsos et al. [13], Madani and anougast [15] and Madani et al. [16]. The architecture presented by Kitsos et al. [12] is ASIC, so the comparison is difficult. The architecture presented by Zhang et al. [14] uses less hardware as compared to proposed refined architecture because only one mode implemented on hardware. 94 52 55 102 57 57 103 57 55 0 20 40 60 80 100 120 4 input LUTs Occupied Slices Slices containing Related Logic Presented Novel Modulo CLA Exisisting Conventional CLA [13] Exisisting Modified CLA [22] 534 1152 2048 748 2304 4164 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Proposed Low Frequency Architecture Proposed High frequency Architecture Existing Architectures [12, 13, 14, 15, 16] No. of slices used Number of 4 input LUTs
 ISSN: 2088-8708 Int J Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 554 Table 3. Device utilization summary of optimized SNOW 3G architecture Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization 1. Number of Slice Registers 870 64000 1% 2. Number of Slice LUTs 1208 64000 1% 3. Number of fully used LUT-FF pairs 680 1398 48% 4. Number of bonded IOBs 325 640 50% 5. Number of BUFG/BUFGCTRLs 10 32 31% Table 4. Comparison of hardware resources for different architectures Sr. No. Architectures Hardware resources used 1 Proposed Refined Architecture 870 Slice Registers and 1208 slice LUTs on Virtex 5 2 The architecture proposed by P. Kitsos et al. [12] ASIC implementation used 25016 equivalent gates 3 The architecture proposed by P. Kitsos et al. [13] Slices used 3559 on Spartan 3 Family 4 The architecture proposed by L. Zhang et al. [14] Only one mode implemented on hardware to increase throughput with minimum hardware resources, 356 slices on Virtex 5 5 The architecture proposed by Mahdi Madani and Camel Tanougast [15] 1020 Slice Registers and 889 Slice LUTs on Virtex5 6 The architecture proposed Mahdi Madani, Ilyas Benkhaddra et al. [16] 912 Slice Registers and 1108 Slice LUTs on Virtex 5 6.2. Propagation delay 6.2.1. Novel modulo CLA over 232 Propagation delay comparison of proposed refined CLA and existing CLA architectures [13, 22] is shown in Figure 12. Propagation delay evaluation shows that delay of presented novel modulo CLA architecture is fewer than existing CLA architectures. The presented CLA architecture will help to improve the throughput of Optimized SNOW 3G architecture. Figure 12. Delay comparisons of novel and existing CLA architectures 6.2.2. Novel S-Box architecture The combinational path delay comparisons of proposed refined S-box architectures and existing S-box architectures [12-16] are shown in the Table 5. The comparison shows that the propagation delay of proposed low-frequency architecture is more as compared to other architectures, with less hardware. Similarly, the propagation delay of proposed high-frequency architecture is less as compared to other architectures with moderate hardware utilization. The path delay of existing architectures is more as compared to presented architecture 1 but less as compared to architecture 2. The hardware resources used by existing architecture are more as compared to other architectures.
Int J Elec & Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 555 Table 5. Hardware used and propagation delay comparison of S-box implementations Sr. No. S- Box architectures No. of slices used Number of 4 input LUTs Propagation delay (ns) 1 Proposed Low-Frequency Architecture 534 748 9.92 2 Proposed High-frequency Architecture 1152 2304 9.12 3 Existing Architecture 2048 4164 9.34 6.3. Throughput and memory Comparisons of throughput achieved and memory used for S-box realization of optimized SNOW 3G and existing SNOW 3G [12-16] architectures are shown in Figure 13. The comparison shows that throughput of optimized SNOW 3G is higher than architecture presented by Kitsos et al. [13], close to architecture presented by Kitsos et al. [12], but less than architecture presented by Zhang et al. [14], Madani and Tanougast [15] and Madani et al. [16]. This may be due to the use of more hardware resources. Figure 13. Comparisons throughput and memory used for the realization of S-boxes 7. CONCLUSION Optimized SNOW 3G architecture is presented in the paper uses novel modulo CLA and novel S-box architecture. The use of novel CLA minimizes hardware required for modulo adders and minimizes propagation delay as compared to existing architectures. The use of novel S-box architecture minimizes 6 K bytes of memory as compared to existing architectures. The presented architecture uses 2K bytes of memory, whereas existing architectures 8 K bytes of memory for the same. The presented SNOW architecture attained throughput of 7.2463 Gbps at a clock frequency of 226.562 MHz. Presented architecture achieves throughput more than architecture and close to ASIC implementation. The throughput of existing architectures is more than the presented architecture. It may be due to: (1) S-boxes used in these architectures use 8 KB memory for S-box realizations; (2) Architecture uses a software platform that helps to minimize hardware and to increase throughput; (3) Architecture is ASIC realization and ASIC designs are always faster than FPGA realizations. REFERENCES [1] C. Y. Yan and R. Xiao, “Study of block algorithms implement on hardware in an information security system,” in Business Management and Electronic Information (BMEI), pp. 589-593, 2011. [2] P. Leglise, et al., “Efficient Implementation of Recent Stream Ciphers on Reconfigurable Hardware Devices,” in 26th Symposium on Information Theory in the Benelux, pp. 261-268, 2005. [3] B. Prathiba, et al., “FPGA Implementation of Smart Cryptography Algorithm,” in International Journal of Recent Technology and Engineering (IJRTE), vol. 8, no. 5, pp. 3017-3020, 2020. [4] B. Wang and L. Liu, “A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing,” in IEEE International Symposium on Circuits and Systems, vol. 14, pp. 1182-1185, 2015. [5] Y. Chen, et al., “Research and Implementation of Reconfigurable Architectures of DES and ZUC,” in Second Advanced Information Technology, Electronic and Automation Control Conference (IAEAC), vol. 7, no. 1, pp. 216-220, 2017.
 ISSN: 2088-8708 Int J Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 556 [6] N. B. Hulle, et al., “Compact Reconfigurable Architecture for Sosemanuk Stream Cipher,” in International Journal of Engineering and Advanced Technology (IJEAT), vol. 9, no. 3, pp. 607-611, 2020. [7] A. Khalid, et al., “RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1072-1084, 2017. [8] G. Paul and A. Chattopadhyay, “Three Snakes in One Hole : A 67 Gbps Flexible Hardware for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes,” in IACR Cryptology ePrint Archive, pp. 1-19, 2013. [9] M. Galanis, et al., “Comparison of the Hardware Implementation of Stream Ciphers,” The International Arab Journal of Information Technology, vol. 2, no. 4, pp. 267-274, 2005. [10] “Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2 & UIA2, Document 2: SNOW 3G specification,” ETSI/SAGE Specification, Version 1.1, 2006. [11] “Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2 & UIA2, Document 3: Implementor’s Test Data,” ETSI/SAGE Specification, Version 1.1, 2012. [12] P. Kitsos, et al., “High-Performance ASIC Implementation of the SNOW 3G Stream Cipher,” in IFIP/IEEE VLSI- SOC 2008 - International Conference on Very Large Scale Integration (VLSI SOC), Rhodes Island, Greece, pp. 1-4, 2008. [13] P. Kitsos, et al., “FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0,” Microprocessors and Microsystems, vol. 37, no. 2, pp. 235-245, 2013. [14] L. Zhang, et al., “Evaluating the Optimized Implementations of SNOW 3G and ZUC on FPGA,” in Trust, Security and Privacy in Computing and Communications (TrustCom), pp. 436-442, 2012. [15] M. Madani and C. Tanougast, “Combined and Robust SNOW-ZUC Algorithm Based on Chaotic System,” in 2018 International Conference on Cyber Security and Protection of Digital Services, Cyber Security, pp. 1-7, 2018. [16] M. Madani, et al., “Digital Implementation of an Improved LTE Stream Cipher Snow-3G Based on Hyperchaotic PRNG,” Security and Communication Networks, vol. 2017, no. 2, pp. 1-15, 2017. [17] R. D. Kharadkar and N. B. Hulle, “FPGA Implementation of Modulo (231 -1) Adder,” in 7th International Conference on Emerging Trends in Engineering & Technology, Kobe, Japan, pp. 85 -90, 2015. [18] P. Ekdahl and T. Johansson, “SNOW - a new stream cipher,” in RST open Nessie workshop, Heverlee, Belgium, pp. 1-17, 2001. [19] P. Hawkes and G. G. Rose, “Guess-and-Determine Attacks on SNOW,” in SAC 2002 Revised Papers from the 9th Annual International Workshop on Selected Areas in Cryptography, pp. 37-46, 2002. [20] P. Ekdahl and T. Johansson, “A New Version of the Stream Cipher SNOW,” in International Workshop on Selected Areas in Cryptography, pp. 47-61, 2002. [21] V. Jairaj, et al., “High Performance Implementation of Snow3G Algorithm in Memory Limited Environments,” in New Technologies, Mobility, and Security (NTMS), no. 5, pp. 1-4, 2011. [22] Y. Pai and Y. Chen, “The Fastest Carry Lookahead Adder,” in Second IEEE International Workshop on Electronic Design, Test and Applications, no. 1, pp. 4-6, 2004. [23] S. Traboulsi, et al., “An Optimized Parallel and Energy-Efficient Implementation of SNOW 3G for LTE Mobile Devices,” in International Conference on Communication Technology (ICCT), pp. 535-538, 2010. [24] N. B. Hulle, et al., “The Novel Architecture for Carry Lookahead Adder,” Technical Journal of The Institution of Engineers (India), Pune Local Centre, vol. 36, no. 1, pp. 84-88, 2012. [25] N. B. Hulle, et al., “High Performance Architecture for LILI-II Stream Cipher,” in International Journal of Computer Applications, vol. 107, no. 13, pp. 10-13, 2014. [26] G. Orhanou, et al., “SNOW 3G Stream Cipher Operation and Complexity Study,” Contemporary Engineering Sciences, vol. 3, no. 3, pp. 97-111, 2010. [27] S. Hessel, et al., “Implementation and Benchmarking of Hardware Accelerators for Ciphering in LTE Terminals,” in Global Telecommunications Conference, pp. 1-7, 2009. [28] N. P. Maity and R. Maity, “Design and Modelling of Paralleled RAM Architecture,” in International Conference on Future Information Technology, vol. 13, pp. 98-102, 2011. [29] A. Bikos and N. Sklavos, “Architecture Design of an Area Efficient High-Speed Crypto Processor for 4G LTE,” IEEE Transactions on Dependable and Secure Computing, vol. 15, no. 5, pp. 729-741, 2018. [30] xilinx.com, “XUPV5-LX110T,” 2015. [Online], Available: http://www.xilinx.com/univ/xupv5-lx110t.htm. BIOGRAPHIES OF AUTHORS Dr. N. B. Hulle is an Associate Professor at G H Raisoni Institute of Engineering and Technology, Pune, Maharashtra, India. He completed his Bachelor's and Masters from Dr. Babasaheb Ambedkar Marathwada University, Aurangabad, Maharashtra, India, and Ph.D. from Rashtrasant Tukadoji Maharaj Nagpur University, Nagpur, Maharashtra, India. He has 21 years of teaching experience. He guides UG and PG students. His area of research is VLSI, cryptography & Wireless Network Security. He published papers in National & International Journals and conferences. Dr. N. B. Hulle is a life member of ISTE and IETE.
Int J Elec & Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 557 B. Prathiba is an Assistant Professor at G H Raisoni Institute of Engineering and Technology, Pune, Maharashtra, India. She has published articles in various international publications in the area of Wireless Sensor Networks. Her interested areas are Wireless Sensor Networks, Microcontrollers, and VLSI. B. Prathiba is a life member of ISTE and IETE. Sarika R. Khope is an Assistant Professor at G H Raisoni Institute of Engineering and Technology, Pune, Maharashtra, India. She has published the articles in various international publications in the area of Image steganography, Image Fusion, and VLSI Her interested areas are Digital Systems Design, Machine Learning, and VLSI. Sarika Khope is a life member of ISTE. Dr. K. Anuradha is a Professor and Dean ICT at Gokaraju Rangaraju Institute of Engineering & Technology, Hyderabad, Telangana, India. She is specialized in the areas of Data mining, Image Processing, Machine Learning, Network Security and Computer Networks. Yogini Borole is an Assistant Professor at G H Raisoni Institute of Engineering and Technology, Pune, Maharashtra, India. She has published the articles in various international publications in the area of DSP and VLSI. Her interested areas are Digital Signal Processing, Power Electronics, and VLSI. Yogini Borole is a life member of ISTE and IETE. Dr. D. Kotambkar is an Assistant Professor at Shri Ramdeobaba College of Engineering and Management, Nagpur, Maharashtra, India. She has published the articles in various international publications in the area of MIMO Wireless Communication.Her interested areas are Digital Signal Processing and Wireless Communication..She is a life member of IETE.

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Optimized architecture for SNOW 3G

  • 1.
    International Journal ofElectrical and Computer Engineering (IJECE) Vol. 11, No. 1, February 2021, pp. 545~557 ISSN: 2088-8708, DOI: 10.11591/ijece.v11i1.pp545-557  545 Journal homepage: http://ijece.iaescore.com Optimized architecture for SNOW 3G N. B. Hulle1 , Prathiba B2 , Sarika R. Khope3 , K. Anuradha4 , Yogini Borole5 , D. Kotambkar6 1,2,3,5 Department of Electronics and Telecommunication, G H Raisoni Institute of Engineering and Technology, India 4 Department of Computer Science and Engineering, Gokaraju Rangaraju Institute of Engineering and Technology, India 6 Department of Electronics Design Technology, Shri Ramdeobaba College of Engineering and Management, India Article Info ABSTRACT Article history: Received Apr 3, 2020 Revised Jun 19, 2020 Accepted Aug 11, 2020 SNOW 3G is a synchronous, word-oriented stream cipher used by the 3GPP standards as a confidentiality and integrity algorithms. It is used as first set in long term evolution (LTE) and as a second set in universal mobile telecommunications system (UMTS) networks. The cipher uses 128-bit key and 128 bit IV to produce 32-bit ciphertext. The paper presents two techniques for performance enhancement. The first technique uses novel CLA architecture to minimize the propagation delay of the 232 modulo adders. The second technique uses novel architecture for S-box to minimize the chip area. The presented work uses VHDL language for coding. The same is implemented on the FPGA device Virtex xc5vfx100e manufactured by Xilinx. The presented architecture achieved a maximum frequency of 254.9 MHz and throughput of 7.2235 Gbps. Keywords: Cryptography FPGA SNOW 3G Stream cipher VHDL Wireless network security This is an open access article under the CC BY-SA license. Corresponding Author: N. B. Hulle, Department of Electronics and Telecommunication, G H Raisoni Institute of Engineering and Technology, Pune, India. Email: nagnath.hulle@raisoni.net 1. INTRODUCTION Security of the records is important in the systems where personal and financial matters are involved. Hiding of information from unauthorized users becomes essential in such systems and services. Cryptography is one of the widely used techniques for securing information from eavesdroppers. Considering the need to secure information many researchers are working in the area of information security. To maintain advanced network security, the concern network architecture must change from traditional security to advanced security. The same may be achieved by sinking holes in the security wall. Cryptography algorithms and their associated key are more secure when it is implemented on a hardware platform [1]. Side-channel attacks and fault attacks may exist. However, developed algorithms must be fast enough to support autonomous protocols. These protocols use different encryption algorithms for a different session. Many recent autonomous protocols like secure sockets layer (SSL) and internet protocol security (IPsec) use different ciphers for different sessions. Hardware implementation of the cryptographic algorithm on FPGA devices is attractive solutions because FPGAs are reconfigurable [2-8]. This property provides flexibility for dynamic system development and capable of implementing a wide range of functions/architectures/algorithms. It seems to be significant to emphasize FPGA based implementations of cryptographic algorithms, especially high throughput architectures [9]. SNOW 3G algorithm is the core of the 3rd generation partnership project (3GPP) algorithms UEA2 and UIA2. The 3GPP is a joint attempt between telecommunication associations (TG) to make globally applicable specifications for long term evolution (LTE) mobile phone systems [10, 11].
  • 2.
     ISSN: 2088-8708 IntJ Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 546 The presented work uses optimized architecture for SNOW 3G stream cipher. This architecture requires only 2K bytes of memory for implementation of S-box in place of 8K bytes of memory required for the existing SNOW 3G architectures [10-16]. The paper is arranged in the following sections. Section-2 provides initial versions of SNOW stream cipher [17]. Section-3 provides the working and design parameters of the SNOW 3G algorithm. Section-4 lists existing work related to presented techniques. Section-5 presents optimized SNOW 3G architecture and its analysis. The results are discussed in Section-6 and Section-7 concludes the presented work. 2. INITIAL VERSIONS OF SNOW The researcher Patrik Ekdahl et. al. proposed a stream cipher SNOW (SNOW 1.0) in the year 2000 [18], after two years Hawkes et. al. described a new attack known as a guess-and-determine attack [19] on SNOW 1.0. SNOW 1.0 has two limitations. The first limitation was finite state machine (FSM) has a single input, which allows the attacker to disturb the working procedure in FSM and second SNOW 1.0 was little unlucky in choosing feedback polynomial. This allows creating bitwise correspondence in FSM and which is the base of distinguishing attack. Patrik Ekdahl et. al. the proposed a new version of SNOW cipher as SNOW 2.0 [20] with modifications in SNOW 1.0 [18]. They provided two inputs to FSM and modified feedback polynomial in the new version SNOW 2.0. The two inputs to FSM in SNOW 2.0 makes the guess-and-determine attack more difficult because FSM update registers R1 and R2 do not depend only on FSM output. The polynomial selection in SNOW 1.0 was made to speed up the multiplication by left shift operation in LFSR. This allows the result of multiplication to appear at many places as a bit shifted version of the original word. Such a selection of polynomial provides a base for correlation attack in the initial version [18]. SNOW 2.0 provides better distribution of the bits in feedback function by defining field (F_2^32) as an extension over the field (F_2^8). Each multiplication was implemented as shifting the content by one byte and unconditional XOR with 256 possible patterns. So SNOW 2.0 [20] is strong against correlation attack as compared to Snow 1.0 [18]. During the evaluation of The European Telecommunications Standards Institute (ETSI)/Security Algorithms Group of Experts (SAGE), the SNOW 2.0 was further modified to increase its resistance against algebraic attacks and the new design named as SNOW 3G [10]. 3. SPECIFICATIONS AND WORKING OF SNOW 3G SNOW 3G generates a 32-bit ciphertext per clock cycle with the help of a 128-bit key and 128-bit initialization vector (IV) as shown in Figure 1. It consists of the main four modules initial operations, linear feedback shift register (LFSR), finite state machine (FSM), and a feedback path. The initial operations will divide 128 bit Key into four blocks as per equations (01), (02), (03), and (04). Similarly, it also divides 128 bit IV into four blocks as per equations (05), (06), (07), and (08) [10]. 𝐾3 = 𝑘[0] ‖ 𝑘[1] ‖ 𝑘[2] ‖ … ‖ 𝑘[31] (1) 𝐾2 = 𝑘[32] ‖ 𝑘[33] ‖ 𝑘[34] ‖ … ‖ 𝑘[63] (2) 𝐾1 = 𝑘[64] ‖ 𝑘[65] ‖ 𝑘[66] ‖ … ‖ 𝑘[95] (3) 𝐾0 = 𝑘[96] ‖ 𝑘[97] ‖ 𝑘[98] ‖ … ‖ 𝑘[127] (4) 𝐼𝑉3 = 𝑖𝑣[0] ‖ 𝑖𝑣[1] ‖ 𝑖𝑣[2] ‖ … ‖ 𝑖𝑣[31] (5) 𝐼𝑉2 = 𝑖𝑣[32] ‖ 𝑖𝑣[33] ‖ 𝑖𝑣[34] ‖ … ‖ 𝑖𝑣[63] (6) 𝐼𝑉1 = 𝑖𝑣[64] ‖ 𝑖𝑣[65] ‖ 𝑖𝑣[66] ‖ … ‖ 𝑖𝑣[95] (7) 𝐼𝑉0 = 𝑖𝑣[96] ‖ 𝑖𝑣[97] ‖ 𝑖𝑣[98] ‖ … ‖ 𝑖𝑣[127] (8) where 𝑘[0], 𝑖𝑣[0] are LSB part and 𝑘[127], 𝑖𝑣[127] are MSB part of the key and IV respectively. Initial operations are performed on key and iv as per Table 1. The output of the initial operations block is loaded into LFSR before the first clock cycle [10]. The second module LFSR consists of sixteen stages each having parallel 32 bits. Contents of LFSR are shifted from MSB (S15) to LSB (S0) in each clock cycle. S15 receives new value from the feedback path at each clock cycle. Third module FSM consists of
  • 3.
    Int J Elec& Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 547 three parallel 32-bit update registers R1, R2, R3, two S-Boxes S1, S2 each of 4Kbytes, two 32 bit modulo adders and two 32 bit XOR gates. The final module is the feedback path which consists of functions MULα, DIVα, and many XOR operations. The two functions MULα and DIVα are implemented as lookup tables. Divide KEY and IV 128 32 32 32 32 32 K0 K1 K2 K3 IV0 IV1 IV2 IV3 Initial Operations S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 128 LFSR S5 S15 S2 S11 S0 FSM 32 32 Feedback 32 32 Key Stream 32 32 32 F v Key IV Mode 0 1 0: Initialization mode 1: Keystream mode Clk Rst1 Rst2 Figure 1. Existing SNOW 3G architectures Table 1. LFSR initialization calculations 𝑆0 = 𝐾0 ⊕ 1 𝑆4 = 𝐾0 𝑆8 = 𝐾0 ⊕ 1 𝑆12 = 𝐾0 ⊕ 𝐼𝑉1 𝑆1 = 𝐾1 ⊕ 1 𝑆5 = 𝐾1 𝑆9 = 𝐾1 ⊕ 1 ⊕ 𝐼𝑉3 𝑆13 = 𝐾1 𝑆2 = 𝐾2 ⊕ 1 𝑆6 = 𝐾2 𝑆10 = 𝐾2 ⊕ 1 ⊕ 𝐼𝑉2 𝑆14 = 𝐾2 𝑆3 = 𝐾3 ⊕ 1 𝑆7 = 𝐾3 𝑆11 = 𝐾3 ⊕ 1 𝑆15 = 𝐾3 ⊕ 𝐼𝑉0 SNOW 3G works into two modes of operation, initialization mode and keystream mode. At the start of initialization, the model system should reset LFSR and FSM using terminals Rst1 and Rst2 respectively. In the first clock cycle values calculated in the initialization, a mode is loaded into sixteen stages of LFSR but FSM registers should remain in a reset state. In the second clock cycle, Rst2=0 and now LFSR is clocked. At each clock, 32-bit output F of FSM is combined with S0, S2 & S11 in the feedback path by selecting mode 0 from a select line of the multiplexer and applied to S15 as intermediate signal v. The following equation provides the intermediate signal v in the initialization mode [10]. 𝑣 = (𝑆0,1‖𝑆0,2‖𝑆0,3‖0𝑥00) ⊕ 𝑀𝑈𝐿𝛼(𝑆0,0) ⊕ S2 ⊕ (0𝑥00‖𝑆11,0‖𝑆11,1‖𝑆11,2) ⊕ 𝐷𝐼𝑉 𝛼(𝑆11,3) ⊕ F (9) After 32 clock cycles, SNOW 3G enters into keystream mode. Operations in this mode are the same as initialization mode but the only difference is that output F of FSM is not combined in feedback path by making mode = 1 from the multiplexer. The intermediate signal in keystream mode is given by the following equation [10]. 𝑣 = (𝑆0,1‖ 𝑆0,2‖𝑆0,3‖0𝑥00) ⊕ 𝑀𝑈𝐿𝛼(𝑆0,0) ⊕ S2 ⊕ (0𝑥00‖𝑆11,0‖𝑆11,1‖𝑆11,2) ⊕ 𝐷𝐼𝑉 𝛼(𝑆11,3) (10) In keystream mode, FSM is clocked for one clock cycle and its first output is discarded when it is clocked for n clock cycles to encrypt n number of 32-bit words, where n = number of 32-bit data words is to be encrypted [10].
  • 4.
     ISSN: 2088-8708 IntJ Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 548 4. RELATED WORK The study of existing architectures of SNOW 3G evolved two challenges. One minimizing propagation delay of the 232 modulo adders and other is minimizing the chip area of S-boxes. The researcher Kitsos et al. [12] realized S-boxes using 8 lookup tables. Each lookup table consumes 1 KB memory, so memory used for S-box realization is 8 KB. Jairaj et al. used symmetry of S-box lookup tables to minimize cache requirement in the software implementation of SNOW 3G [21]. Kitsos et al. [12] used conventional CLA for modulo adder implementation. The researcher Pai and Chen [22] presented a modified CLA design to minimize the propagation delay. Traboulsi et al. [23] implemented SNOW 3G on an embedded platform. The motive of the design was to minimize the memory required for S-box implementation. Researchers used 2 lookup tables in place of 8 lookup tables for implementation of 2 S-boxes. Eight-bit shifting with cache memory is used efficiently to minimize memory requirement. 5. PRESENTED SNOW 3G ARCHITECTURE Considering the challenges of existing FSM, the proposed implementation uses the following refinements to improve the performance of the SNOW 3G algorithm. - Use of novel modulo CLA architecture over 232 to minimize propagation delay in FSM, which decides the critical delay of the algorithm - Use of novel S-Box architecture to minimize chip area 5.1. Novel modulo CLA architecture over 232 Modulo adders are usually implemented by using ripple-carry adders, but this technique increases the propagation delay of the critical path. The propagation delay of n bit ripple carries adder is (2n+1) gate delays. Modulo adder over 232 implemented by using ripple-carry adders will have delay of (2*32+1 = 65) 65 gates delay, assuming average gate delay of 10 ηs the total delay of one modulo adder will be 65*10 = 650 ηs. FSM consists of two such adders so a total delay of modulo adders for single computation will be 1300 ηs. The propagation delay of modulo adders can be minimized by using CLA for its implementation. Existing CLAs are realized by using basic gates i.e. AND, XOR, and OR gates, but Pai et al. realized CLA by using universal gates i.e. NAND or NOR gates [22]. The same design minimized gate requirement as compared to existing architectures. At the same time, this CLA [22, 24] designs are faster than conventional CLA architectures. Adder architecture [25] developed for LILI-II cipher uses different approach for addiation. Reduction in propagation delay and chip area is possible in existing architectures [12-16, 22], so the presented research work uses universal gates for CLA implementation and other techniques to minimize the number of gates required. Novel modulo CLA architecture over 232 uses following three architectures in multilevel CLA designs for performance improvement - 4 bit CLA at LSB (to calculate S0 to S3) - 4 bit CLA at middle stages (to calculate S4 to S27) - 4 bit CLA at MSB (to calculate S28 to S31) Using the above CLA architectures novel architecture for modulo CLA over 232 was designed as shown in Figure 2. Presented modulo adder architecture is an area, propagation delay, and energy-efficient as compared to existing modulo CLA architectures. Gate reduction at level 2, Stage 1 Unused logic circuit reduction Four bit LSB adder Four bit middle stage adder Four bit MSB adder Gate reduction at level 3, stage 1 FA_WC S0 G0 B0 A0 FA_NAND S1 G1 P1 B1 A1 C1 FA_NAND S2 G2 P2 B2 A2 C2 FA_NAND S3 G3 P3 B3 A3 C3 GG0 FA_NAND S4 G4 P4 B4 A4 C4 FA_NAND S5 G5 P5 B5 A5 C5 FA_NAND S6 G6 P6 B6 A6 C6 FA_NAND S7 G7 P7 B7 A7 C7 GG1 PG1 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 FA_NAND S8 G8 P8 B8 A8 C8 FA_NAND S9 G9 P9 B9 A9 C9 FA_NAND S10 G10 P10 B10 A10 C10 FA_NAND S11 G11 P11 B11 A11 C11 GG2 PG2 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 FA_NAND S12 G12P12 B12 A12 C12 FA_NAND S13 G13P13 B13 A13 C13 FA_NAND S14 G14 P14 B14 A14 C14 FA_NAND S15 G15 P15 B15 A15 C15 GG3 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 PG3 GG16 FA_NAND S16 G16P16 B16 A16 FA_NAND S17 G17P17 B17 A17 C17 FA_NAND S18 G18 P18 B18 A18 C18 FA_NAND S19 G19 P19 B19 A19 C19 GG4 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 PG4 FA_NAND S20 G20P20 B20 A20 FA_NAND S21 G21P21 B21 A21 C21 FA_NAND S22 G22 P22 B22 A22 C22 FA_NAND S23 G23 P23 B23 A23 C23 GG5 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 PG5 FA_NAND S24 G24P24 B24 A24 FA_NAND S25 G25P25 B25 A25 C25 FA_NAND S26 G26 P26 B26 A26 C26 FA_NAND S27 G27 P27 B27 A27 C27 GG6 N1 N3 N6 N13 N12 N11 N10 N14 N2 N4 N5 N8 N7 N9 PG6 C16 C20 C24 FA_NAND S28 G28 P28 B28 A28 FA_NAND S29 G29 P29 B29 A29 C29 FA_NAND S30 G30 P30 B30 A30 C30 FA_NAND_WGIPI S31 B31 A31 C31 C28 Figure 2. Novel modulo CLA architecture over 232
  • 5.
    Int J Elec& Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 549 5.2. Novel S-Box architecture Two S-boxes S1 & S2 are used in SNOW 3G architecture each requires memory of 4 KB. The lookup table of S1 is taken from the Rijndael substitution box and a lookup table of S2 is based on Dickson polynomial over GF-28. As per design specification, each S-box (S1 or S2) is implemented by using 4 lookup tables and each lookup table has 256 values each of 4 bytes. So the implementation of each lookup table requires (256x4 = 1024bytes of memory). Each S-box has 4 lookup tables, so total memory required for the implementation of S1 or S2 is (4x1024 = 4K) 4KB. The total memory needed for the realization of two S-boxes is 8KB. Existing implementation [10-16, 26-29] uses S-box architecture as shown in Figure 3. S1_T0 S1_T1 S1_T2 S1_T3 32 8 8 8 8 32 32 32 32 32 S2_T0 S2_T1 S2_T2 S2_T3 32 8 8 8 8 32 32 32 32 32 S-box S1 Implementation S-box S2 Implementation Figure 3. Existing S-boxes architecture The four lookup tables of S1 i.e. S1_T0 to S1_T3 as shown in Figure 3 has the same content but exist in 8 bit shifted form. Analogous is the case of S-box S2. Presented novel S-box architectures use a single lookup table for implementation of S-box (S1 or S2). Presented research work uses two architectures for S-box implementation. First architecture as shown in Figure 4, consumes fewer resources but useful to low-frequency applications only. Second architecture as shown in Figure 5, consumes fewer resources as compared to existing architectures but required more resources as compared to Novel S-box architecture-1. Addr1 Addr2 Addr3 Addr4 DataOut1 DataOut2 DataOut3 DataOut4 8 8 8 8 32 32 32 32 Multiport ROM 8 32 32 Bit Latch 32 32 32 32 32 Bit Latch 32 Bit Latch 32 Bit Latch 2 Bit Counter Figure 4. Novel S-Box architecture1 Presented designs require 2 KB of memory for the realization of S-boxes S1 & S2. These designs save 6 KB of memory as compared to existing designs. S-box architecture-1 saves 6 KB memory at the cost of some additional hardware (Single 2-bit counter, two 4 I/p multiplexers, and four 32 bit latches). This architecture is 4 times slower than conventional architectures and useful for low-frequency applications. S-box architecture-2 has the same speed as conventional architectures but uses 4 additional 256:1 multiplexers. The second architecture can be used for low and high-speed applications depending on cost and speed tradeoffs
  • 6.
     ISSN: 2088-8708 IntJ Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 550 LOC1 LOC0 LOC255 MUX MUX MUX Out1 for A1 Out2 for A2 Out4 for A4 Address A1 Address A2 Address A4 32 32 32 8 8 8 Figure 5. Novel S-Box architecture 2 5.3. Optimized SNOW 3G architecture Optimized SNOW 3G architecture as shown in Figure 6 is designed using novel modulo CLA architecture and novel S-Box architecture as discussed in the previous section. SNOW 3G architecture designed using S-Box architecture-1 is used for low-frequency applications and needs two clock arrangements. Whereas SNOW 3G architecture designed using S-Box architecture-2 is used for high-frequency applications and needs a single clock. Internal block diagram of optimized SNOW 3G architecture as shown in Figure 7. Divide KEY and IV 128 32 32 32 32 32 K0 K1 K2 K3 IV0 IV1 IV2 IV3 Initial Operations S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 128 LFSR S5 S15 S2 S11 S0 Feedback 32 32 Key Stream 32 32 32 F v Key IV Mode 0 1 0: Initialization mode 1: Keystream mode Clkfast Rst1 S1 and S2 Logic 2 bit Register Clkslow Other logic in FSM Rst2 FSM Figure 6. Top module of refined SNOW 3G architecture
  • 7.
    Int J Elec& Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 551 32 32 32 S0 S1 S2 S5 S14 S15 .. .. .. LFSR 32 R3 R1 S2-BOX R2 S1-BOX 32 32 32 32 32 32 32 32 32 Feedback FSM Mode 0 1 32 S11 Divide KEY and IV 128 K0 K1 K2 K3 IV0 IV1 IV2 IV3 Initial Operations S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 128 KEY IV Key Stream Out 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 DIVα >> 8 32 32 32 32 MULα << 8 32 0: Initialization mode 1: Keystream mode 0 1 F v Mod CLA Mod CLA Figure 7. Internal block diagram of optimized SNOW 3G architecture FSM of SNOW 3G architecture consists of two modulo adders and two S-Boxes. Two modulo adders will decide the speed of the algorithm and two S-boxes will decide hardware utilization of the algorithm. The use of novel modulo CLA over 232 minimizes propagation delay and the use of novel S-box architecture minimizes hardware utilization. These refinements help to improve the performance of the SNOW 3G algorithm in terms of throughput and area. Optimized SNOW 3G architecture uses VHDL language for coding. The same is implemented on the FPGA device Virtex xc5vfx100e manufactured by Xilinx [30]. The presented architecture achieved a maximum frequency of 254.9 MHz and throughput of 7.2235 Gbps. Table 2 shows particulars about the technology used. Figure 8 and Figure 9 show RTL schematic and output waveform of the presented architecture respectively. Table 2. Technology used details SNOW3GNEW Project Status (05/03/2020 - 11:34:41) Project File: SNOW3GOPT.xise Parser Errors: No Errors Module Name: SNOW3G Implementation State: Synthesized Target Device: xc5vfx100t-3ff1136  Errors: No Errors Product Version: ISE 13.2  Warnings: No Warnings Design Goal: Balanced  Routing Results: Design Strategy: Xilinx Default (unlocked)  Timing Constraints: Environment: System Settings  Final Timing Score:
  • 8.
     ISSN: 2088-8708 IntJ Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 552 Figure 8. RTL schematic Figure 9. Output waveform 6. RESULT AND DISCUSSIONS The following section discusses the result in terms of area, propagation delay, throughput, and memory utilized for presented SNOW 3G architecture. 6.1. The area 6.1.1. Novel modulo CLA architecture over 232 Presented novel modulo CLAs are used as modulo adders over 232 in Optimized SNOW 3G architecture. A comparison of device utilization of existing [13, 22] and presented architectures is shown in Figure 10.
  • 9.
    Int J Elec& Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 553 Figure 10. Comparisons of hardware utilization for CLA architectures 6.1.2. Novel S-Box architecture Optimized SNOW 3G architecture uses Novel S-box architecture to avoid redundancy of lookup tables. Presented Novel S-Box architecture-1 is suitable for low-frequency applications and Novel S-Box architecture-2 is useful for high-frequency applications. The use of these novel architectures minimizes hardware requirement as shown in the Figure 11. The comparison shows that the hardware resources used in the presented architectures are less than existing architectures [12-16]. The reduction in area is possible because S-box is designed using one lookup table in place of four lookup tables. Figure 11. Comparisons of hardware utilization for S-box 6.1.3. Optimized SNOW 3G architecture Optimized SNOW 3G architecture uses refined modulo CLA over 232 and refined S-box to for performance improvement. Hardware resources used by optimized SNOW 3G architecture are presented in Table 3 and Table 4 shows comparisons of hardware resources used by optimized SNOW 3G and existing architectures [12-16]. The comparison shows that optimized SNOW 3G architecture utilizes minimum resources as compared to architecture presented Kitsos et al. [13], Madani and anougast [15] and Madani et al. [16]. The architecture presented by Kitsos et al. [12] is ASIC, so the comparison is difficult. The architecture presented by Zhang et al. [14] uses less hardware as compared to proposed refined architecture because only one mode implemented on hardware. 94 52 55 102 57 57 103 57 55 0 20 40 60 80 100 120 4 input LUTs Occupied Slices Slices containing Related Logic Presented Novel Modulo CLA Exisisting Conventional CLA [13] Exisisting Modified CLA [22] 534 1152 2048 748 2304 4164 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Proposed Low Frequency Architecture Proposed High frequency Architecture Existing Architectures [12, 13, 14, 15, 16] No. of slices used Number of 4 input LUTs
  • 10.
     ISSN: 2088-8708 IntJ Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 554 Table 3. Device utilization summary of optimized SNOW 3G architecture Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization 1. Number of Slice Registers 870 64000 1% 2. Number of Slice LUTs 1208 64000 1% 3. Number of fully used LUT-FF pairs 680 1398 48% 4. Number of bonded IOBs 325 640 50% 5. Number of BUFG/BUFGCTRLs 10 32 31% Table 4. Comparison of hardware resources for different architectures Sr. No. Architectures Hardware resources used 1 Proposed Refined Architecture 870 Slice Registers and 1208 slice LUTs on Virtex 5 2 The architecture proposed by P. Kitsos et al. [12] ASIC implementation used 25016 equivalent gates 3 The architecture proposed by P. Kitsos et al. [13] Slices used 3559 on Spartan 3 Family 4 The architecture proposed by L. Zhang et al. [14] Only one mode implemented on hardware to increase throughput with minimum hardware resources, 356 slices on Virtex 5 5 The architecture proposed by Mahdi Madani and Camel Tanougast [15] 1020 Slice Registers and 889 Slice LUTs on Virtex5 6 The architecture proposed Mahdi Madani, Ilyas Benkhaddra et al. [16] 912 Slice Registers and 1108 Slice LUTs on Virtex 5 6.2. Propagation delay 6.2.1. Novel modulo CLA over 232 Propagation delay comparison of proposed refined CLA and existing CLA architectures [13, 22] is shown in Figure 12. Propagation delay evaluation shows that delay of presented novel modulo CLA architecture is fewer than existing CLA architectures. The presented CLA architecture will help to improve the throughput of Optimized SNOW 3G architecture. Figure 12. Delay comparisons of novel and existing CLA architectures 6.2.2. Novel S-Box architecture The combinational path delay comparisons of proposed refined S-box architectures and existing S-box architectures [12-16] are shown in the Table 5. The comparison shows that the propagation delay of proposed low-frequency architecture is more as compared to other architectures, with less hardware. Similarly, the propagation delay of proposed high-frequency architecture is less as compared to other architectures with moderate hardware utilization. The path delay of existing architectures is more as compared to presented architecture 1 but less as compared to architecture 2. The hardware resources used by existing architecture are more as compared to other architectures.
  • 11.
    Int J Elec& Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 555 Table 5. Hardware used and propagation delay comparison of S-box implementations Sr. No. S- Box architectures No. of slices used Number of 4 input LUTs Propagation delay (ns) 1 Proposed Low-Frequency Architecture 534 748 9.92 2 Proposed High-frequency Architecture 1152 2304 9.12 3 Existing Architecture 2048 4164 9.34 6.3. Throughput and memory Comparisons of throughput achieved and memory used for S-box realization of optimized SNOW 3G and existing SNOW 3G [12-16] architectures are shown in Figure 13. The comparison shows that throughput of optimized SNOW 3G is higher than architecture presented by Kitsos et al. [13], close to architecture presented by Kitsos et al. [12], but less than architecture presented by Zhang et al. [14], Madani and Tanougast [15] and Madani et al. [16]. This may be due to the use of more hardware resources. Figure 13. Comparisons throughput and memory used for the realization of S-boxes 7. CONCLUSION Optimized SNOW 3G architecture is presented in the paper uses novel modulo CLA and novel S-box architecture. The use of novel CLA minimizes hardware required for modulo adders and minimizes propagation delay as compared to existing architectures. The use of novel S-box architecture minimizes 6 K bytes of memory as compared to existing architectures. The presented architecture uses 2K bytes of memory, whereas existing architectures 8 K bytes of memory for the same. The presented SNOW architecture attained throughput of 7.2463 Gbps at a clock frequency of 226.562 MHz. Presented architecture achieves throughput more than architecture and close to ASIC implementation. The throughput of existing architectures is more than the presented architecture. It may be due to: (1) S-boxes used in these architectures use 8 KB memory for S-box realizations; (2) Architecture uses a software platform that helps to minimize hardware and to increase throughput; (3) Architecture is ASIC realization and ASIC designs are always faster than FPGA realizations. REFERENCES [1] C. Y. Yan and R. Xiao, “Study of block algorithms implement on hardware in an information security system,” in Business Management and Electronic Information (BMEI), pp. 589-593, 2011. [2] P. Leglise, et al., “Efficient Implementation of Recent Stream Ciphers on Reconfigurable Hardware Devices,” in 26th Symposium on Information Theory in the Benelux, pp. 261-268, 2005. [3] B. Prathiba, et al., “FPGA Implementation of Smart Cryptography Algorithm,” in International Journal of Recent Technology and Engineering (IJRTE), vol. 8, no. 5, pp. 3017-3020, 2020. [4] B. Wang and L. Liu, “A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing,” in IEEE International Symposium on Circuits and Systems, vol. 14, pp. 1182-1185, 2015. [5] Y. Chen, et al., “Research and Implementation of Reconfigurable Architectures of DES and ZUC,” in Second Advanced Information Technology, Electronic and Automation Control Conference (IAEAC), vol. 7, no. 1, pp. 216-220, 2017.
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     ISSN: 2088-8708 IntJ Elec & Comp Eng, Vol. 11, No. 1, February 2021 : 545 - 557 556 [6] N. B. Hulle, et al., “Compact Reconfigurable Architecture for Sosemanuk Stream Cipher,” in International Journal of Engineering and Advanced Technology (IJEAT), vol. 9, no. 3, pp. 607-611, 2020. [7] A. Khalid, et al., “RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1072-1084, 2017. [8] G. Paul and A. Chattopadhyay, “Three Snakes in One Hole : A 67 Gbps Flexible Hardware for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes,” in IACR Cryptology ePrint Archive, pp. 1-19, 2013. [9] M. Galanis, et al., “Comparison of the Hardware Implementation of Stream Ciphers,” The International Arab Journal of Information Technology, vol. 2, no. 4, pp. 267-274, 2005. [10] “Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2 & UIA2, Document 2: SNOW 3G specification,” ETSI/SAGE Specification, Version 1.1, 2006. [11] “Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2 & UIA2, Document 3: Implementor’s Test Data,” ETSI/SAGE Specification, Version 1.1, 2012. [12] P. Kitsos, et al., “High-Performance ASIC Implementation of the SNOW 3G Stream Cipher,” in IFIP/IEEE VLSI- SOC 2008 - International Conference on Very Large Scale Integration (VLSI SOC), Rhodes Island, Greece, pp. 1-4, 2008. [13] P. Kitsos, et al., “FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0,” Microprocessors and Microsystems, vol. 37, no. 2, pp. 235-245, 2013. [14] L. Zhang, et al., “Evaluating the Optimized Implementations of SNOW 3G and ZUC on FPGA,” in Trust, Security and Privacy in Computing and Communications (TrustCom), pp. 436-442, 2012. [15] M. Madani and C. Tanougast, “Combined and Robust SNOW-ZUC Algorithm Based on Chaotic System,” in 2018 International Conference on Cyber Security and Protection of Digital Services, Cyber Security, pp. 1-7, 2018. [16] M. Madani, et al., “Digital Implementation of an Improved LTE Stream Cipher Snow-3G Based on Hyperchaotic PRNG,” Security and Communication Networks, vol. 2017, no. 2, pp. 1-15, 2017. [17] R. D. Kharadkar and N. B. Hulle, “FPGA Implementation of Modulo (231 -1) Adder,” in 7th International Conference on Emerging Trends in Engineering & Technology, Kobe, Japan, pp. 85 -90, 2015. [18] P. Ekdahl and T. Johansson, “SNOW - a new stream cipher,” in RST open Nessie workshop, Heverlee, Belgium, pp. 1-17, 2001. [19] P. Hawkes and G. G. Rose, “Guess-and-Determine Attacks on SNOW,” in SAC 2002 Revised Papers from the 9th Annual International Workshop on Selected Areas in Cryptography, pp. 37-46, 2002. [20] P. Ekdahl and T. Johansson, “A New Version of the Stream Cipher SNOW,” in International Workshop on Selected Areas in Cryptography, pp. 47-61, 2002. [21] V. Jairaj, et al., “High Performance Implementation of Snow3G Algorithm in Memory Limited Environments,” in New Technologies, Mobility, and Security (NTMS), no. 5, pp. 1-4, 2011. [22] Y. Pai and Y. Chen, “The Fastest Carry Lookahead Adder,” in Second IEEE International Workshop on Electronic Design, Test and Applications, no. 1, pp. 4-6, 2004. [23] S. Traboulsi, et al., “An Optimized Parallel and Energy-Efficient Implementation of SNOW 3G for LTE Mobile Devices,” in International Conference on Communication Technology (ICCT), pp. 535-538, 2010. [24] N. B. Hulle, et al., “The Novel Architecture for Carry Lookahead Adder,” Technical Journal of The Institution of Engineers (India), Pune Local Centre, vol. 36, no. 1, pp. 84-88, 2012. [25] N. B. Hulle, et al., “High Performance Architecture for LILI-II Stream Cipher,” in International Journal of Computer Applications, vol. 107, no. 13, pp. 10-13, 2014. [26] G. Orhanou, et al., “SNOW 3G Stream Cipher Operation and Complexity Study,” Contemporary Engineering Sciences, vol. 3, no. 3, pp. 97-111, 2010. [27] S. Hessel, et al., “Implementation and Benchmarking of Hardware Accelerators for Ciphering in LTE Terminals,” in Global Telecommunications Conference, pp. 1-7, 2009. [28] N. P. Maity and R. Maity, “Design and Modelling of Paralleled RAM Architecture,” in International Conference on Future Information Technology, vol. 13, pp. 98-102, 2011. [29] A. Bikos and N. Sklavos, “Architecture Design of an Area Efficient High-Speed Crypto Processor for 4G LTE,” IEEE Transactions on Dependable and Secure Computing, vol. 15, no. 5, pp. 729-741, 2018. [30] xilinx.com, “XUPV5-LX110T,” 2015. [Online], Available: http://www.xilinx.com/univ/xupv5-lx110t.htm. BIOGRAPHIES OF AUTHORS Dr. N. B. Hulle is an Associate Professor at G H Raisoni Institute of Engineering and Technology, Pune, Maharashtra, India. He completed his Bachelor's and Masters from Dr. Babasaheb Ambedkar Marathwada University, Aurangabad, Maharashtra, India, and Ph.D. from Rashtrasant Tukadoji Maharaj Nagpur University, Nagpur, Maharashtra, India. He has 21 years of teaching experience. He guides UG and PG students. His area of research is VLSI, cryptography & Wireless Network Security. He published papers in National & International Journals and conferences. Dr. N. B. Hulle is a life member of ISTE and IETE.
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    Int J Elec& Comp Eng ISSN: 2088-8708  Optimized architecture for SNOW 3G (N. B. Hulle) 557 B. Prathiba is an Assistant Professor at G H Raisoni Institute of Engineering and Technology, Pune, Maharashtra, India. She has published articles in various international publications in the area of Wireless Sensor Networks. Her interested areas are Wireless Sensor Networks, Microcontrollers, and VLSI. B. Prathiba is a life member of ISTE and IETE. Sarika R. Khope is an Assistant Professor at G H Raisoni Institute of Engineering and Technology, Pune, Maharashtra, India. She has published the articles in various international publications in the area of Image steganography, Image Fusion, and VLSI Her interested areas are Digital Systems Design, Machine Learning, and VLSI. Sarika Khope is a life member of ISTE. Dr. K. Anuradha is a Professor and Dean ICT at Gokaraju Rangaraju Institute of Engineering & Technology, Hyderabad, Telangana, India. She is specialized in the areas of Data mining, Image Processing, Machine Learning, Network Security and Computer Networks. Yogini Borole is an Assistant Professor at G H Raisoni Institute of Engineering and Technology, Pune, Maharashtra, India. She has published the articles in various international publications in the area of DSP and VLSI. Her interested areas are Digital Signal Processing, Power Electronics, and VLSI. Yogini Borole is a life member of ISTE and IETE. Dr. D. Kotambkar is an Assistant Professor at Shri Ramdeobaba College of Engineering and Management, Nagpur, Maharashtra, India. She has published the articles in various international publications in the area of MIMO Wireless Communication.Her interested areas are Digital Signal Processing and Wireless Communication..She is a life member of IETE.