This chapter you will be understand how it work

1. Chapter 4
Microprocessor
interfacing

2. Programmable Interrupt
Controller (PIC)
A PIC is an integrated circuit
that helps a microprocessor
handle interrupt requests (IRQs)
coming from multiple different
sources. When an interrupt
request comes in, the PIC
assesses the IRQs’ relative
priorities and informs the CPU to
switch execution to the most
appropriate interrupt handler.
The PIC has a set of registers:
interrupt request register (IRR),
in-service register (ISR), and
interrupt mask register (IMR).
The IRR specifies which
interrupts are pending
acknowledgement, the ISR register
specifies which interrupts have
been acknowledged but are still

3. Data Bus
A data bus is a system within a
computer or device, consisting of a
connector or set of wires, that
provides transportation for data The
data bus can transfer data to and from
the memory of a computer, or into or
out of the central processing unit
(CPU). The speed at which information
is exchanged between components is
regulated by a bus controller
Information coming from the CPU will
always travel at a much higher speed
than data coming from other
components. However, in a computer,
everything must travel at the same
speed, and bus controllers serve this
purpose

4. Buffer
In computer science, a buffer is
temporary storage used when one
component feeds data to the other, but
their speeds aren’t the same. For
example, data transfers between a fast
CPU and a slow external device are
impossible without a buffer in between
them. The buffer acts as intermediate
storage. The producer places the
generated data items into the buffer.
The consumer takes the items one at a
time at a speed it can process them.
If its processing is slower than data
generation, they’ll wait for the
consumer to pick them. Meanwhile, the
producer will keep putting the data
into the buffer, so no items will be
lost

5. Direct Memory Access (DMA)
is a technique that allows I/O devices to directly access memory with
minimal involvement from the processor. This is facilitated by a
hardware device known as a DMA Controller.
Here’s a more detailed:
• DMA Controller
• Types of DMA
• Working of DMA Controller

6. DMA Controller
This is a control unit that works as
an interface for the data bus and the
I/O Devices1. It transfers data
between I/O devices and main memory
with very little interaction with the
processor1. The DMA Controller also
contains an address unit, which
generates the address and selects an
I/O device for the transfer of data1.

7. Types of DMA
There are four popular types of DMA:
• Single-Ended DMA: Single-Ended DMA Controllers operate by reading and
writing from a single memory address. They are the simplest DMA
• Dual-Ended DMA: Dual-Ended DMA controllers can read and write from
two memory addresses. Dual-ended DMA is more advanced than single-
ended DMA.
• Arbitrated-Ended DMA: Arbitrated-Ended DMA works by reading and
writing to several memory addresses. It is more advanced than Dual-
Ended DMA.
• Interleaved DMA: Interleaved DMA are those DMA that read from one
memory address and write from another memory address.
The type of DMA used depends on the specific requirements of the data
transfer, such as the number of memory addresses involved and the
complexity of the operation

8. The DMA controller registers have three registers as
follows.
Address register – It contains the address to specify the desired
location in memory.
Word count register – It contains the number of words to be
transferred.
Control register – It specifies the transfer mode.
Note: All registers in the DMA appear to the CPU as I/O interface
registers. Therefore, the CPU can both read and write into the DMA
registers under program control via the data bus.
The figure below shows the block diagram of the DMA controller. The
unit communicates with the CPU through the data bus and control lines.
Through the use of the address bus and allowing the DMA and RS register
to select inputs, the register within the DMA is chosen by the CPU. RD
and WR are two-way inputs. When BG (bus grant) input is 0, the CPU can

9. Explanation: The CPU initializes
the DMA by sending the given
information through the data bus.
• The starting address of the memory block
where the data is available (to read) or where
data are to be stored (to write).
• It also sends word count which is the number
of words in the memory block to be read or
written.
• Control to define the mode of transfer such
as read or write.
• A control to begin the DMA transfer

10. Modes of Data Transfer in DMA
There are 3 modes of data transfer in DMA that
are described below.
Burst Mode: In Burst Mode, buses are handed over to the CPU by
the DMA if the whole data is completely transferred, not before
that.
Cycle Stealing Mode: In Cycle Stealing Mode, buses are handed
over to the CPU by the DMA after the transfer of each byte.
Continuous request for bus control is generated by this Data
Transfer Mode. It works more easily for higher-priority tasks.
Transparent Mode: Transparent Mode in DMA does not require any
bus in the transfer of the data as it works when the CPU is
executing the transaction.

11. Programmable peripheral
interface 8255
PPI 8255 is a general purpose
programmable I/O device designed to
interface the CPU with its outside
world such as ADC, DAC, keyboard
etc. We can program it according to
the given condition. It can be used
with almost any microprocessor. It
consists of three 8-bit
bidirectional I/O ports i.e. PORT
A, PORT B and PORT C. We can assign
different ports as input or output
functions.

12. It consists of 40 pins and operates in +5V regulated power supply. Port
C is further divided into two 4-bit ports i.e. port C lower and port C
upper and port C can work in either BSR (bit set rest) mode or in mode
0 of input-output mode of 8255. Port B can work in either mode 0 or in
mode 1 of input-output mode. Port A can work either in mode 0, mode 1
or mode 2 of input-output mode. It has two control groups, control
group A and control group B. Control group A consist of port A and port
C upper. Control group B consists of port C lower and port B. Depending
upon the value if CS’, A1 and A0 we can select different ports in
different modes as input-output function or BSR. This is done by
writing a suitable word in control register (control word D0-D7)
CS A1 A0 Selection Address
0 0 0 PORT A 80 H
0 0 1 PORT B 81 H
0 1 0 PORT C 82 H
0 1 1 Control Register 83 H
1 X X No Seletion X

13. PA0 – PA7 – Pins of port A
PB0 – PB7 – Pins of port B
PC0 – PC7 – Pins of port C
D0 – D7 – Data pins for the
transfer of data
RESET – Reset input
RD’ – Read input
WR’ – Write input
CS’ – Chip select
A1 and A0 – Address pins

14. 8254 programmable
interval timer
8254 is a device designed to
solve the timing control
problems in a microprocessor. It
has 3 independent counters, each
capable of handling clock inputs
up to 10 MHz, and size of each
counter is 16 bit. It operates
in +5V regulated power supply
and has 24 pin signals. All
modes are software programmable.
The 8254 is an advanced version
of 8253 which did not offered
the feature of read back
command.

15. It has 3 counters each with two inputs (Clock and Gate)
and one output. Gate is used to enable or disable
counting. When any value of count is loaded and value of
gate is set(1), after every step value of count is
decremented by 1 until it becomes zero.
Depending upon the value of CS, A1, and A0 we can
determine the addresses of the selected counter.
CS A1 A0
SELECTION
0 0 0
C0
0 0 1
C1
0 1 0
C2
0 1 1

16. Applications :
• To generate an accurate
time delay
• As an event counter
• Square wave generator
• Rate generator
• Digital one shot

17. Multiple purpose programmable devices
are typically referred to as Programmable Logic Devices (PLDs). They
are electronic components that can be configured to perform a specific
logic function by the user. Unlike fixed logic devices that have
predefined functions, such as logic gates or flip-flops, PLDs can be
programmed and reprogrammed to implement different logic circuits.
PLDs are widely used in digital systems design, as they offer
flexibility, speed, and cost-effectiveness1. They contain an array of
logic elements and interconnections that can be programmed by the user
to implement a desired logic function1. The logic elements are usually
simple combinational or sequential circuits, such as AND, OR, NOT, and
XOR gates, or registers1

18. There are different types of programmable logic devices,
depending on their complexity, architecture, and
programmability1. Some of the common types are:
• Simple Programmable Logic Devices (SPLDs
• Complex Programmable Logic Devices (CPLDs):
• Field-Programmable Gate Arrays (FPGAs):
The programming of a PLD can be done using a hardware description language (HDL), such as
Verilog or VHDL, or a graphical user interface (GUI) software tool. The programming code or file
is then downloaded to the PLD using a special device programmer or a standard interface, such
as JTAG or USB. The programming code or file determines how the logic elements and
interconnections are configured to perform the desired logic function

19. Simple Programmable Logic
Devices (SPLDs)
These are the simplest and smallest PLDs
that contain a few logic elements and
interconnections. They are usually
programmed using fuse or anti-fuse
technology, which means that once
programmed, they cannot be changed1. Some
examples of SPLDs are Programmable Read-
Only Memory (PROM), Programmable Logic
Array (PLA), and Programmable Array Logic
(PAL).

20. Complex Programmable Logic
Devices (CPLDs)
CPLDs are essentially multiple PLDs in one
chip, connected by a programmable
interconnect3. This arrangement allows
complex digital circuits to be implemented in a
single chip.

21. Field-Programmable Gate
Arrays (FPGAs)
These are more complex PLDs that offer a
higher level of programmability and flexibility.

22. The programming of a PLD can be done using a
hardware description language (HDL), such as
Verilog or VHDL, or a graphical user interface (GUI)
software tool1. The programming code or file is then
downloaded to the PLD using a special device
programmer or a standard interface, such as JTAG
or USB1. The programming code or file determines
how the logic elements and interconnections are
configured to perform the desired logic function

23. A programmable keyboard is a type of
keyboard that allows you to assign custom actions
to specific keys12. This feature is particularly useful
for tasks that require repetitive key presses, such as
gaming or certain professional tasks. Some popular
programmable keyboards include the Das Keyboard
X50Q, X-keys Programmable Keypads and
Keyboards, and the Koolertron Single-Handed
Programmable Mechanical Keyboard.
Programmable keyboards can be fully-
programmable, meaning you can reprogram any key
on the keyboard, or they can add extra keys to the
keyboard for programming macros. They are
popular with gamers who use high-powered macros
and require extra keys to trigger them, but
programmable keyboards are also powerful
productivity tools at home or in the office.

24. programmable display devices
these are typically seen in gaming keyboards
that have LCD screens. These screens can
display useful information such as in-game
stats, system performance metrics, or even
custom messages3.
In a broader context, programmable display
devices can also refer to programmable
peripheral interfaces like the 8255, which is a
general-purpose programmable I/O device
designed to interface the CPU with its outside
world such as ADC, DAC, keyboard etc4.
Overall, programmable keyboard/display
devices offer a high level of customization and
can significantly enhance productivity and user
experience.