Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.
MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers  <ul><li>Source: Freescale Semiconductor </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module provides an overview of MCF5223x Ethernet Microcon...
Features   <ul><li>10/100 Fast Ethernet Controller with Ethernet PHY.  </li></ul><ul><li>Optional cryptographic accelerati...
Integration <ul><li>Up to 32 KB SRAM. </li></ul><ul><li>Up to 256 KB flash: 100 KB W/E cycles, 10 years data retention. </...
Target Applications  <ul><li>Medical instrumentation and monitors.  </li></ul><ul><li>Remote data collection.  </li></ul><...
Comparison of Different MCF5223X Families
MCF5223x Family Block Diagram
Version 2 ColdFire CPU core <ul><li>Implements instruction set architecture A+ (ISA_A+) </li></ul><ul><li>Background debug...
Enhanced Multiply-Accumulate Unit (EMAC) <ul><li>High-performance solution for maximum signal processing bandwidth. </li><...
Multiply-Accumulate Unit <ul><li>Features: </li></ul><ul><li>Integrated into the Operand Execution Pipeline </li></ul><ul>...
Cryptographic Acceleration Unit (CAU) <ul><li>Dedicated, instruction-level coprocessor for DES, 3DES, AES, MD5 and SHA-1 p...
Random Number Generator Accelerator (RNGA) <ul><li>The RNGA module is a digital integrated circuit capable of generating 3...
Real-Time Clock <ul><li>The RTC module includes the following features: </li></ul><ul><ul><li>Full clock — days, hours, mi...
Reset Controller Module <ul><li>Seven sources of reset: </li></ul><ul><ul><li>External reset input. </li></ul></ul><ul><ul...
Low Power Modes <ul><li>Run   Mode: </li></ul><ul><li>Run   mode   is   the   normal   system   operating   mode. </li></u...
SRAM <ul><li>RAM uses two single port arrays and a two-way banked access scheme. </li></ul><ul><li>Creates a second port t...
Chip Configuration Module (CCM) <ul><li>The CCM selects the following: </li></ul><ul><ul><li>External clock or phase-lock ...
ColdFire Flash Module (CFM) <ul><li>The flash module itself can be up to 512 Kbytes of Flash memory. </li></ul><ul><li>Con...
EzPORT <ul><li>Serial Interface that is compatible with a subset of the SPI format. </li></ul><ul><li>Reset the MCU, allow...
FlexBus – System Bus Controller <ul><li>Independent, user-programmable chip-select signals that can interface with SRAM, P...
Direct Memory Access <ul><li>Up to four fully independent DMA channels. </li></ul><ul><li>Single and dual address transfer...
System Integration Module <ul><li>Glueless bus interface with chip selects. </li></ul><ul><li>8-, 16- & 32-bit support for...
Standard Peripheral Block: UART <ul><li>Full-duplex, asynchronous serial port </li></ul><ul><li>Quadruple-buffered receive...
Ethernet Physical Transceiver (EPHY) <ul><li>Full-/half-duplex support in all modes </li></ul><ul><li>Supports Medium-inde...
Fast Ethernet Controller (FEC) <ul><li>IEEE® 802.3-compliant 10/100 Mbps Ethernet MAC. </li></ul><ul><li>Standard medium i...
I 2 C Module <ul><li>Compatibility with I 2 C bus standard. </li></ul><ul><li>Interface for EEPROMs, LCD controllers, ADC,...
Queued Serial Peripheral Interface (QSPI) <ul><li>Full-duplex, synchronous serial port. </li></ul><ul><li>Dedicated, 16-en...
JTAG <ul><li>JTAG pins: </li></ul><ul><ul><li>TDI: test data input. </li></ul></ul><ul><ul><li>TDO: test data output. </li...
Additional Resource <ul><li>For ordering the MCF5223X, please click the part list or </li></ul><ul><li>Call our sales hotl...
Upcoming SlideShare
Loading in …5
×

MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers

1,304 views

Published on

Overview of MCF5223x Ethernet Microcontrollers

Published in: Technology, Business
  • Be the first to comment

MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers

  1. 1. MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers <ul><li>Source: Freescale Semiconductor </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module provides an overview of MCF5223x Ethernet Microcontrollers. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Feature Overview </li></ul></ul><ul><ul><li>Target applications </li></ul></ul><ul><ul><li>Comparison of different Family </li></ul></ul><ul><ul><li>Key features </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>29 pages </li></ul></ul>
  3. 3. Features <ul><li>10/100 Fast Ethernet Controller with Ethernet PHY. </li></ul><ul><li>Optional cryptographic acceleration unit (CAU) and random number generator. </li></ul><ul><li>Up to 57 Dhrystone 2.1 MIPS @ 60 MHz. </li></ul><ul><li>Enhanced MAC module and hardware divide. </li></ul><ul><li>32K bytes SRAM; Up to 256K bytes flash 100K W/E cycles, 10 years data retention. </li></ul><ul><li>Optional controller area network (CAN) 2.0B controller 4 ch. 32-bit timers with DMA support; 4 ch. 16-bit. capture/compare/PWM timers; 2 ch. periodic interrupt timer; 8/4 ch. 8/16-bit PWM timer. </li></ul><ul><li>Up to 73 general-purpose I/O. </li></ul><ul><li>System integration (PLL, SW Watchdog). </li></ul><ul><li>Single 3.3V supply. </li></ul><ul><li>Real-time clock. </li></ul>
  4. 4. Integration <ul><li>Up to 32 KB SRAM. </li></ul><ul><li>Up to 256 KB flash: 100 KB W/E cycles, 10 years data retention. </li></ul><ul><li>10/100 Fast Ethernet controller (FEC) with PHY. </li></ul><ul><li>Ethernet media access controller (EMAC) module. </li></ul><ul><li>Cryptographic accelerator unit with random number generator. </li></ul><ul><li>CAN 2.0B controller </li></ul><ul><li>Three UARTs. </li></ul><ul><li>Queued serial peripheral interface (QSPI). </li></ul><ul><li>Inter-integrated circuit (I 2 C) bus interface. </li></ul><ul><li>Four 32-bit timer channels with </li></ul><ul><li>DMA capability. </li></ul><ul><li>4-channel, 16-bit timer for capture, compare and pulse width modulation (PWM). </li></ul><ul><li>2-channel periodic interrupt timer. </li></ul><ul><li>4-channel, 16-bit or 8-channel, 8-bit PWM generator. </li></ul><ul><li>Two 4-channel, 12-bit analog-to-digital converters (ADCs). </li></ul><ul><li>4-channel DMA controller. </li></ul><ul><li>Up to 73 general-purpose I/Os. </li></ul><ul><li>System integration (PLL, SW watchdog). </li></ul><ul><li>Single 3.3-volt supply. </li></ul>
  5. 5. Target Applications <ul><li>Medical instrumentation and monitors. </li></ul><ul><li>Remote data collection. </li></ul><ul><li>Power-over-Ethernet. </li></ul><ul><li>ZigBee control nodes. </li></ul><ul><li>Security/access control panels. </li></ul><ul><li>Health care pumps and monitors. </li></ul><ul><li>Lighting control nodes. </li></ul><ul><li>Home/industrial automation. </li></ul>
  6. 6. Comparison of Different MCF5223X Families
  7. 7. MCF5223x Family Block Diagram
  8. 8. Version 2 ColdFire CPU core <ul><li>Implements instruction set architecture A+ (ISA_A+) </li></ul><ul><li>Background debug mode with real-time trace capability </li></ul><ul><li>Hardware divider is standard </li></ul><ul><li>DSP support MAC or EMAC block </li></ul><ul><li>Two-stage instruction fetch pipeline </li></ul><ul><ul><li>Instruction address generation </li></ul></ul><ul><ul><li>Instruction fetch </li></ul></ul><ul><li>Three-longword entry instruction buffer decouples IFP/OEP </li></ul><ul><li>Two-stage operand execution pipeline </li></ul><ul><ul><li>Decode and select/operand cycle </li></ul></ul><ul><ul><li>Address generation execute cycle </li></ul></ul>
  9. 9. Enhanced Multiply-Accumulate Unit (EMAC) <ul><li>High-performance solution for maximum signal processing bandwidth. </li></ul><ul><li>Executes both 16 x 16 and 32 x 32 products with 48-bit accumulation in 1 clock cycle. </li></ul><ul><li>Speeds up regular ColdFire MULS and MULU instructions. </li></ul><ul><li>Uses operands in any two data registers and 10 dedicated registers. </li></ul><ul><ul><li>Four 32-bit accumulators (ACCx) with 16-bit extensions (ACCEXTx) hold the accumulated results </li></ul></ul><ul><ul><li>MASK constrains addresses for circular queues </li></ul></ul><ul><ul><li>Overflow/saturation, signed/unsigned, fractional/integer and round/truncate math governed by MACSR[7:4] </li></ul></ul><ul><ul><li>Dedicated N, Z, V, EV condition code bits reside in MACSR[3:0] </li></ul></ul><ul><ul><li>Per accumulator overflows reported by MACSR[11:8] </li></ul></ul>
  10. 10. Multiply-Accumulate Unit <ul><li>Features: </li></ul><ul><li>Integrated into the Operand Execution Pipeline </li></ul><ul><li>Implements a 3 stage arithmetic pipeline optimized for 16x16 multiplies </li></ul><ul><li>Provides hardware support for a limited number of DSP operations used in embedded code </li></ul><ul><li>Functionality: </li></ul><ul><li>Functionality is provided in three related areas: </li></ul><ul><li>Signed and Unsigned Integer Multiplies </li></ul><ul><li>Multiply-accumulate operation supporting: </li></ul><ul><ul><li>16x16 [un]signed Multiply-accumulate in 1 Clk Cycle </li></ul></ul><ul><ul><li>32 x32 [un]signed Multiply-accumulate in 3 Clk Cycles </li></ul></ul><ul><ul><li>Also supports signed fixed point fractional operands </li></ul></ul><ul><ul><li>Product may be Shifted once right or left prior to Accumulation </li></ul></ul><ul><li>Register-based Arithmetic operations </li></ul>
  11. 11. Cryptographic Acceleration Unit (CAU) <ul><li>Dedicated, instruction-level coprocessor for DES, 3DES, AES, MD5 and SHA-1 primitives. </li></ul><ul><li>Requires no new instructions; register file accessed with existing coprocessor load(cp0ld.l) and store (cp0st.l) opcodes. </li></ul><ul><li>Gate count is reduced by a factor of 6.5 over slave bus MDHA and SKHA blocks used previously. </li></ul><ul><li>Achieves performance better than wire line on symmetric key algorithms and near or better than wire line on hashing functions. </li></ul><ul><li>Flexible design can accommodate future needs for new algorithms. </li></ul><ul><li>Random number generator still resides off platform. </li></ul>
  12. 12. Random Number Generator Accelerator (RNGA) <ul><li>The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers. </li></ul><ul><li>The random bits are generated by clocking shift registers with clocks derived from ring Oscillators. </li></ul><ul><li>The oscillators with their unknown frequencies provide the required entropy needed to create random data. </li></ul><ul><li>The RNGA has two primary modes of operation, Normal Mode and Sleep Mode. </li></ul><ul><li>These are entered by setting the appropriate bits in the RNGA Control Register. </li></ul>
  13. 13. Real-Time Clock <ul><li>The RTC module includes the following features: </li></ul><ul><ul><li>Full clock — days, hours, minutes, seconds </li></ul></ul><ul><ul><li>Minute countdown timer with interrupt </li></ul></ul><ul><ul><li>Programmable daily alarm with interrupt </li></ul></ul><ul><ul><li>Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts </li></ul></ul>
  14. 14. Reset Controller Module <ul><li>Seven sources of reset: </li></ul><ul><ul><li>External reset input. </li></ul></ul><ul><ul><li>Power-on reset (POR). </li></ul></ul><ul><ul><li>Phase locked-loop (PLL) loss of lock. </li></ul></ul><ul><ul><li>PLL loss of clock. </li></ul></ul><ul><ul><li>Software. </li></ul></ul><ul><ul><li>Low-voltage detector (LVD). </li></ul></ul><ul><ul><li>JTAG CLAMP, HIGHZ and EXTEST instructions. </li></ul></ul><ul><li>Software-assertable RSTO pin independent of chip reset state. </li></ul><ul><li>Software-readable status flags indicating the cause of the last reset. </li></ul><ul><li>LVD control and status bits for setup and use of LVD reset or interrupt. </li></ul>
  15. 15. Low Power Modes <ul><li>Run Mode: </li></ul><ul><li>Run mode is the normal system operating mode. </li></ul><ul><li>Current consumption in this mode is related directly to the system clock frequency. </li></ul><ul><li>Wait Mode: </li></ul><ul><li>Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is detected. </li></ul><ul><li>Peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU to exit from wait mode. </li></ul><ul><li>Doze Mode: </li></ul><ul><li>Each peripheral defines individual operational characteristics in doze mode. </li></ul><ul><li>Peripherals which continue to run and have the capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode. </li></ul><ul><li>Stop Mode: </li></ul><ul><li>All clocks to the system are stopped and the peripherals cease operation. </li></ul><ul><li>When exiting stop mode, most peripherals retain their pre-stop status and resume operation. </li></ul>
  16. 16. SRAM <ul><li>RAM uses two single port arrays and a two-way banked access scheme. </li></ul><ul><li>Creates a second port to the RAM memory. </li></ul><ul><li>Manages the dual port memory resource. </li></ul><ul><li>The SRAM is dual-ported to provide access for the DMA or other on-chip masters. </li></ul><ul><li>The SRAM is partitioned into two physical memory arrays to allow simultaneous access to both arrays by the processor core and another bus master. </li></ul>
  17. 17. Chip Configuration Module (CCM) <ul><li>The CCM selects the following: </li></ul><ul><ul><li>External clock or phase-lock loop (PLL) mode with internal or external reference. </li></ul></ul><ul><ul><li>Output pad drive strength. </li></ul></ul><ul><ul><li>Low-power configuration. </li></ul></ul><ul><ul><li>Processor status (PSTAT) and processor debug data (DDATA) functions. </li></ul></ul><ul><ul><li>BDM or JTAG mode. </li></ul></ul><ul><li>Three functions are defined: </li></ul><ul><ul><li>Reset configuration </li></ul></ul><ul><ul><li>Output pad strength configuration </li></ul></ul><ul><ul><li>Clock mode selections </li></ul></ul>
  18. 18. ColdFire Flash Module (CFM) <ul><li>The flash module itself can be up to 512 Kbytes of Flash memory. </li></ul><ul><li>Concurrent erase or blank verify of all flash array blocks. </li></ul><ul><li>Supports up to 80 MHz flash array read operations with 2-1-1-1 burst accesses. </li></ul><ul><li>Single power supply (Vdd, 3.3V) used for all module operations. No need for separate programming voltage. </li></ul><ul><li>Automated program and erase operation. </li></ul><ul><li>Read-while-write capability on some devices. </li></ul><ul><li>100,000 W/E cycles at room temperature and 10 years data retention. </li></ul><ul><li>Optional interrupt on command completion. </li></ul><ul><li>Protection scheme to prevent accidental program or erase. </li></ul><ul><li>Access restriction control for supervisor/user and data/program space operations. </li></ul><ul><li>Security for single-chip operations. </li></ul><ul><li>Auto sense amplifier timeout for low-power, low-frequency read operations. </li></ul>
  19. 19. EzPORT <ul><li>Serial Interface that is compatible with a subset of the SPI format. </li></ul><ul><li>Reset the MCU, allowing to boot from the Flash memory after the memory has been Configured. </li></ul><ul><li>Two modes of operation: </li></ul><ul><ul><li>Enabled mode : preventing access flash memory from other cores or peripherals. </li></ul></ul><ul><ul><li>Disabled mode : the rest of the MCU can access Flash memory as normal . </li></ul></ul>
  20. 20. FlexBus – System Bus Controller <ul><li>Independent, user-programmable chip-select signals that can interface with SRAM, PROM, EPROM, EEPROM, Flash, or other peripherals. </li></ul><ul><li>8-, 16-, and 32-bit port sizes. </li></ul><ul><li>Byte, word, longword, and line size transfers. </li></ul><ul><li>Programmable burst/burst-inhibited transfers selectable for each chip select and transfer direction. </li></ul><ul><li>Internal and external termination of bus cycles. </li></ul><ul><ul><li>Up to 63 wait states used for auto-acknowledge cycles. </li></ul></ul><ul><li>New secondary wait state counter added for burst cycles. </li></ul><ul><li>Programmable address setup and hold time. </li></ul>
  21. 21. Direct Memory Access <ul><li>Up to four fully independent DMA channels. </li></ul><ul><li>Single and dual address transfer operation. </li></ul><ul><li>Data transfer of 8, 16, 32 or 128-bit block w/ bursting capability. </li></ul><ul><li>Auto-alignment capable on source or destination transfers. </li></ul><ul><li>DMA transfer operation can be initiated internally or externally. </li></ul><ul><li>Channel arbitration on transfer boundaries. </li></ul><ul><li>16-bit or 24-bit byte count register (device implementation dependent). </li></ul><ul><li>Two address pointers, source and destination. </li></ul><ul><li>Supports memory to memory, peripheral to memory, and memory to peripheral transfers. </li></ul><ul><li>Independent transfer widths for source and destination. </li></ul><ul><li>Source and destination pointer may be programmed to increment after transfer or not. </li></ul><ul><li>Continuous-mode or cycle-steal transfers. </li></ul>
  22. 22. System Integration Module <ul><li>Glueless bus interface with chip selects. </li></ul><ul><li>8-, 16- & 32-bit support for DRAM, SRAM, ROM, FLASH & I/O devices. </li></ul><ul><li>8 chip-select signals, 2 that are programmable with base address registers, 6 at an offset of one base register. </li></ul><ul><li>Programmable wait states & port sizes. </li></ul><ul><li>IEEE 1149.1 test (JTAG) compliant. </li></ul><ul><li>16-bit general purpose I/O interface. </li></ul><ul><li>Programmable interrupt controller </li></ul><ul><ul><li>Low interrupt latency. </li></ul></ul><ul><ul><li>4 external interrupt request inputs. </li></ul></ul><ul><ul><li>Programmable auto vector generator. </li></ul></ul>
  23. 23. Standard Peripheral Block: UART <ul><li>Full-duplex, asynchronous serial port </li></ul><ul><li>Quadruple-buffered receiver; double-buffered transmitter </li></ul><ul><li>Independently programmable receiver and transmitter clock sources </li></ul><ul><li>Data is 5-8 bits plus odd, even, no parity, or force parity and 1, 1½ or 2 stop bits </li></ul><ul><li>Automatic wake-up mode for multi-drop applications </li></ul><ul><li>Four maskable interrupt conditions </li></ul><ul><li>Transmit and receive DMA service capability </li></ul>
  24. 24. Ethernet Physical Transceiver (EPHY) <ul><li>Full-/half-duplex support in all modes </li></ul><ul><li>Supports Medium-independent interface (MII) </li></ul><ul><li>Supports auto-negotiation </li></ul><ul><li>Auto-negotiation next page ability </li></ul><ul><li>Single RJ45 connection </li></ul><ul><li>1:1 common transformer </li></ul><ul><li>Baseline wander correction </li></ul><ul><li>Digital adaptive equalization </li></ul><ul><li>Far-end fault detect </li></ul><ul><li>125 MHz clock generator and timing recovery </li></ul><ul><li>Loopback modes </li></ul>
  25. 25. Fast Ethernet Controller (FEC) <ul><li>IEEE® 802.3-compliant 10/100 Mbps Ethernet MAC. </li></ul><ul><li>Standard medium independent interface (MII) to physical layer. </li></ul><ul><li>Programmable max frame length supports IEEE 802.1 VLAN tags and priority. </li></ul><ul><li>Full and half duplex operation. </li></ul><ul><ul><li>50 MHz minimum platform clock frequency for full duplex </li></ul></ul><ul><ul><li>25 MHz minimum platform clock frequency for half duplex </li></ul></ul><ul><li>Bus-mastering design minimizes CPU intervention. </li></ul><ul><li>Transmit FIFO re-sends following collision. </li></ul><ul><li>Automatic receive FIFO flushing for runts and address recognition rejects. </li></ul>
  26. 26. I 2 C Module <ul><li>Compatibility with I 2 C bus standard. </li></ul><ul><li>Interface for EEPROMs, LCD controllers, ADC, and keypads. </li></ul><ul><li>Two-wire bidirectional serial bus. </li></ul><ul><li>Multiple master operation. </li></ul><ul><li>Programmable for one of 64 clock frequencies. </li></ul><ul><li>Interrupt driven, byte-by-byte transfer. </li></ul><ul><li>Automatic switching. </li></ul><ul><li>Start and stop signal generation and detection. </li></ul><ul><li>Repeated START signal generation. </li></ul>
  27. 27. Queued Serial Peripheral Interface (QSPI) <ul><li>Full-duplex, synchronous serial port. </li></ul><ul><li>Dedicated, 16-entry receive, transmit and command queues. </li></ul><ul><li>Transfer sizes from 8 to 16 bits inclusive. </li></ul><ul><li>Four peripheral chip selects. </li></ul><ul><li>Platform clock feeds fixed ÷2 followed by ÷1 to ÷255 prescaler to generate bit clock. </li></ul><ul><li>Standard four CPOL/CPHA combinations. </li></ul><ul><li>Optional pre- and post-transfer delays. </li></ul><ul><li>Wraparound mode for continuous transfers. </li></ul>
  28. 28. JTAG <ul><li>JTAG pins: </li></ul><ul><ul><li>TDI: test data input. </li></ul></ul><ul><ul><li>TDO: test data output. </li></ul></ul><ul><ul><li>TCK: test clock. </li></ul></ul><ul><ul><li>TMS: test mode select. </li></ul></ul><ul><ul><li>TRST: test reset. </li></ul></ul>
  29. 29. Additional Resource <ul><li>For ordering the MCF5223X, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MCF5223X&webpageId=1113331549638725695448&nodeId=0162468rH3YTLC00M95448&fromPage=tax </li></ul></ul>Newark Farnell

×