Mobicents Summit 2012 - Dmitri Soloviev - Telscale SS7 Card

•

1 like•1,066 views

The document discusses the Telscale SS7 card, which converts SS7 signaling into SIGTRAN protocols. It can be used as a standalone SS7 terminal or to interface existing PBXs to SIP networks. The card uses an FPGA and DSP running Linux to interface E1/T1 lines and implement various SS7 protocols in software. Current goals include optimization, new features, and improving usability. The card is already in production use and aims to provide a flexible platform for SS7 and SIGTRAN applications.

Technology

Telscale SS7 card
Part 1: long intro
● SS7, Sigtran and TDM

● What is it? G.704 structure

● Who are competitors?

● How long TDM will survive?

Part 2: Telscale SS7 card
● Architecture

● Use cases

● Software structure

● Current state & Goals

Telscale SS7 card

jSS7 and Telscale Card

CAMEL MAP

ISUP TCAP

SCCP →a card to convert SS7 into Sigtran
(M3UA, M2UA, M2PA)
M3UA MTP3 → support media (MGCP+G.711)
SCTP TCP MTP2 → G.703 to SIP gateway
→ G.703 probe
Ethernet HW

Telscale SS7 card

E1, T1 etc

● G.703 — pulse shaping, masks

● Bipolar coding with clock recovery (HDB-3 for E1)
● Sequence of bits

TS31 TS0 TS0 TS0 TS0 TS0 TS0 TS0 TS0 TS1 TS1
bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1

● 32 channels (time slots), 8 bits each

● Time slot 0: G.704. Dedicated content

● A time slot is a 64k channel: SS7 link, G.711 voice or whatever

● Quality monitoring: PBV (code errors) + CRC-4 (timeslot 0)

.. and why do they call it G.703?

Telscale SS7 card

Cards at the Market
● Dialogic
– sophisticated card with CPU onboard
– voice and signaling onboard
– OS driver, API

● Digium (Asterisk)
– low cost card w/o inteligence
– OS driver, interfaces timeslots to host CPU

● Telscale Card
– NO drivers:
stand-alone system with Ethernet interfacing
– DSP running uClinux:
DSP interfaces(SPORT) + power of linux

Telscale SS7 card

Is there a Market?
● GSM world (various SS7 apps with or w/o voice)
– initial GSM specs; available everywhere
– too much was invested

● Interfacing existing PBXs (ISDN ↔ SIP)

.. how long G.703 will survive?
.. how long will SS7 live?

Telscale SS7 card

Architecture
DSP Core
– running uClinux
– 2 Ethernet

E1/T1
line FPGA
interfacing

Additional – E1/T1 interfacing RAM SPI Par.
E1/T1 – SS7 MTP2(HDLC) 128M flash flash
receivers

FPGA
conf.memory

Telscale SS7 card

Use Cases

→ PCM terminal
● Set of SS7 terminals
● SS7 terminals + optional Voice
● ISDN ↔ SIP

→ SS7 probe for various apps

Telscale SS7 card
Software Structure
Part 1

An embedded system
with FPGA and linux

Flexible Schematics that
→ must be configured (from SPI flash)
to “build” a “hardware”
→ DSP can “reload” a new schematics
(@another offset)
→ SPI content can be changed Linux system that has
→ a flexible boot loader
→ linux + applications

Telscale SS7 card
Software Structure
Part 2
→ Various SS7/Sigtran stacks
in parallel
M3UA → SS7 links are distributed
M2UA M2PA
via shared memory
→ “multiplexing” works with
array of time slots,
SS7 links via SHM ea ether
→ processes time slot as
SS7 link
“Multiplexing” → controls time slot via
MGCP (ea media)
→ each driver interfaces
PCM driver PCM driver a PCM line

Telscale SS7 card
Current state & Goals
→ deployed already
→ production state, commercially available
Production (now)
→ fixing production cycle and logistics

Optimization (Q4'12) Features(Q1'13)
→ driver re-design (char → MMAP) → M2PA for card
→ moving part of MTP2 to FPGA → M2PA for jSS7

USABILITY
→ user-friendly configuration
FEATURES
→ SCTP Multihoming
→ M2UA/M2PA ?
→ T1 if requested
→ pseudo-interfaces for wireshark
VOICE
→ MGCP+RTP
→ DTMF+ECHO

Telscale SS7 card

Questions? Ideas?

Dmitri.Soloviev@telestax.com

http://OpenSigtran.org

The document provides an introduction to GPU programming using CUDA. It outlines GPU and CPU architectures, the CUDA programming model involving threads, blocks and grids, and CUDA C language extensions. It also discusses compilation with NVCC, memory hierarchies, profiling code with Valgrind/Callgrind, and Amdahl's law in the context of parallelization. A simple CUDA program example is provided to demonstrate basic concepts like kernel launches and data transfers between host and device memory.

RISC-V offers simple, modular ISA : Notes

Subhajit Sahu

Highlighted notes of article suggested for reading by Gamers Nexus: RISC-V offers simple, modular ISA New CPU Instruction Set Is Open and Extensible By David Kanter (March 28, 2016) David Kanter is Principal Analyst and Editor-in-Chief at Real World Tech, which focuses on microprocessors, servers, graphics, computers, and semiconductors. He is also a consultant specializing in intellectual property evaluation/development and technical/competitive analysis. Mr. Kanter has been quoted in the New York Times, CNN, Reuters, IEEE Spectrum, and many more over the last 10 years. Mr. Kanter was a Founder of Strandera, a startup commercializing advanced multi-core hardware and software technologies. Prior to Strandera, he was an early employee at Aster Data Systems (acquired by Teradata), a leader in data warehousing and analytic databases. He also was an Economic Analyst at the Huron Consulting Group and graduated with an S.B. in Mathematics with a specialization in Computer Science, and Economics from the University of Chicago.

Comandos ospf

1 2d

This document provides an overview and summary of OSPF commands for the Matrix X Router. It describes the global configuration mode OSPF command "router ospf" which is used to enter OSPF Router Configuration mode. It also lists and provides brief descriptions of global OSPF commands including "advertise-subnet", "authentication", "compatible rfc1583", and others. Tables provide page references for additional information on area commands, default commands, interface commands, and querying commands.

PASTE: Network Stacks Must Integrate with NVMM Abstractions

micchie

The document discusses the implications of non-volatile main memories (NVMMs) for networking stacks. It presents a case study on write-ahead logging that shows networking can become a bottleneck. It then proposes a PASTE approach using static packet buffers on NVMM to enable fast, zero-copy logging with minimal data movement and caching issues. Preliminary results show a 10-88% increase in throughput and 9-46% decrease in latency.

Poll mode driver integration into dpdk

Vipin Varghese

This document discusses integrating a custom Poll Mode Driver (PMD) into DPDK to enable offloading packet processing tasks to multicore or application-specific integrated circuit (ASIC) hardware. A use case of offloading intrusion detection system and IPsec processing to multicore hardware while encrypted SSL traffic is decrypted via the multicore is presented. Developing a custom PMD allows leveraging multicore/ASIC as a line card or load balancer while avoiding issues like extra overhead from additional interfaces, frame reprocessing, and increased latency when using network connections between DPDK and hardware. Performance is improved by directly connecting the multicore/ASIC to DPDK which removes overhead and provides a high-throughput interface.

mSwitch: A Highly-Scalable, Modular Software Switch

micchie

This document summarizes the mSwitch software which provides a highly scalable and modular approach to software switching. The key points are: - mSwitch separates the switching fabric from the switching logic to allow for modular and flexible forwarding decisions while still achieving high performance. - It uses a scalable packet switching algorithm and separate packet buffers per port to efficiently handle packet I/O across many ports. - Switching logic is implemented as kernel modules, allowing flexibility to change the forwarding behavior while the switch is running. - Evaluation shows mSwitch scales throughput linearly with CPU cores and ports, outperforming other software switches in port scalability and CPU efficiency. It can forward over 1 million minimum sized packets per

This document discusses various types and implementations of parallel architectures. It covers parallelism concepts like data, thread, and instruction level parallelism. It also describes Flynn's taxonomy of parallel systems and different parallel machine designs like SIMD, vector, VLIW, and MIMD architectures. Specific examples of parallel supercomputers are provided like Cray, Connection Machine, and SGI Origin. Challenges in parallel programming and portability are also summarized.

Building a QT based solution on a i.MX7 processor running Linux and FreeRTOS

Fernando Luiz Cola

This document discusses developing embedded solutions using asymmetric multiprocessing (AMP) architectures. It provides an overview of AMP vs symmetric multiprocessing (SMP), examples of AMP applications, and the NXP I.MX7 dual-core processor architecture. It then demonstrates inter-processor communication between Linux on an ARM Cortex-A7 core and FreeRTOS on a Cortex-M4 core using RPMSG. Finally, it shows an example Qt application running on Linux that receives sensor data from FreeRTOS via RPMSG and displays it in real-time charts.

piplining ...very nice

Osama Tahir

Shibu lijack is a technique used in advanced microprocessors where the microprocessor begins executing the second instruction before the first has been completed. It overlaps the execution of multiple instructions to increase CPU speed. There are three main types of hazards that can reduce this speed: structural hazards due to competing for limited hardware resources, data hazards when instructions depend on data that is not ready yet, and control hazards when the next instruction path is unknown until a branch is resolved. Solutions include stalling the pipeline, forwarding data early, or predicting instruction paths.

OpenStack SDN

Adrian Norte Fernandez

SDN allows programmatic creation and management of networks. Neutron is OpenStack's networking service that uses Open vSwitch and plugins like ML2 with GRE tunneling to abstract logical networks over a physical network. When a packet arrives for a VM, it is encapsulated in a GRE tunnel to the compute node hosting the VM and handed off to the VM via bridges and namespaces that isolate tenant networks.

Netmap presentation

Amir Razmjou

Netmap is a framework that allows applications to access network interface controller (NIC) hardware at near line-rate speeds. It reduces packet processing costs by eliminating system calls, memory copies between layers, and memory allocation/deallocation. Netmap provides applications with direct access to NIC buffers and rings via memory mapping, allowing packets to bypass the kernel for fast I/O. It also supports multi-queue NICs and provides rings for the host stack to still use the NIC while netmap applications have access.

Linux rumpkernel - ABC2018 (AsiaBSDCon 2018)

Hajime Tazaki

This document discusses Linux rumpkernel and the LKL (Linux Kernel Library). It introduces LKL as a library that allows running unmodified Linux kernel code in various configurations like application libraries and microkernels. LKL transforms a monolithic kernel code into a reusable library called liblkl by outsourcing machine-dependent code and keeping application and kernel code untouched. It provides different interfaces for applications to interact with the LKL kernel, including direct syscalls, hijacking the host library, or extending an alternative libc. Various usages of LKL are also presented, such as running a network stack in userspace (NUSE), building unikernels, and doing network simulation with ns-3 using the Linux network stack.

T2: What the Second Generation Holds

Vlado Handziski

Recent advance in netmap/VALE(mSwitch)

micchie

This document summarizes recent advancements in netmap and VALE (mSwitch). Netmap is a fast packet I/O mechanism that removes unnecessary metadata and reduces data copies between the NIC and user-space. VALE (mSwitch) is a netmap-based software switch that can achieve line-rate packet forwarding using a minimal packet representation and efficient forwarding algorithms. Evaluation shows the bare mSwitch can saturate 10Gbps links with low CPU usage and scales well with number of ports. The document outlines the key techniques that enable high performance, including netmap, list-based forwarding, and separating packet processing from the switching fabric.

Network stack personality in Android phone - netdev 2.2

Hajime Tazaki

An alternate approach to updating the Android network stack is to implement the stack in userspace using the Linux Kernel Library (LKL). This allows new network protocols and stacks to be added without replacing the host kernel. Measurements show the userspace LKL stack can achieve comparable performance to the native kernel over WiFi, and higher throughput over multipath TCP despite processing packets twice. However, results are often unstable and there are some limitations like asynchronous signal safety that require further work. Overall, using LKL provides a way to more easily distribute new network code without waiting for kernel upgrades.

Linux Kernel Library - Reusing Monolithic Kernel

Hajime Tazaki

The document summarizes the Linux Kernel Library (LKL), which allows running Linux kernel code in userspace. LKL provides a hardware-independent architecture and interfaces to underlying resources like clocks and memory allocation. This allows Linux drivers and code to run on different platforms like Windows and as application libraries. LKL implements common kernel functions with pthreads and exposes syscall interfaces for applications. It has various use cases like instant kernel bypass, reusing kernel code in userspace programs, and building unikernels. The performance of LKL is evaluated and shows improvements from optimizations like avoiding dynamic allocation.

Heterogeneous multiprocessing on androd and i.mx7

Kynetics

PCIe

ChiaYang Tsai

This document provides an overview of the PCI Express physical layer technology. It discusses the lane counts and data rates supported by different PCIe versions. It describes the three logical layers of PCIe and divides the physical layer into logical and electrical sub-blocks. It explains several key physical layer technologies including 8b/10b encoding, data scrambling, de-emphasis, and link training. Link training negotiates link parameters and ensures synchronization between devices on the link.

Asymmetric Multiprocessing - Kynetics ELC 2018 portland

Nicola La Gloria

Asymmetric multi-processing (AMP) systems fulfill the need for high performance and real-time by combining the responsiveness of a MCU with the processing power of an application processor which runs a full OS. This talk will present a technical overview on asymmetric multiprocessing platforms focussing on motivations, use cases and how to handle interprocess communication between MCU and MPU in practice.

LF_DPDK17_GRO/GSO Libraries: Bring Significant Performance Gains to DPDK-base...

LF_DPDK

This document provides an overview of GRO and GSO in DPDK. It discusses how GRO and GSO can be used to reduce packet processing overheads by merging or splitting packets. It describes the GRO and GSO algorithms used in DPDK to handle packets in a lightweight manner. It also outlines an experiment that shows the performance improvements of DPDK GRO and GSO compared to no offloading or Linux offloading.

Bare Metal Club ATX: Networking Discussion

Carl Perry

Playing BBR with a userspace network stack

Hajime Tazaki

Hajime Tazaki presented on using the Linux Kernel Library (LKL) to run a userspace network stack with TCP BBR. Initial benchmarks showed poor BBR performance with LKL due to imprecise timestamps. Improving the timestamp resolution and scheduler optimizations increased BBR throughput to be comparable to native Linux. Further work is needed to fully understand performance impacts and optimize for high-speed networks. LKL provides a reusable network stack across platforms but faces challenges with timing accuracy required for features like BBR.

M Traxler TRB and Trasgo

Miguel Morales

The TRB was developed as a general purpose platform for time-to-digital converters (TDCs) and fast data acquisition for nuclear physics experiments with thousands of channels. It provides integrated TDC, data acquisition, and local computing capabilities in a modular design that can be directly mounted on detectors. Measurements showed time resolutions of 40 picoseconds for 128 channels and 16 picoseconds for 32 channels. The TRB has been successfully used in several experiments and more developments are planned to further improve performance and reduce costs.

I3 multicore processor

Amol Barewar

The document provides information about the Intel i3 processor. It begins with a brief introduction of processors in general, then discusses some key features of the i3 processor, including that it is a dual core chip that is faster than the previous Core2Duo. It describes technologies like multi-core processing, Hyper-Threading, virtualization support, and caches that improve processor performance. Finally, it mentions security features like Execute Disable Bit that help prevent buffer overflow attacks.

Linux Network Stack

Adrien Mahieux

- The document discusses Linux network stack monitoring and configuration. It begins with definitions of key concepts like RSS, RPS, RFS, LRO, GRO, DCA, XDP and BPF. - It then provides an overview of how the network stack works from the hardware interrupts and driver level up through routing, TCP/IP and to the socket level. - Monitoring tools like ethtool, ftrace and /proc/interrupts are described for viewing hardware statistics, software stack traces and interrupt information.

Graphics processing uni computer archiecture

Haris456

This document discusses graphics processing units (GPUs) and their evolution from specialized hardware for graphics to general-purpose parallel processors. It covers key aspects of GPU architecture like their massively parallel threading model, SIMD execution, memory hierarchy, and how programming models like CUDA map computations to large numbers of threads grouped into blocks. Examples of GPU hardware like Nvidia's Fermi architecture are also summarized.

Cuda tutorial

Mahesh Khadatare

This document discusses GPU computing with CUDA and NVIDIA Tesla hardware. It provides an overview of GPU computing and how it differs from CPU computing in being optimized for data-parallel throughput rather than low latency. It also describes the key specifications of the NVIDIA Tesla C1060 GPU and Tesla streaming multiprocessor. Finally, it outlines the CUDA parallel computing architecture and programming model, including how applications use the GPU as a coprocessor through kernels launched from the CPU.

Philippe Langlois - LTE Pwnage - P1security

P1Security

Today, we’re entering the realm of LTE super high speed always-on connectivity and with that comes the victory of TCP/IP in front of the old ITU/3GPP protocols. And with this comes many side effects: software gets standardized, everything runs on top of ATCA (Advanced Telecom Computing Architecture) hardware running mostly Linux -give or take 6 or 8 proprietary FPGA-based sister cards, TFTP-booted with decade old VxWorks that routinely show hardcoded DES credentials and funny “behaviour”. Easily 20 GB of fat C++ binaries, some for x86, PPC, MIPS, some with up to 200 Mbytes file sizes for one single EXE! It’s called a vulnerability research and reverse engineering paradise… or hell. All the protocols now run on top of IP, which ends up having 12 layers thanks to encapsulation and still the weight of legacy in bugs quantity and diversity. We’ll see how the porting of SS7 MAP on top of IP (SIGTRAN, Diameter) has given rise to funny Denial of Service (DoS) attacks against telecom core elements (DSR, STP), with trashy-crashy anti-forensics consequences for DPI and tracking (Hey @grugq!!). We’ll look into specific vulnerabilities, and talk about the very particular way that Network Equipment Vendors deal with security in the telecom domain. We will demo a virtualized Huawei HSS from our testbed and show some of the vulnerabilities and attacks directly on the equipment itself. We will finally talk about telco equipment and product security reviews and the fallacy of (some) certification and (many) standardization attempts. We will then see how to conduct a practical and fast telecom product security life cycle with automation and open source tools.

What's hot

L05 parallel

MEPCO Schlenk Engineering College

Building a QT based solution on a i.MX7 processor running Linux and FreeRTOS

Fernando Luiz Cola

piplining ...very nice

Osama Tahir

OpenStack SDN

Adrian Norte Fernandez

Netmap presentation

Amir Razmjou

Linux rumpkernel - ABC2018 (AsiaBSDCon 2018)

Hajime Tazaki

T2: What the Second Generation Holds

Vlado Handziski

Recent advance in netmap/VALE(mSwitch)

micchie

Network stack personality in Android phone - netdev 2.2

Hajime Tazaki

Linux Kernel Library - Reusing Monolithic Kernel

Hajime Tazaki

Heterogeneous multiprocessing on androd and i.mx7

Kynetics

PCIe

ChiaYang Tsai

Asymmetric Multiprocessing - Kynetics ELC 2018 portland

Nicola La Gloria

LF_DPDK17_GRO/GSO Libraries: Bring Significant Performance Gains to DPDK-base...

LF_DPDK

Bare Metal Club ATX: Networking Discussion

Carl Perry

Playing BBR with a userspace network stack

Hajime Tazaki

M Traxler TRB and Trasgo

Miguel Morales

I3 multicore processor

Amol Barewar

What's hot (18)

L05 parallel

Building a QT based solution on a i.MX7 processor running Linux and FreeRTOS

piplining ...very nice

OpenStack SDN

Netmap presentation

Linux rumpkernel - ABC2018 (AsiaBSDCon 2018)

T2: What the Second Generation Holds

Recent advance in netmap/VALE(mSwitch)

Network stack personality in Android phone - netdev 2.2

Linux Kernel Library - Reusing Monolithic Kernel

Heterogeneous multiprocessing on androd and i.mx7

PCIe

Asymmetric Multiprocessing - Kynetics ELC 2018 portland

LF_DPDK17_GRO/GSO Libraries: Bring Significant Performance Gains to DPDK-base...

Bare Metal Club ATX: Networking Discussion

Playing BBR with a userspace network stack

M Traxler TRB and Trasgo

I3 multicore processor

Similar to Mobicents Summit 2012 - Dmitri Soloviev - Telscale SS7 Card

Linux Network Stack

Adrien Mahieux

Graphics processing uni computer archiecture

Haris456

Cuda tutorial

Mahesh Khadatare

Philippe Langlois - LTE Pwnage - P1security

P1Security

Philippe Langlois - Hacking HLR HSS and MME core network elements

P1Security

6 Lo Wpan Tutorial 20080206

pauldeng

This document provides an overview of 6LoWPAN (IPv6 over Low-Power Wireless Personal Area Networks), which allows IP to be implemented on IEEE 802.15.4 low-power wireless networks. It describes how 6LoWPAN compresses IPv6 and higher-level protocol headers to address constraints of low-power wireless networks like small packet sizes. Key techniques include header compression, mesh routing at the link layer under the IP topology, and leveraging existing IP standards to meet requirements of long device lifetimes on limited energy in highly embedded environments.

Workshop actualización SVG CESGA 2012

CESGA Centro de Supercomputación de Galicia

The document summarizes upgrades made to the SVG supercomputer in 2012, including: - Upgrading to Sandy Bridge processors with 192 cores and 1.5TB memory on thin nodes and 512GB memory on fat nodes. - Installing an Infiniband FDR 56Gb/s network with 4Tb/s bandwidth and 1us MPI latency. - Configuring queues to take advantage of the Infiniband network and turbo boost, allowing up to 112 cores and 1024GB memory per job. - Benchmark results showed peak performance of 3788 GFlops on thin nodes and 563 GFlops on fat nodes.

Case Study: Porting Qt for Embedded Linux on Embedded Processors

account inactive

Qt has been crucial for Texas Instruments to develop attractive applications as system demonstrations including appealing graphics and communication features within a defined time space and resource environment. This session will discuss porting and using Qt for Embedded Linux on several embedded processors. Walzer will present TI's experience and the current status of configuring Qt for ARM based platforms running Linux as the operating system, as well as have a look at the current state of integrating hardware accelerators such as DSP and graphics cores into Qt4. Presentation by Frank Walzer held during Qt Developer Days 2009. http://qt.nokia.com/developer/learning/elearning

MPLS Concepts and Fundamentals

Shawn Zandi

fpga1 - What is.pptx

ssuser0de10a

This document provides an overview of field-programmable gate arrays (FPGAs): FPGAs can be configured to act like any circuit and do many computational tasks. Unlike CPUs and GPUs which have fixed hardware, FPGAs have programmable hardware that can be optimized for specific applications. This specialized hardware enables much higher performance and efficiency than general purpose processors. Programming FPGAs involves using hardware description languages to describe circuits or high-level synthesis tools to compile software languages into hardware implementations.

Tizen RT: A Lightweight RTOS Platform for Low-End IoT Devices

Samsung Open Source Group

This document provides an overview and agenda for a presentation on Tizen RT, a lightweight real-time operating system (RTOS) platform for low-end IoT devices. The presentation will cover the technology and features of Tizen RT, how it differs from other RTOS options like NuttX and TinyAra, and how to build and run applications on Tizen RT using examples like building a simple "Hello World" app. It also lists several demos that will be shown, including connecting to WiFi, running MQTT subscriptions, and controlling GPIO pins.

SIGTRAN - An Introduction

Tareque Hossain

Introduction to DPDK

Kernel TLV

DPDK is a set of drivers and libraries that allow applications to bypass the Linux kernel and access network interface cards directly for very high performance packet processing. It is commonly used for software routers, switches, and other network applications. DPDK can achieve over 11 times higher packet forwarding rates than applications using the Linux kernel network stack alone. While it provides best-in-class performance, DPDK also has disadvantages like reduced security and isolation from standard Linux services.

100 M pps on PC.

Redge Technologies

This document discusses achieving very high speeds of 100 million packets per second (100Mpps) on commodity PC hardware using kernel bypassing techniques. It describes the company redCDN and their development of a DDoS mitigation solution called redGuardian. Key challenges discussed include the limitations of operating system network stacks at high speeds, hardware capabilities, and how data plane frameworks like DPDK can be used to bypass the OS and achieve wire-speed performance by accessing network interface cards directly from userspace.

Using Many-Core Processors to Improve the Performance of Space Computing Plat...

Fisnik Kraja

This document summarizes a presentation on introducing many-core and commercial off-the-shelf (COTS) technologies into satellite computing architectures. It discusses constraints of onboard computers like power, size, heat, and high reliability requirements. It proposes a new architecture using many-core processors and COTS products to improve processing abilities while maintaining reliability through hardware and software fault tolerance techniques. It evaluates the architecture on synthetic aperture radar benchmarking and finds performance scales linearly with cores. Combining COTS with radiation-hardened components could provide over 100x speedup and improved reliability, flexibility, and portability.

FPGA In a Nutshell

Somnath Mazumdar

The FlexTiles Development Platform offers Dual FPGA for 3D SoC Prototyping

FlexTiles Team

This document summarizes an FPGA carrier board called the SMT166. It has the following key features: - It contains two Virtex-6 FPGAs and memory banks that can be used for processing and storage. - It supports various mezzanine cards and modules through SLB connectors, including ADC boards and optional DSP modules. - It provides interfaces such as PCIe, SATA, Ethernet and USB to connect to other devices and systems.

GPUDirect RDMA and Green Multi-GPU Architectures

inside-BigData.com

Dustin Franklin (GPGPU Applications Engineer, GE Intelligent Platforms ) presents: "GPUDirect support for RDMA provides low-latency interconnectivity between NVIDIA GPUs and various networking, storage, and FPGA devices. Discussion will include how the CUDA 5 technology increases GPU autonomy and promotes multi-GPU topologies with high GPU-to-CPU ratios. In addition to improved bandwidth and latency, the resulting increase in GFLOPS/watt poses a significant impact to both HPC and embedded applications. We will dig into scalable PCIe switch hierarchies, as well as software infrastructure to manage device interopability and GPUDirect streaming. Highlighting emerging architectures composed of Tegra-style SoCs that further decouple GPUs from discrete CPUs to achieve greater computational density." Learn more at: http://www.gputechconf.com/page/home.html

Segment Routing

APNIC

This document provides an introduction to segment routing. It discusses: - The objective of segment routing is to enable source routing without requiring state in intermediate nodes. - Segment routing allows encoding paths as sequences of topological sub-paths called segments. Segments can represent nodes, links, or services. - The IETF SPRING working group is standardizing segment routing to address issues with scalability of traffic engineering and fast reroute with protocols like RSVP-TE and LDP. Segment routing aims to provide these capabilities without per-flow state.

From fermi to kepler

Ofer Rosenberg

The document summarizes the evolution of NVIDIA GPU architectures from Fermi to Kepler. Key points include: - Fermi GF100 introduced the SM with 32 CUDA cores and improvements in the GF104 including 48 CUDA cores and instruction level parallelism. - Kepler GK104 introduced the SMX with 192 CUDA cores organized into six clusters, allowing it to issue instructions to four warps concurrently. - While Kepler has fewer multiprocessors than Fermi, each Kepler SMX is more powerful with twice the register file and ability to execute warps in a single cycle. - Kepler also improved scheduling with features like Hyper-Q allowing simultaneous processing from multiple CPU processes.

Similar to Mobicents Summit 2012 - Dmitri Soloviev - Telscale SS7 Card (20)

Linux Network Stack

Graphics processing uni computer archiecture

Cuda tutorial

Philippe Langlois - LTE Pwnage - P1security

Philippe Langlois - Hacking HLR HSS and MME core network elements

6 Lo Wpan Tutorial 20080206

Workshop actualización SVG CESGA 2012

Case Study: Porting Qt for Embedded Linux on Embedded Processors

MPLS Concepts and Fundamentals

fpga1 - What is.pptx

Tizen RT: A Lightweight RTOS Platform for Low-End IoT Devices

SIGTRAN - An Introduction

Introduction to DPDK

100 M pps on PC.

Using Many-Core Processors to Improve the Performance of Space Computing Plat...

FPGA In a Nutshell

The FlexTiles Development Platform offers Dual FPGA for 3D SoC Prototyping

GPUDirect RDMA and Green Multi-GPU Architectures

Segment Routing

From fermi to kepler

More from telestax

Api and fly! CPaaS Enablement: Combining Apps, Networks, and APIs

Mobicents Summit 2012 - Dmitri Soloviev - Telscale SS7 Card

Recommended

Recommended

More Related Content

What's hot

What's hot (18)

Similar to Mobicents Summit 2012 - Dmitri Soloviev - Telscale SS7 Card

Similar to Mobicents Summit 2012 - Dmitri Soloviev - Telscale SS7 Card (20)

More from telestax

More from telestax (20)

Recently uploaded

Recently uploaded (20)

Mobicents Summit 2012 - Dmitri Soloviev - Telscale SS7 Card