Linux Plumbers
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Linux Plumbers, Santa Rosa, California 7-9 September, 2011 http://www.linuxplumbersconf.org/2011/ocw/users/963
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Cgroupv1 (or just "cgroups") has helped revolutionize the way that we manage and use containers over the past 8 years. In kernel 4.5, a complete overhaul is coming -- cgroupv2. This talk will go into why a new control group system was needed, the changes from cgroupv1, and practical uses that you can apply to improve the level of control you have over the processes on your servers.
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Presented at Linux Plumbers 2018
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Rohit Jnagal, David Lo, Dragos Sbirlea - Google
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1) Bus-based architectures have CPUs, caches and shared memory connected by a shared bus. The bus bandwidth limits scalability. It discusses the memory coherence problem and snooping protocols like MESI to address it.
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interference delay experienced by running tasks on the platform.
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interference delay analysis for COTS multicore systems. The analysis
considers a COTS processor that can generate multiple outstanding
requests and a COTS DRAM controller that has a separate read and write
request buffer, prioritizes reads over writes, and supports
out-of-order request processing. Focusing on LLC and DRAM bank
partitioned systems, our analysis computes worst-case upper bounds on
memory-interference delays, caused by competing memory requests.
We validate our analysis on a Gem5 full-system simulator modeling a
realistic COTS multicore platform, with a set of carefully designed
synthetic benchmarks as well as SPEC2006 benchmarks.
The evaluation results show that our analysis produces safe upper
bounds in all tested benchmarks, while the current state-of-the-art analysis significantly
under-estimates the delays.
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In this paper, we show that cache partitioning does
not necessarily ensure predictable cache performance in modern
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memory-level-parallelism (MLP).
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multicore platforms (four distinct CPU architectures) and a cycleaccurate
full system simulator, we show that special hardware
registers in non-blocking caches, known as Miss Status Holding
Registers (MSHRs), which track the status of outstanding cachemisses,
can be a significant source of contention; we observe up
to 21X WCET increase in a real COTS multicore platform due
to MSHR contention.
We propose a hardware and system software (OS) collaborative
approach to efficiently eliminate MSHR contention for
multicore real-time systems. Our approach includes a low-cost
hardware extension that enables dynamic control of per-core
MLP by the OS. Using the hardware extension, the OS scheduler
then globally controls each core’s MLP in such a way that
eliminates MSHR contention and maximizes overall throughput
of the system.
We implement the hardware extension in a cycle-accurate fullsystem
simulator and the scheduler modification in Linux 3.14
kernel. We evaluate the effectiveness of our approach using a set
of synthetic and macro benchmarks. In a case study, we achieve
up to 19% WCET reduction (average: 13%) for a set of EEMBC
benchmarks compared to a baseline cache partitioning setup.
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Speaker:
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https://github.com/veltzer
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Zanabria alvarado alejandra-el_lenguaje_de_las_manos.
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Los ademanes son movimientos del cuerpo que forman parte integral de la comunicación no verbal y pueden reforzar o contradecir el mensaje verbal. Los ademanes acompañan al lenguaje hablado a menos que se trate del lenguaje de señas utilizado por los sordomudos. Son importantes porque les dan énfasis visual y emocional a las palabras del orador y permiten transmitir ideas y sentimientos de manera más efectiva.
Apuntes metodologia investigación
Este documento presenta conceptos clave relacionados con la investigación como ciencia, teoría, técnica, tecnología e investigación científica. También describe las etapas del proceso de investigación incluyendo la concepción de la idea, descripción del problema, marco de referencia, formulación de hipótesis, método, elaboración de documentos y reportes. Finalmente, discute la relación entre investigación, docencia y universidad.
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This document summarizes two shared memory architectures - bus-based and directory-based. It describes:
1) Bus-based architectures have CPUs, caches and shared memory connected by a shared bus. The bus bandwidth limits scalability. It discusses the memory coherence problem and snooping protocols like MESI to address it.
2) Directory-based architectures avoid broadcast snooping and scale better using point-to-point messaging. Each block tracks its presence in caches using a directory with processor bits. It brings coherence through directory lookups and targeted invalidations.
Task migration using CRIU
This document discusses Google's use of CRIU for task migration at scale. It provides background on Borg, Google's cluster management system, and how tasks run in isolated containers. CRIU is used to checkpoint and restore task state, allowing tasks to be migrated transparently to avoid evictions. While migrations currently take 1-2 minutes, work is ongoing to improve performance and implement live migration to support latency-sensitive tasks. Security around CRIU's use of privileges is also an area of focus. Overall, CRIU has worked well but continued collaboration is needed to address remaining challenges.
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Control groups (cgroups) allow administrators to allocate CPU, memory, storage, and other system resources to groups of processes running on the system. The document describes testing done using cgroups on a Red Hat Enterprise Linux 6 system with four Oracle database instances running an OLTP workload. It demonstrates how cgroups can be used for application consolidation, performance optimization, dynamic resource management, and application isolation.
Cache coherence ppt
This document discusses cache coherence in single and multiprocessor systems. It provides techniques to avoid inconsistencies between cache and main memory including write-through, write-back, and instruction caching. For multiprocessors, it discusses issues with sharing writable data, process migration, and I/O activity. Software solutions involve compiler and OS management while hardware uses coherence protocols like snoopy and directory protocols.
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Cache coherence and consistency model in multiprocessor architecture. These slide show the introduction of multiprocessor and cache multilevel and then describe the basic mechanism of coherence and consistency protocols. In particular the protocols describe are the following: snooping and directory protocols for the coherence part and sequential protocol for the consistency part. There are also example of (in)consistency and (in)coherence.
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In modern Commercial Off-The-Shelf (COTS) multicore systems, each core
can generate many parallel memory requests at a time. The processing of
these parallel requests in the DRAM controller greatly affects the memory
interference delay experienced by running tasks on the platform.
In this paper, we present a new parallelism-aware worst-case memory
interference delay analysis for COTS multicore systems. The analysis
considers a COTS processor that can generate multiple outstanding
requests and a COTS DRAM controller that has a separate read and write
request buffer, prioritizes reads over writes, and supports
out-of-order request processing. Focusing on LLC and DRAM bank
partitioned systems, our analysis computes worst-case upper bounds on
memory-interference delays, caused by competing memory requests.
We validate our analysis on a Gem5 full-system simulator modeling a
realistic COTS multicore platform, with a set of carefully designed
synthetic benchmarks as well as SPEC2006 benchmarks.
The evaluation results show that our analysis produces safe upper
bounds in all tested benchmarks, while the current state-of-the-art analysis significantly
under-estimates the delays.
Taming Non-blocking Caches to Improve Isolation in Multicore Real-Time Systems
In this paper, we show that cache partitioning does
not necessarily ensure predictable cache performance in modern
COTS multicore platforms that use non-blocking caches to exploit
memory-level-parallelism (MLP).
Through carefully designed experiments using three real COTS
multicore platforms (four distinct CPU architectures) and a cycleaccurate
full system simulator, we show that special hardware
registers in non-blocking caches, known as Miss Status Holding
Registers (MSHRs), which track the status of outstanding cachemisses,
can be a significant source of contention; we observe up
to 21X WCET increase in a real COTS multicore platform due
to MSHR contention.
We propose a hardware and system software (OS) collaborative
approach to efficiently eliminate MSHR contention for
multicore real-time systems. Our approach includes a low-cost
hardware extension that enables dynamic control of per-core
MLP by the OS. Using the hardware extension, the OS scheduler
then globally controls each core’s MLP in such a way that
eliminates MSHR contention and maximizes overall throughput
of the system.
We implement the hardware extension in a cycle-accurate fullsystem
simulator and the scheduler modification in Linux 3.14
kernel. We evaluate the effectiveness of our approach using a set
of synthetic and macro benchmarks. In a case study, we achieve
up to 19% WCET reduction (average: 13%) for a set of EEMBC
benchmarks compared to a baseline cache partitioning setup.
Advanced Namespaces and cgroups
The document provides an overview of the cgroup subsystem and namespace subsystem in Linux, which form the basis of Linux containers. It discusses how cgroups and namespaces enable lightweight virtualization of processes through isolation of resources and namespaces. It then covers specific aspects of cgroups like the memory, CPU, devices, and PIDs controllers. It also summarizes the key differences and improvements in the cgroup v2 implementation, such as having a single unified hierarchy and consistent controller interfaces.
Multiprocessor Scheduling
This document discusses scheduling for multicore processors. It begins by explaining that multicore processors pack multiple CPU cores onto a single chip to increase processing speed. However, traditional C programs only use one CPU, so simply adding more CPUs does not speed programs up. The document then covers several challenges in multicore scheduling, such as cache coherence and affinity. It proposes some solutions like multi-queue scheduling, where each CPU has its own job queue, to help address issues like lack of scalability from single-queue approaches. Common Linux schedulers like the O(1) scheduler and Completely Fair Scheduler that use multiple queues are also mentioned.
Directory based cache coherence
The document discusses non-uniform cache architectures (NUCA), cache coherence, and different implementations of directories in multicore systems. It describes NUCA designs that map data to banks based on distance from the controller to exploit non-uniform access times. Cache coherence is maintained using directory-based protocols that track copies of cache blocks. Directories can be implemented off-chip in DRAM or on-chip using duplicate tag stores or distributing the directory among cache banks. Examples of systems like SGI Origin2000 and Tilera Tile64 that use these techniques are also outlined.
Cache coherence
The document discusses cache coherence in multiprocessor systems. It describes the cache coherence problem that can arise when multiple processors have caches and can access shared memory. It then summarizes two primary hardware solutions: directory protocols which maintain information about which caches hold which memory lines; and snoopy cache protocols where cache controllers monitor bus traffic to maintain coherence without a directory. Finally it mentions a software-based solution relying on compiler analysis and operating system support.
Snooping protocols 3
The document discusses snooping cache coherence protocols. It covers key design issues like when memory gets updated, who responds to requests, and optimizations like adding states. It then describes several specific protocols: a 4-state protocol, the MESI protocol, an update protocol called Dragon, and issues around implementing these with split transaction buses. Key challenges addressed include non-atomic transitions, livelock, and handling multiple outstanding requests.
Linux Locking Mechanisms
Agenda:
In this talk we will present various locking mechanisms implemented in the linux kernel.
From System V locks to raw spinlocks and the RT patch.
Speaker:
Mark Veltzer - CTO of Hinbit and a senior instructor at John Bryce. Mark is also a member of the Free Source Foundation and contributes to many free projects.
https://github.com/veltzer
Cache coherence
Cache coherence is a technique used in multiprocessing systems to maintain consistency between caches and shared memory. When a processor modifies a variable in its cache that is also stored in another processor's cache, inconsistency arises. There are three main techniques to maintain cache coherence: snoopy-based protocols invalidate or update other caches when a write is observed; directory-based protocols use a directory to control access to shared data and update or invalidate caches; and snarfing-based protocols allow caches to watch addresses and data to update copies when writes are seen. Cache coherence aims to ensure data consistency across caches for shared resources.
Continguous Memory Allocator in the Linux Kernel
Agenda:
Continguous Memory Allocator - how to allocate large continguous memory for large scale DMA in the kernel.
Speaker:
Mark Veltzer - CTO of Hinbit and a senior instructor at John Bryce. Mark is also a member of the Free Source Foundation and contributes to many free projects.
Ch23
The document discusses various techniques for performance tuning a database system, including identifying and eliminating bottlenecks. It describes tuning at the hardware level by adding resources like disks and memory. Database parameters and design can also be tuned, such as schema changes, appropriate indices, and materialized views. Transactions play a role and can be tuned as well. The overall goal is to optimize performance by reducing bottlenecks.
HP-UX 11i LVM Mirroring Features and Multi-threads by Dusan Baljevic
The document discusses methods used in Logical Volume Manager (LVM) to maintain consistency between mirrored logical volumes. It describes two key methods - the Mirror Write Cache (MWC) and Mirror Consistency Record (MCR). The MWC resides in memory and tracks pending writes, while the MCR on disk is used for recovery after crashes. The document provides details on how these methods work and how they can impact performance and recovery times in different situations.
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Ademan
El término "ademán" proviene del árabe y se refiere a las actitudes corporales que denotan estados emocionales o intenciones de acción. Los ademanes constituyen una forma de comunicación no verbal que puede hacer que un mensaje sea más eficaz o ineficaz. Los ademanes no siempre reemplazan el lenguaje hablado, sino que más bien lo complementan y son el único medio de comunicación para los sordomudos.
Zanabria alvarado alejandra-el_lenguaje_de_las_manos.
Introducción al Arte UDEP 2012-I
Interpretación realizada por los alumnos de IAR E del tema "Las manos en el Arte"
Ademan
Los ademanes son movimientos del cuerpo que forman parte integral de la comunicación no verbal y pueden reforzar o contradecir el mensaje verbal. Los ademanes acompañan al lenguaje hablado a menos que se trate del lenguaje de señas utilizado por los sordomudos. Son importantes porque les dan énfasis visual y emocional a las palabras del orador y permiten transmitir ideas y sentimientos de manera más efectiva.
Apuntes metodologia investigación
Este documento presenta conceptos clave relacionados con la investigación como ciencia, teoría, técnica, tecnología e investigación científica. También describe las etapas del proceso de investigación incluyendo la concepción de la idea, descripción del problema, marco de referencia, formulación de hipótesis, método, elaboración de documentos y reportes. Finalmente, discute la relación entre investigación, docencia y universidad.
Oratoria
El documento habla sobre la oratoria. Explica que la oratoria es el arte de hablar en público de manera elocuente para informar, convencer o persuadir a una audiencia. Señala que la oratoria se desarrolló en la antigua Grecia y que figuras como Sócrates, Demóstenes y Cicerón fueron grandes oradores. El documento luego proporciona consejos para hablar en público de manera efectiva y ganar confianza, así como detalles sobre un concurso de oratoria.
Las 9 reglas de la ORatoria Curso de locucion UCV
Todos los seres humanos debemos aprender a hablar de forma correcta en todo momento. Existen muchos tips y recomendaciones para lograr la atención de las personas que nos escuchan. Sin embargo, existen 9 reglas básicas de la oratoria que se muestran de forma sencilla en esta presentación.
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Zanabria alvarado alejandra-el_lenguaje_de_las_manos.
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The document summarizes a talk on container performance analysis. It discusses identifying bottlenecks at the host, container, and kernel level using various Linux performance tools. It then provides an overview of how containers work in Linux using namespaces and control groups (cgroups). Finally, it demonstrates some example commands like docker stats, systemd-cgtop, and bcc/BPF tools that can be used to analyze containers and cgroups from the host system.
Container Performance Analysis Brendan Gregg, Netflix
The document summarizes a talk on container performance analysis. It discusses identifying bottlenecks at the host, container, and kernel level using various Linux performance tools. It also provides an overview of how containers work in Linux using namespaces and control groups (cgroups). Specifically, it demonstrates analyzing resource usage and limitations for containers using tools like docker stats, systemd-cgtop, and investigating namespaces.
Percona Xtradb Cluster (pxc) 101 percona university 2019
Slides da apresentação sobre Percona Percona XtraDB Cluster
feitos para Percona University São Paulo 2019
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This document discusses memory order consume semantics in C++11. It begins with a recap of acquire and release semantics, then explains that consume semantics are designed to exploit data dependency ordering on weakly-ordered CPUs. However, current compilers like GCC and Clang do not efficiently implement consume, instead using memory barriers. The document ends by discussing proposals to narrow the definition of consume dependencies to guide compiler implementations.
Clug 2012 March web server optimisation
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module4.ppt
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Q2.12: Existing Linux Mechanisms to Support big.LITTLE
Resource: Q2.12
Name: Existing Linux Mechanisms to Support big.LITTLE
Date: 28-05-2012
Speaker: Chris Redpath
Supporting Time-Sensitive Applications on a Commodity OS
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2) TSL improves kernel latency through an accurate timer mechanism called firm timers, a responsive kernel using lock-breaking preemption, and effective scheduling using proportion-based and priority-based algorithms.
3) Evaluation shows TSL reduces timer latency to under 1ms and preemption latency to under 1ms, improving synchronization of media playback under load compared to standard Linux.
MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isola...
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Backing up Wikipedia Databases
Slides presented at Percona Live Europe Open Source Database Conference 2019, Amsterdam, 2019-10-01.
Imagine a world where all Wikipedia articles disappear due to a human error or software bug. Sounds unreal? According to some estimations, it would take an excess of hundreds of million person-hours to be written again. To prevent that scenario from ever happening, our SRE team at Wikimedia recently refactored the relational database recovery system.
In this session, we will discuss how we backup 550TB of MariaDB data without impacting the 15 billion page views per month we get. We will cover what were our initial plans to replace the old infrastructure, how we achieved recovering 2TB databases in less than 30 minutes while maintaining per-table granularity, as well as the different types of backups we implemented. Lastly, we will talk about lessons learned, what went well, how our original plans changed and future work.
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Kvm performance optimization for ubuntu
This document discusses various techniques for optimizing KVM performance on Linux systems. It covers CPU and memory optimization through techniques like vCPU pinning, NUMA affinity, transparent huge pages, KSM, and virtio_balloon. For networking, it discusses vhost-net, interrupt handling using MSI/MSI-X, and NAPI. It also covers block device optimization through I/O scheduling, cache mode, and asynchronous I/O. The goal is to provide guidance on configuring these techniques for workloads running in KVM virtual machines.
cache2k, Java Caching, Turbo Charged, FOSDEM 2015
cache2k is one of the best performing Java in memory cache solution available today. The talk details about the internal design and latest research on the used low overhead eviction algorithm. At the end benchmarks are presented comparing the speed of different cache solutions including EHCache, Infinispan and Google Guava.
µCLinux on Pluto 6 Project presentation
Slides from a talk given to coursemates about my university final year project on the UWE CRTS course which involved porting uCLinux to the Pluto 6 gaming control board.
UKUUG presentation about µCLinux on Pluto 6
Slides from a <a>talk</a> given at the UKUUG 2006 conference derived from my final year project on the UWE CRTS degree which involved porting uCLinux to the Pluto 6 gaming control board.
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Monday, November 16 • 17:20 - 18:05
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Principal engineer at Odin Server Virtualization team, creator and maintainer of the CRIU project. Joined Parallels in 2004 as junior Linux kernel developer, later became kernel team leader. Now works on architecture of the Odin Server products. | | Pavel tweets at @xemulp.
http://dockerconeu2015.sched.org/event/62e6d2ea7380442a48fafaeee26c9842
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http://www.youtube.com/watch?v=0y7a3_Nn2hI
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👉👉 Click Here To Get More Info 👇👇
https://sumonreview.com/ai-fusion-buddy-review
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Top Features to Include in Your Winzo Clone App for Business Growth (4).pptx
Linux Plumbers
- 1. List of topics 1. Control loops in userspace 2. Hierarchical Cgroup support in userland 3. Efficient utilization by overcommitment 4. dcache management 5. Memory controller improvements 6. Checkpoint/restart in the userspace 7. Container in a file 8. Proc fs virtualization 9. Entering a container 10.vzctl for LXC 11.Extending CPU accounting stats
- 2. dcache mgmt 1/2: problems ● Problem 1 ● the number of dentries grows uncontrollable ● Entries can be pinned with low effort, leading to all memory being used and unreclaimable ● Leading to system being unresponsive/stuck ● Problem 2 ● Unfair dentry cache usage distribution among containers
- 3. dcache mgmt 2/2: Solution ● Account for and limit dcache usage per (smth) ● Currently (smth) is superblock ● Shrink dcache per (smth) once limit it hit
- 4. checkpoint-restore 1/3 ● Checkpoint: ● freeze task(s) with freezer cgroup ● read tasks creds via /proc – some patches extending kernel API required ● read tasks regs with PTRACE ● dump tasks mem with PTRASE_SEIZE (new)
- 5. checkpoint-restore 2/3 ● Restore: ● Fork task tree – CLONE_SETPID required ● each task restores its creds – uid/gid – open files – capabilities – etc. ● each task calls execve() on an image – ELF binfmt handler extension required
- 6. checkpoint-restore 3/3 ● TODO: ● some shared resources (fdtable, mm_struct) ● signals handling ● sockets ● container environment – namespaces – IPC – networking
- 7. Container in a file 1/2 ● Currently containers' files reside on host partition and tasks work in plain chroot ● Problems: ● extX journal is performance bottleneck ● hackish live migration (rsync) ● not effective management (tons of small files)
- 8. Container in a file 2/2 ● Solution – loop-like block device ● Parallels implementation – block device, that remaps bio-s with FS bmap call ● Possible implementation – DM extension ● block map provided by userspace ● block map got from FS bmap call