The document discusses the instruction sets and programming of the 8085 microprocessor. It covers the various addressing modes of the 8085 including immediate, register, direct, indirect, and implicit addressing modes. It also describes the instruction format, opcode format, and the different instruction groups of the 8085 such as data transfer, arithmetic, logical, branching, and machine control instructions. For each instruction group, it provides the list of instructions, number of bytes, and number of clock cycles.

1. Instruction Sets and Programming of 8085
Dr. Nilesh Bhaskarrao Bahadure
https://www.sites.google.com/site/nileshbbahadure/home
July 26, 2021
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2. Overview
1 Addressing Modes
Addressing Modes
2 Instruction Format
Instruction Format
Opcode Format
3 Instruction Sets
Data Transfer Instruction
Summary of Data Transfer Group
Arithmetic Group
Summary of Arithmetic Group
Logical Group
Summary of Logical Group
Branching Group
Summary of Branching Group
Miscellaneous or Machine Control Group
Summary of Machine Control Group
4 Thank You
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3. Addressing Modes
1 Immediate addressing mode
2 Register addressing mode
3 Direct addressing mode
4 Register indirect addressing mode
5 Implicit or inherent addressing mode
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4. Instruction Format
An instruction is a command to the microprocessor to perform a given
task on a specified data. Each instruction has two parts: one task to be
performed, called the operation code (opcode), and the second is the data to
be operated on, called the operand. The operand (or data) can be specified
in various ways. It may include 8-bit (or 16-bit) data, an internal register,
a memory location, or 8-bit (or 16-bit) address. In some instructions, the
operand is implicit
1 One-word or 1-byte instructions
2 Two-word or 2-byte instructions
3 Three-word or 3-byte instructions
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5. Opcode Format
Register address
B 000
C 001
D 010
E 011
H 100
L 101
M 110
A 111
Table : Register and their address
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6. Opcode Format...
Register Pair Address
BC 00
DE 01
HL 10
SP or AF 11
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7. Opcode Format...
Instruction Opcode Format
MOV Rd, Rs 0 1 D D D S S S
MVI Rd, DATA 0 0 D D D 1 1 0
LXI Rp, 16 - BIT DATA 0 0 D D 0 0 0 1
ADD R 1 0 0 0 0 S S S
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8. Instructions of 8085
1 Data Transfer Group
2 Arithmetic Group
3 Logical Group
4 Branching Group
5 Machine Control or Miscellaneous Group
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9. Data Transfer Group
1. MOV Rd, Rs
Copy data from source register to destination register
2. MOV Rd, M
Copy the contents of memory location to the destination register.
3. MOV M, Rs
Copy the contents of source register to the memory location
4. MVI Rd, DATA
Move immediate 8 - bit data to the destination register
5. MVI M, DATA
Copy immediate data to the memory location
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10. Data Transfer Group...
6. LXI Rp, 16 - BIT DATA
The instruction loads 16-bit data in the register pair designated in the
operand.
7. LDA 16 - BIT ADDRESS
Copy 8 - bit data from the memory location to the accumulator
8. STA 16 - BIT ADDRESS
Store accumulator to the memory location
9. LDAX Rp
Load accumulator indirect
10. STAX Rp
Store accumulator to the indirect memory location
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11. Data Transfer Group...
11. LHLD 16 - BIT ADDRESS
Load HL register direct
12. SHLD 16 - BIT ADDRESS
Store H and L register direct
13. IN 8-BIT PORT ADDRESS
Input data to the accumulator from 8 - bit port address
14. OUT 8 - BIT PORT ADDRESS
Output data from accumulator the output port
15. PUSH Rp
Push registers pair onto the stack
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12. Data Transfer Group...
16. POP Rp
Pop off stack to register pair
17. SPHL
Load stack pointer register with HL register
18. XCHG
Exchange HL with DE registers pair
19. XTHL
Exchange H and L with top of the stack
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13. Summary of Data Transfer Group
Sr. No. Instruction No. of Bytes No. of Cycles
01 MOV Rd, Rs 01 01
02 MVI Rd, DATA 02 02
03 MOV Rd, M 01 02
04 MOV M, Rs 01 02
05 MVI M, 8 -BIT DATA 02 03
06 LXI Rp, 16 - BIT DATA 03 03
07 LDA 16 - BIT ADDRESS 03 04
08 STA 16 - BIT ADDRESS 03 04
09 LDAX Rp 01 03
10 STAX Rp 01 03
Table : Summary of Data Transfer Group
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14. Summary of Data Transfer Group...
Sr. No. Instruction No. of Bytes No. of Cycles
11 LHLD 16 - BIT ADDRESS 03 05
12 SHLD 16 - BIT ADDRESS 03 05
13 PUSH Rp 01 03
14 POP Rp 01 03
15 XCHG 01 01
16 IN 8 - BIT PORT ADDRESS 02 03
17 OUT 8 - BIT PART ADDRESS 02 03
18 SPHL 01 01
19 XTHL 01 05
Table : Summary of Data Transfer Group
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15. Arithmetic Group
1. ADD R
Add register to accumulator
2. ADD M
Add memory contents to accumulator
3. ADI 8- BIT DATA
Add immediate data to accumulator
4. ADC R
Add register to accumulator with carry
5. ADC M
Add contents of memory to accumulator with carry
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16. Arithmetic Group
6. ACI 8 - BIT DATA
Add immediate data to accumulator with carry
7. DAA
Decimal adjust accumulator
8. SUB R
Subtract register from accumulator
9. SUB M
Subtracts contents of memory from accumulator
10. SUI 8 - BIT DATA
Subtract immediate data from accumulator
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17. Arithmetic Group
11. SBB R
Subtract source and borrow from accumulator
12. SBB M
Subtract contents of memory location and borrow from accumulator
13. SBI 8 - BIT DATA
Subtract 8 - bit immediate data with borrow from accumulator
14. DAD Rp
Add 16 - data from HL register pair with the specified register pair
15. INR R
Increment register by one
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18. Arithmetic Group
16. INR M
The contents of the designated memory are incremented by 1 and the
result is stored in the same place. If the operand is a memory location, its
location is specified by the contents of the HL registers.
17. INX Rp
Increments register pair by one
18. DCR R
Decrement register by one
19. DCR M
Decrement contents of memory by one
20. DCX Rp
Decrement specified register pair by one
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19. Arithmetic Group
Sr. No. Instruction No. of Bytes No. of Cycles
01 ADD R 01 01
02 ADD M 01 02
03 ADI 8 - BIT DATA 02 02
04 ADC R 01 01
05 ADC M 01 02
06 ACI 8 - BIT DATA 02 02
07 DAA 01 01
08 SUB R 01 01
09 SUB M 01 02
10 SUI 8 - BIT DATA 02 02
Table : Summary of Arithmetic Group
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20. Arithmetic Group
Sr. No. Instruction No. of Bytes No. of Cycles
11 SBB R 01 01
12 SBB M 01 02
13 SBI 8 - BIT DATA 02 02
14 DAD Rp 01 03
15 INR R 01 01
16 INR M 01 03
17 INX Rp 01 01
18 DCR R 01 01
19 DCR M 01 03
20 DCX Rp 01 01
Table : Summary of Arithmetic Group
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21. Logical Group
1. ANA R
Logical AND contents of register with accumulator
2. ANA M
Logical ANDing of contents of memory with accumulator
3. ANI 8 - BIT DATA
Logical ANDing 8 - bit immediate data with accumulator
4. ORA R
Logical ORing contents of register with accumulator
5. ORA M
Logical ORing the contents of memory with accumulator
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22. Logical Group...
6. ORI 8 - BIT DATA
Logical ORing 8 - bit immediate data with accumulator
7. XRA R
Exclusive ORed register with accumulator
8. XRA M
Exclusive ORed contents of memory with accumulator
9. XRI 8 - BIT DATA
Logical Exclusive ORing immediate data with accumulator
10. CMP R
Compare register with accumulator
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23. Logical Group
11. CMP M
Compare contents of memory with accumulator
12. CPI 8 - BIT DATA
Compare 8 - bit immediate data with accumulator
13. RLC
Rotate accumulator left
14. RAL
Rotate accumulator left through carry
15. RRC
Rotate accumulator right
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24. Logical Group
16. RAR
Rotate accumulator right through carry
17. CMA
Complement accumulator
18. CMC
Complements carry flag
19. STC
Set carry flag.
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25. Logical Group
Sr. No. Instruction No. of Bytes No. of Cycles
01 ANA R 01 01
02 ANA M 01 02
03 ANI 8 - BIT DATA 02 02
04 ORA R 01 01
05 ORA M 01 02
06 ORI 8 - BIT DATA 02 02
07 XRA R 01 01
08 XRA M 01 01
09 XRI 8 - BIT DATA 01 02
10 CMP R 02 02
Table : Summary of Logical Group
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26. Logical Group
Sr. No. Instruction No. of Bytes No. of Cycles
11 CMP M 01 01
12 CPI 8 - BIT DATA 03 02
13 RLC 02 02
14 RAL 01 03
15 RRC 01 01
16 RAR 01 03
17 CMA 01 01
18 CMC 01 01
19 STC 01 03
Table : Summary of Logical Group
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27. Branching Group
1. JMP 16 - bit address
Unconditional Jump
The program sequence is transferred to the memory location specified by
the 16-bit address given in the operand.
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28. Branching Group
2. JCONDITION 16 bit address
Conditional Jump
The program sequence is transferred to the memory location specified by
the 16-bit address given in the operand based on the specified flag as
described below.
(a) If the given condition in the instruction is satisfied then new number
i.e. 16 bit address given along with the instruction is transferred to
the program counter so microprocessor will jump to the location
whose address given along with the instruction.
(b) If the given condition in the instruction is not satisfied then new
number i.e. 16 bit address given along with the instruction is not
transferred to the program counter instead program counter is
incremented by three (three byte instruction) so the next instruction
is executed in the sequence.
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29. Branching Group...
Instruction Description Flag status
JC 16 - BIT ADDR Jump on carry CY = 1
JNC 16 - BIT ADDR Jump on no carry CY = 0
JZ 16 - BIT ADDR Jump on zero ZF = 1
JNZ 16 - BIT ADDR Jump on no zero ZF = 0
JPE 16 - BIT ADDR Jump on parity even PF = 1
JPO 16 - BIT ADDR Jump on parity odd PF = 0
JP 16 - BIT ADDR Jump on positive SF = 0
JM 16 - BIT ADDR Jump on minus SF = 1
Table : Conditional Jump Instruction
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30. Branching Group...
3. CALL 16 - BIT ADDR
Unconditional Call to the subprogram
4. CCONDITION 16 - BIT ADDR
Conditional Call to the subprogram
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31. Branching Group...
Instruction Description Flag status
CC 16 - BIT ADDR Call on carry CY =1
CNC 16 - BIT ADDR call on no carry CY = 0
CZ 16 - BIT ADDR Call on zero ZF = 1
CNZ 16 - BIT ADDR Call on no zero ZF = 0
CPE 16 - BIT ADDR Call on parity even PF = 1
CPO 16 - BIT ADDR Call on parity odd PF = 0
CP 16 - BIT ADDR Call on positive SF = 0
CM 16 - BIT ADDR Call on minus SF = 1
Table : Conditional Call Instruction
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32. Branching Group...
5. RET
Return from subprogram / subroutine unconditionally
6. RCONDITION
Return from subprogram / subroutine conditionally
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33. Branching Group...
Instruction Description Flag status
RC Return on carry CY = 1
RNC Return on no carry CY = 0
RZ Return on zero ZF = 1
RNZ Return on no zero ZF = 0
RPE Return on parity even PF = 1
RPO Return on parity odd PF = 0
RP Return on positive SF = 0
RM Return on minus SF = 1
Table : Conditional Return Instruction
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34. Branching Group...
7. PCHL
Load program counter (PC) with HL contents
8. RSTn (n = 0 to 7)
Restart The RST instruction is equivalent to a 1-byte call instruction to
one of eight memory locations depending upon the number. The
instructions are generally used in conjunction with interrupts and inserted
using external hardware. However these can be used as software
instructions in a program to transfer program execution to one of the eight
locations. The addresses are:
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35. Branching Group...
Instruction Restart Address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
Table : Conditional Return Instruction
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36. Branching Group
Sr. No. Instruction No. of Bytes No. of Cycles
01 JMP 16 - BIT ADDRESS 03 03
02 JCONDITION 16- BIT ADDRESS 03 03 / 02
03 CALL 16 - BIT ADDRESS 03 05
04 CCONDITION 16 - BIT ADDRESS 03 05 / 02
05 RET 01 03
06 RCONDITION 01 03 / 01
07 PCHL 01 01
08 RSTn 01 03
Table : Summary of Branching Group
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37. Machine Control Group
1. NOP
No operation
2. HLT
Halt and enter wait state
3. DI
Disable interrupts
4. EI
Enable interrupts
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38. Machine Control Group...
5. SIM
Set interrupt mask
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5
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39. Machine Control Group...
5. RIM
Read interrupt mask
D7 D6 D5 D4 D3 D2 D1 D0
SID I7 I6 I5 IE M7.5 M6.5 M5.5
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40. Machine Control Group
Sr. No. Instruction No. of Bytes No. of Cycles
01 NOP 01 01
02 HLT 01 01
03 DI 01 01
04 EI 01 01
05 SIM 01 01
06 RIM 01 01
Table : Summary of Machine Control Group
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41. Thank you
Please send your feedback at nbahadure@gmail.com
For more details and updates kindly visit
https://sites.google.com/site/nileshbbahadure/home
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