1) The document presents a design for a 1-bit full adder cell that implements power gating techniques to reduce leakage power and ground bounce noise for use in mobile applications. 2) A sleep transistor is added between the actual ground rail and circuit ground to cut off the leakage path during sleep mode. 3) Stacking power gating with a delayed select input is also implemented and shown to further minimize both leakage power and ground bounce noise. 4) Simulation results demonstrate that the proposed design significantly reduces active power and standby leakage power compared to a conventional CMOS full adder cell.

1. 4th INTERNATIONAL SET CONFERENCE
PRESENTATION
ON
Implementation of Power Gating Technique in CMOS Full Adder Cell to
Reduce Leakage Power and Ground Bounce Noise for Mobile
Application
Under guidance of
PRESENTED BY :
Dr. HARISH M. KITTUR
VLSI Division, SENSE,
VIT University
AMIT BAKSHI ( 11MVD0055)

2. Mobile phone when operates in stand-by mode still results
in the leakage current which though is smaller in
magnitude but depletes the battery charge over long period
of time. To reduce this leakage current and the ground
bounce noise which occurs during transition from sleep to
active mode, low leakage adder cells along with stacking
power gating technique has been implemented in this paper.
Simulation is done using cadence spectre 90nm CMOS
tech. at 1V supply voltage.

3.  Adder cells are used to reduce power consumption.
 Mobile phone in standby mode results in leakage current
which depletes battery charge.
 Power gating technique is used to reduce leakage power where
sleep transistor is added b/w actual ground rail and virtual
ground.
 Sleep transistor is turned off in sleep mode to cut off the
leakage path.
 Stacking power gating technique is used to reduce Ground
bounce noise.

4. PROPOSED FULL ADDER DESIGN
Conventional CMOS full adder

5.  This is base adder cell throughout this paper and all
comparisons have been done with this adder.
 It consists of 28 CMOS transistors which incorporates pull up
and pull down n/w to produce desired outputs.
 PMOS to NMOS ratio is 2 for an inverter.
 Remaining blocks follows the same ratio when considered
equivalent inverters.
 This ratio doesn’t provide best results for standby leakage
power.

6. Full adder (Design1) circuit with sleep transistor

7. 1 bit full adder (Design2) circuit with sleep transistor

8. Design 2 with stacking power gating technique (proposed.)
Modified Design 2

9.  Initially, MSL1 and MSL2 are kept off to
reduce leakage curent.
 The delay is introduced to SELECT input so as
to keep the Ground bounce noise minimum.
 The value of delay is calculated by taking the
half of the oscillation period of RLC circuit.
 The values taken were as R=0.217ohm,
L=8.18nH and C=5.32pF.
 The formula used to calculate time period is
given by

10. Functional simulation of Conventional CMOS 1-bit Full adder cell

11. Functional simulation of Full adder (Design1) circuit with sleep
transistor

12. Functional simulation of 1-bit Full adder (Design2) circuit with
sleep transistor

13. Functional simulation of Design 2 with stacking power gating
technique.

14. TABLE 1.
ACTIVE POWER DISSIPATION OF 1-BIT FULL ADDER CELL
Design2 with
Stacking Power
Conventional
gating
Circuit CMOS Design 1 Design 2
Active Power
(μw) 7.56 5.14 2.57 3.17

15. Input Vector Standby leakage Power(nWatt)
Conventional CMOS Design 1 Design 2 Design 2 with Stacking
Adder Cell power gatting
000 64.72 13.21 8.64 7.69
001 69.62 14.91 10.47 6.25
010 87.45 17.24 11.78 5.28
011 86.32 19.41 14.27 6.69
100 63.24 18.71 13.71 5.31
101 60.21 15.62 12.54 7.18
110 66.55 14.67 11.11 6.92
111 61.28 10.14 8.49 4.67

16. TABLE 3.
PROPOGATION DELAY OF 1-BIT FULL ADDER CELL
Conventional CMOS Modified
Input Vector Adder (ps) Design 1(ps) Design 2(ps) Design2(ps)
A B C SUM CARRY SUM CARRY SUM CARRY SUM CARRY
0 p 0 93.65 d 78.55 d 82.67 d 81.57 d
0 p 1 82.36 59.58 94.52 68.92 88.54 66.71 88.32 68.41
1 p 0 77.44 63.22 102.22 78.15 107.25 75.45 105.26 71.35
1 p 1 83.92 d 64.25 d 72.11 d 79.21 d
p 0 0 95.25 d 86.33 d 79.57 d 75.57 d
p 0 1 84.36 62.58 94.64 77.32 98.44 70.17 97.24 69.24
p 1 0 88.44 58.12 101.11 74.75 87.15 73.61 87.95 70.77
p 1 1 91.12 d 69.25 d 72.21 d 71.21 d
0 0 p 90.21 d 81.22 d 71.84 d 70.54 d
0 1 p 85.88 60.31 98.54 70.24 91.27 64.25 94.37 64.21
1 0 p 81.37 64.27 109.67 76.54 124.25 71.01 122.35 70.24
1 1 p 87.63 d 72.55 d 82.35 d 82.44 d

17. showing ground bounce noise in design2 with stacking power gating technique without delay

18. showing ground bounce noise in design2 with stacking power gating technique with
delay

19.  In this paper 1-bit full adder cell with power gating technique is
implemented where a sleep transistor is added between actual ground rail
and circuit ground. The device is turned off during sleep mode to cut-off
the leakage path. For optimal performance, stacking power gating
technique has been implemented where SELECT input to stacked sleep
transistor with delta T delay further minimizes the leakage power and
ground bounce noise. The comparison of active power, standby leakage
power is done and it’s observed that power is greatly reduced as we move
from conventional CMOS full adder cell to Modified Design2. The ground
bounce noise is compared for Modified Design2 without delay and with
delay and it is reduced in the latter case. The implemented 1-bit full adders
are designed using 90nm technology and operated supply voltage of 1V.

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21. Thank you