Cmos Arithmetic Circuits

7,415 views

Published on

This is to study about Cmos Arithmetic Circuits..ok enjoy reading

Published in: Technology, Business
0 Comments
4 Likes
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total views
7,415
On SlideShare
0
From Embeds
0
Number of Embeds
31
Actions
Shares
0
Downloads
243
Comments
0
Likes
4
Embeds 0
No embeds

No notes for slide

Cmos Arithmetic Circuits

  1. 1. CMOS Arithmetic Circuits
  2. 2. Multiplication of numbers
  3. 3. Datapath circuit techniques for adders
  4. 4. Binary adder
  5. 5. Binary adder
  6. 6. Special trick for reducing No of transistor <ul><li>Cout = AB + C IN .(A + B) </li></ul><ul><li>SUM = ABC CN + C ’ OUT (A + B + CIN) </li></ul><ul><li>The advantage of these type realization is that transistor count is less as compared to earlier realization using expression of slide 5. </li></ul>
  7. 7. CMOS full adder
  8. 8. Mirror Adders <ul><li>As discussed is class, Mirror adder circuit is having symmetrical N block and P block. </li></ul>
  9. 9. Ripple carry adder
  10. 10. Pipelined adder
  11. 11. Carry bypass adder
  12. 12. Carry bypass adder
  13. 13. Linear carry select adder
  14. 14. Linear carry select adder: critical path
  15. 15. Carry look-ahead adder
  16. 16. Carry look-ahead circuit structures
  17. 17. Carry save (CSA) and carry propagate (CPA) adders
  18. 18. Adder delays
  19. 19. Adder delays summary
  20. 20. Datapath circuit techniques for multipliers
  21. 21. Multiplier definition
  22. 22. Binary multiplication
  23. 23. Indirect multiplication
  24. 24. Array multiplier
  25. 25. MxN array multiplier critical path
  26. 26. Carry ripple vs. carry save array multiplier
  27. 27. Carry save multiplier
  28. 28. Adder cells in array multiplier
  29. 29. Array multiplier floorplan
  30. 30. Wallace tree multiplier
  31. 31. Wallace tree multiplier
  32. 32. Wallace tree multiplier
  33. 33. Dadda tree multiplier
  34. 34. Serial-serial multiplier
  35. 35. Serial-parallel multiplier
  36. 36. Parallel vs. serial multipliers
  37. 37. Parallel vs. serial multipliers
  38. 38. Multiplier performance
  39. 39. Multiplier performance
  40. 40. Multiplier summary
  41. 41. Other datapath elements
  42. 42. Binary shifter
  43. 43. Barrel shifter
  44. 44. 4x4 barrel shifter
  45. 45. Logarithmic shifter
  46. 46. Power considerations in datapath structures
  47. 47. Reducing supply voltage
  48. 48. Reducing supply voltage
  49. 49. Architecture trade-offs: reference datapath
  50. 50. Parallel datapath
  51. 51. Pipelined datapath
  52. 52. Datapath architecture summary
  53. 53. Glitching in NOR chain
  54. 54. Glitching in RCA
  55. 55. Switching activity in adders
  56. 56. Switching activity in multipliers
  57. 57. Layout strategy for datapath
  58. 58. Layout strategy for datapaths
  59. 59. Cell area: 2 vs. 3 metal layer process
  60. 60. Summary

×