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Jayaprakash Nagaruru
Jayaprakash Nagaruru

Efficient design implementation of any ASIC requires an appropriate style which meet the design goals Area Power Speed Multi-dimensional Trade off

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A SEMINAR ON LOW POWER AND AREA EFFICIENT CARRY SELECT ADDER BY Jayaprakash Nagaruru
Objective To design a Carry Select Adder(CSLA) with a optimum utilization of area and power Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 2
Agenda • Introduction • Carry Select Adder • Delay and Area Evaluation • Principle Behind Modification • Modified CSLA • Delay and Area Evaluation • Implementation Results • Conclusion Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 3
Introduction • Efficient design implementation of any ASIC requires an appropriate style which meet the design goals  Area  Power  Speed • Multi-dimensional Trade off Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 4
Carry Select Adder • Ripple carry adder & MUX Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 5
Regular CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 6
Delay and Power Evaluation Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 7
Contd… Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 8
Regular CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 9
Principle Behind Modification • Binary to Excess-1 Convertor Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 10
CSLA with BEC Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 11
Modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 12
Delay and Power Evaluation of modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 13
Comparison Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 14
Implementation Results • Typical ASIC flow Using 0.18u Technology for regular and modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 15
Graphical Analysis Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 16
Conclusion No. of Bits Area Reduction (%) 8 9.7 16 15 32 16.7 64 17.4 Power Reduction (%) 7.6 10.56 13.63 15.46 Delay Overhead (%) 14 9.8 6.7 3.76 Power Delay Product(%) 5.2 1.76 8.18 12.28 Area Delay Product(%) 2.9 6.7 11 14.4 • Despite with a little delay overhead a optimized carry select adder has been designed Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 17
Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 18
References Bibliography • IEEE 2012 paper on Low Power & Area Efficient CSLA by B Ram Kumar & H M Kittur • J M Rabaey Digital Integrated Circuits • IJCE 2012 paper on VLSI Realization Of Fast Carry Adder in Binary Excess by Santhosh Kannan and Bhanumathi Webography • http://en.wikipedia.org/wiki/Ca rry-select_adder • http://ieeexplore.ieee.org/xpl /login.jsp?tp=&arnumber=540 7919&url=http%3A%2F%2Fiee explore.ieee.org%2Fxpls%2Fab s_all.jsp%3Farnumber%3D540 7919 Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 19
Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 20

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Csla 130319073823-phpapp01-140821210430-phpapp02

  • 1. A SEMINAR ON LOW POWER AND AREA EFFICIENT CARRY SELECT ADDER BY Jayaprakash Nagaruru
  • 2. Objective To design a Carry Select Adder(CSLA) with a optimum utilization of area and power Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 2
  • 3. Agenda • Introduction • Carry Select Adder • Delay and Area Evaluation • Principle Behind Modification • Modified CSLA • Delay and Area Evaluation • Implementation Results • Conclusion Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 3
  • 4. Introduction • Efficient design implementation of any ASIC requires an appropriate style which meet the design goals  Area  Power  Speed • Multi-dimensional Trade off Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 4
  • 5. Carry Select Adder • Ripple carry adder & MUX Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 5
  • 6. Regular CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 6
  • 7. Delay and Power Evaluation Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 7
  • 8. Contd… Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 8
  • 9. Regular CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 9
  • 10. Principle Behind Modification • Binary to Excess-1 Convertor Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 10
  • 11. CSLA with BEC Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 11
  • 12. Modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 12
  • 13. Delay and Power Evaluation of modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 13
  • 14. Comparison Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 14
  • 15. Implementation Results • Typical ASIC flow Using 0.18u Technology for regular and modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 15
  • 16. Graphical Analysis Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 16
  • 17. Conclusion No. of Bits Area Reduction (%) 8 9.7 16 15 32 16.7 64 17.4 Power Reduction (%) 7.6 10.56 13.63 15.46 Delay Overhead (%) 14 9.8 6.7 3.76 Power Delay Product(%) 5.2 1.76 8.18 12.28 Area Delay Product(%) 2.9 6.7 11 14.4 • Despite with a little delay overhead a optimized carry select adder has been designed Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 17
  • 18. Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 18
  • 19. References Bibliography • IEEE 2012 paper on Low Power & Area Efficient CSLA by B Ram Kumar & H M Kittur • J M Rabaey Digital Integrated Circuits • IJCE 2012 paper on VLSI Realization Of Fast Carry Adder in Binary Excess by Santhosh Kannan and Bhanumathi Webography • http://en.wikipedia.org/wiki/Ca rry-select_adder • http://ieeexplore.ieee.org/xpl /login.jsp?tp=&arnumber=540 7919&url=http%3A%2F%2Fiee explore.ieee.org%2Fxpls%2Fab s_all.jsp%3Farnumber%3D540 7919 Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 19
  • 20. Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 20