The document proposes a novel unsymmetrical FinFET structure and simulates its performance using TCAD simulation software. Key findings include: 1) The unsymmetrical FinFET with a Fin width of 9nm shows an improved Ion/Ioff ratio of around 103 compared to symmetrical FinFET structures. 2) Transfer characteristics of the unsymmetrical nFinFET show better subthreshold characteristics compared to underlap and overlap FinFET structures. 3) A CMOS inverter designed using the optimized nFinFET and pFinFET shows near ideal transient and DC responses.

1. Performance Enhnaced Unsymmetrical FinFET and its
Applications
Govind S Patel1
, Suman L Tripathi2
, Sandhya Awasthi3
1,2Lovely professional University, Phagwara Punjab
3KEC, Gaziabaad, U P
Abstract: A steep subthershold slope novel
usymmetrical FinFET is proposed for gate lenght 9nm
with improved performance in terms of Ion/Ioff ratio in
comparison to existing symmetrical structure.
Proformance is furture optimised in terms of doping
variations and under lap behaviour of FinFET. High-K
dielectric material oxide and metal gate contact of high
work function incorporated and performance compared.
pFinFET and nFinFET both simulated togather to
obtain ideal characteristics required to match in CMOS
technology. 2D/3D Visual TCAD device simulator
utilised in design of all FinFET structures.
Keyword: Unsymmetrical FinFET, Subthreshold slope,
Underlap Gate
I. Introduction
FinFET is potential candidate to meet scalling needs
below 20nm technology node due to its excellent
subthreshold characteristics and high on and off state
current[1-4]. Increse in channel lenght vertically
improves the drive current 3 fold and made it suitable
for high speed operations. In Gate all around the fin
increases Gate control over the channel, made it more
compatible in CMOS as compared to bulk MOSFET
strucures[5]. Introduction to High-k dielectric materials
further improves FinFET performance and reduces
drain induced barrier lowering[6-7]. Optimum channel/
bulk region doping is key parameter to get enhanced
subtherhold performance of FinFET with similar
domensions on SOI wafer or Bulk Structure[8]. FinFET
with bottom spacer exploits shallower junction
behaviour to reduce off sate leakage and simultaneously
use of high doping in inactive fin contribute to the
advantages of punchthrough stopper [9-10]. Reliability
and process related issues still serious concern for
FinFET structures [11-13] in terms of future scalability
and performance parameters. Metal gate work function
variability of pFinFET had been compared for Si and
Ge interface to further optimised pFinFET performance
[14]. Environmental variability such as temperature was
discussed mainly to check variations in fin width, fin
height, gate length, metal work function and oxide
thickness [15]. Tapered Fin Shape that is different width
at top and bottomof Fin, also plays an important role in
ON and OFF characteristics of transistors for some
specified applications [16]. Difficulties and doping
related variations had been minimised through junction-
less FinFET structures and performance enhance to get
high value of Ion/Ioff ratio[17-18]. Other material such
Ge introduced to make heterojunction Si, Ge interface
to get better subthershold performance and
improvement in subthreshold parameters [19]. The
position of Fin based channel from source and drain
side could be other parameter for future investigations.
The important concern is to get High value of Ion/Ioff
current ratio as well as suppressed short channel effects
(SCE). The design must be compatible for CMOS
based circuit applications.
In this paper a novel unsymmetrical FinFET structure
proposed and performance is optimised and compared
with similar symmetrical FinFET structures in terms of
doping variations, gate contact and oxide material.
Unsymmetrical pFinFET, nFinFET for 9nm fin width
designed on Visual TCAD 2D/3D device simulator and
performance compared. Further a CMOS inverter
designed using these n and pFinFETs to get ideal
characteristics. It is observed that proposed FinFET
structres are compatible for analog and digital
applications. Finaaly nFinFET and pFinFET is
implemented as COMS inverter as a devices and
showing near to ideal DC and transient response.
II. Device Design and Structure
Visual TCAD, 2-Dimensional device simulator is used
to design a novel unsymmetrical FinFET and optimized
device performance in low operating voltage regions.
The body thickness varied between 10nm, Source/
Drain doping kept in range varied between 1e18-
1e20cm-3 keeping channel doping constant 1e16cm-3.
High–K Dielectric material HfO2(25) replacing
SiO2(3.9) is preferred under gate contact. Dielectric
constant mainly affects off state current but on state
current have less variation which further supports the
steepness of subthreshold curve. A 2-D unsymmetrical
FET is shown in Fig.1 is designed for 10nm body
thickness 15nm gate length and source/channel/drain
length 10nm/20nm/10nm respectively. Fin Thickness

2. (Wfin) is varied between 8-11nm with Hfin 20nm. Figure
2 shows a symmetrical underlap FinFET structure
similar in dimension as in Fig.2.
Fig.1 2D Unsymmetrical FinFET
Fig.2 2D symmetrical underlap FinFET structure
Fig. 3 2-D view of CMOS based upon FinFET structure
of nFinFET and pFinFET
Finally a FinFET based cmos structure proposed, is
depicted in Fig.3 to observe the compatibility of
proposed unsymmetrical nFinFET and pFinFET for
CMOS technology. The channel potential of
unsymmetrial FinFET depicted in Fig4. The figure
shows that channel potential increases with gate
voltage. Fig.5 shows energy band diagram of
unsymmetrical FinFET. The electric Field of
unsymmetrical FinFET described in Fig.6. It shows that
electric field decreases with increase in gate voltage.
Fig. 4 Channel Potential of Unsymmetrical FinFET
along x-axis
Fig.5 Energy band diagram of Unsymmetrical FinFET
along x-axis

3. Fig.6 Electric Field of Unsymmetrical FinFET along x-
axis
III. Results and Discussion
The Proposed unsymmetrical nFinFET designed on
visual TACD is simulated for gate voltage Vgs variation
(0-1)V keeping drain voltage constant. Fig.7 shows
transfer characteristics of unsymmetrical nFinFET with
constant channel doping 1e16cm-3. This shows a good
improvement in Ion/Ioff ratio ~103 of overlap FinFET
from source side only even with Fin width 9nm. Fig.8
shows variton in Id vs Vgs characteritics depending on
Fin width variation between 9-11nm. This describes
that unsymmetrical FinFET with 9nm Fin width ahs
more steep subthershold characteristic and better Ion/Ioff
ratio. Fig.9 depicts the Transfer characteristics of
unsymmetrical nFinFET with under and overlap
FinFET(either from source side or both source/drain
side ) for Channel doping 1e18cm-3. The unsymmetrical
FinFET have better characteristics as compared all other
FinFET underalp and overlap structures. Fig.10 shows
the comparison of unsymmetrical nFinFET for different
channel doping that shows a symmetrical change in on
and off current keeping current ratio nearly equal. With
increase in doping increases both on and off state
current. So the overall effect on curret ratio is nullified.
Fig.11 shows Id versus Vds characteristics of proposed
unsymmetrical FinFET. It shows that drain current
increases with different values of gate voltage and
matches with ideal behaviour.
Fig.7 Id vs Vgs characteristics of nFinFET (Channel
doping 1e18cm-3)
Fig.8 Id vs Vgs characteristics of nFinFET with
different Fin Width (Channel doping 1e18cm-3)
Fig.9 Transfer characteristics comparing unsymmetrical
FinFET with under and overlap FinFET( Channel
doping 1e18cm-3)

4. Fig.10 Id vs Vgs characteristics of unsymmetrical
nFinFET with different channel doping
nFinFET and pFinFET transfer characteristics shown in
Fig12, compared and it has been observed that the drain
current for both are matching together in on/off state
which a desirable requirement of any CMOS
implementation. A CMOS design based on nFinFET
and pFinFET is further simulated as inverter shown in
Fig.13. The transient response for pulse input in
proposed inverter shown in Fig.14 is almost similar to
ideal behaviour but with the slight difference in output
voltage level.
Fig. 11 Id vs Vds of unsymmetrical FinFET
Fig.12 Comparison of transfer characteristics of
nFinFET and pFinFET with Fin Width 9nm
Fig.13 nFinFET and pFinFET implementation in
CMOS inverter
Fig.14 Transient response of proposed inverter using
unsymmetrical FinFET

5. Fig.15 Inverter Transfer characteristic for Vgs variation
(0-1V)
Fig.15 describes the DC transfer characteristics of
proposed inverter showing near to ideal nature but with
small variation in output voltage level from the required
level.
IV. Conclusions and Future scope
The proposed unsymmetrical Fine structure has good
value of Ion/I off ratio 104 and sub threshold slope of
68mV/V. pined and n-Fine design matches their IV
characteristics, therefore can be easily implemented in
comes inverter circuit. The Id versus vs. characteristics
of proposed ninety and pined is correctly matching. The
proposed unsymmetrical Fine can be further utilized to
design SRAM and DRAM cell.
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