A researcher developed a radix-8 divider for binary64 division units to improve energy efficiency at high clock rates. Simulation results showed the radix-8 divider requires less energy per division than radix-4 or radix-16 approaches. The researcher used Xilinx 10.1 and ModelSim 6.4b tools and VHDL/Verilog languages to develop and test the minimally redundant radix-8 divider.

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Performance/Power Space Exploration for Binary64 Division Units
Abstract
The digit-recurrence division algorithm is used in several high-performance processors because
it provides good tradeoffs in terms of latency, area and power dissipation. In this work we
develop a minimally redundant radix-8 divider for binary64 (double-precision) aiming at
obtaining better energy efficiency in the performance-per-watt space. The results show that the
radix-8 divider, when compared to radix-4 and radix-16 units, requires less energy to complete a
division for high clock rates.
Tools :
 Xilinx 10.1
 Modelsim 6.4b
Languages :
 VHDL / Verilog HDL