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Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Area-Efficient Fixed-Width Squarer with
Dynamic Error-Compensation Circuit
Abstractโ€”This brief proposes a dynamic error-compensation circuit for a fixed-
width squarer based on the Booth folding technique. According the expected value
of the partial productthrough the Booth encoder, a closed form of the compensated
value can be derived, including column information that ca n be used to improve
accuracy. The proposed compensation circuit was derived using a mathematical
probability model, which means that it is easily implemented for bit-lengths of 32,
64, and longer. Implemented using the TSMC 0.18-_m CMOS process, the
proposed 32-bit squarer achieved an operation frequency of 50 MHz and g ate
count of 3.7 k. Compared with previous solutions, the proposed squarer achieves
the best tradeoff between area-efficiency, cost, and accuracy.
SOFTWARE REQUIREMENT:
๏‚ท ModelSim6.4c.
๏‚ท Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
๏‚ท FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com
Area efficient fixed-width squarer with dynamic error-compensation circuit

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Area efficient fixed-width squarer with dynamic error-compensation circuit

  • 1. Logic Mind Technologies Vijayangar (Near Maruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 Area-Efficient Fixed-Width Squarer with Dynamic Error-Compensation Circuit Abstractโ€”This brief proposes a dynamic error-compensation circuit for a fixed- width squarer based on the Booth folding technique. According the expected value of the partial productthrough the Booth encoder, a closed form of the compensated value can be derived, including column information that ca n be used to improve accuracy. The proposed compensation circuit was derived using a mathematical probability model, which means that it is easily implemented for bit-lengths of 32, 64, and longer. Implemented using the TSMC 0.18-_m CMOS process, the proposed 32-bit squarer achieved an operation frequency of 50 MHz and g ate count of 3.7 k. Compared with previous solutions, the proposed squarer achieves the best tradeoff between area-efficiency, cost, and accuracy.
  • 2. SOFTWARE REQUIREMENT: ๏‚ท ModelSim6.4c. ๏‚ท Xilinx 9.1/13.2. HARDWARE REQUIREMENT: ๏‚ท FPGA Spartan 3. PROJECT FLOW: First Review: Literature Survey Paper Explanation Design of Project Project Enhancement explanation Second Review: Implementing 40% of Base Paper Third Review Implementing Remaining 60% of Base Paper with Future Enhancement (Modification) For More Details please contact Logic Mind Technologies Vijayangar (NearMaruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 Mail: logicmindtech@gmail.com